---
- branch: MAIN
  date: Sat Aug 27 17:05:58 UTC 2011
  files:
  - new: '1.2'
    old: '1.1'
    path: src/sys/arch/evbmips/conf/LOONGSON
    pathrev: src/sys/arch/evbmips/conf/LOONGSON@1.2
    type: modified
  - new: '1.1026'
    old: '1.1025'
    path: src/sys/conf/files
    pathrev: src/sys/conf/files@1.1026
    type: modified
  - new: '1.94'
    old: '1.93'
    path: src/sys/dev/ata/ata_wdc.c
    pathrev: src/sys/dev/ata/ata_wdc.c@1.94
    type: modified
  - new: '1.263'
    old: '1.262'
    path: src/sys/dev/ic/wdc.c
    pathrev: src/sys/dev/ic/wdc.c@1.263
    type: modified
  id: 20110827T170558Z.468adc2d09b876116a56c325ba1f5c02d99f56fe
  log: |
    The loongon2f+cs5526+jmicron PATA->SATA bridge cause an interresting issue:
    1) because the CS5536 is not associated with a x86 CPU, interrupts are not
      ack'ed as it expects so interrupts cannot configured as edge-triggered
      (as is expected for a PCIIDE in compat mode)
    2) the PATA->SATA bridge ignores the WDC_IDS (interrupt disable bit) so
      the PATA IRQ line gets asserted when resetting or running some polled
      commands. It also wrongly asserts IRQ when the (nonexistent) slave
      device is selected
    2) wouldn't be an issue with edge-triggered interrupt because we would
       get a spurious interrupt and continue operation, a new interrupt only shows
       up when the PATA IRQ line goes low and high again. But because of 1),
       we get an unclearable interrupt instead, and the system loops on the
       interrupt handler.

    To workaround this, introduce a WDC_NO_IDS compile option which runs
    all polled commands (including reset) at splbio() and without sleeps,
    so that the controller's interrupt is effectively disabled and
    won't be reenabled before the interrupt can be cleared.

    The conditions triggering this problem are speficic enough to handle
    this via a compile-time option; no need for a run-time (e.g. a
    config(9), device property or callback to disable interrupts) solution.
  module: src
  subject: 'CVS commit: src/sys'
  unixtime: '1314464758'
  user: bouyer