Now
MAIN commitmail json YAML
src/sys/arch/arm/arm/cpufunc.c@1.139
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diff
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nxr@1.139
src/sys/arch/arm/arm32/cpu.c@1.100 / diff / nxr@1.100
src/sys/arch/arm/include/cpufunc.h@1.67 / diff / nxr@1.67
src/sys/arch/arm/arm32/cpu.c@1.100 / diff / nxr@1.100
src/sys/arch/arm/include/cpufunc.h@1.67 / diff / nxr@1.67
Keep track of what each cache is (VIVT/VIPT/PIPT).
cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache
cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache