---
- branch: MAIN
  date: Sun Apr 12 20:00:42 UTC 2015
  files:
  - new: '1.5'
    old: '1.4'
    path: src/sys/arch/arm/omap/tifb.c
    pathrev: src/sys/arch/arm/omap/tifb.c@1.5
    type: modified
  id: 20150412T200042Z.915182ddac174e44da43e8da41325dd34690918a
  log: |
    flushing the framebuffer from interrupt has several problems:
    - As pointed out by Jared McNeill, this doesn't work for cold
      or ddb. Some specific handing for these cases would be needed,
      but there's no easy way to know if we're in ddb or not.
    - periodic bus_dmamap_sync() of the whole framebuffer isn't cheap (about
      3% CPU constant on the beaglebone back).

    instead map the framebuffer BUS_DMA_PREFETCHABLE (undocumented flag, but
    is MI and properly handled by arm). This allows write-combining,
    which, in addition with a shadow framebuffer for rasops(9) gives
    a good performance boost too (difference with the cached+sync from intr
    isn't noticeable on a boot sequence).
    For X11, the framebuffer was already mapped BUS_DMA_PREFETCHABLE.
    A few tests shows that mapping it fully cached doesn't make a noticeable
    difference either (with or without xorg's shadow framebuffer).
  module: src
  subject: 'CVS commit: src/sys/arch/arm/omap'
  unixtime: '1428868842'
  user: bouyer