---
- branch: MAIN
  date: Sat Oct 17 15:02:55 UTC 2015
  files:
  - new: '1.38'
    old: '1.37'
    path: src/sys/arch/arm/allwinner/awin_board.c
    pathrev: src/sys/arch/arm/allwinner/awin_board.c@1.38
    type: modified
  id: 20151017T150255Z.5a9aaa8315e62ddb4bf89508f3c2dcfbc1cbc225
  log: |
    The A20 manual says that the pll6 output is (AWIN_REF_FREQ * n * k) / 2,
    not (AWIN_REF_FREQ * n * k) / m (m is only used for the SATA clock).
    On the boards I tested, m happens to be 2 so the correct value was returned
    anyway.
  module: src
  subject: 'CVS commit: src/sys/arch/arm/allwinner'
  unixtime: '1445094175'
  user: bouyer