Pull up following revision(s) (requested by msaitoh in ticket #715):

sys/arch/x86/include/cacheinfo.h: revision 1.24-1.26
usr.sbin/cpuctl/arch/i386.c: revision 1.81-1.84

- Parse the TLB info from `cpuid leaf 18H' on Intel processor. Currently,
  this change doesn't decode perfectly.  Tested with Gemini Lake. It has
  two L2 Shared TLB. One is 4MB and another is 2MB/4MB but former isn't
  printed yet:
        cpu0: ITLB 1 4KB entries 48-way
        cpu0: DTLB 1 4KB entries 32-way
        cpu0: L2 STLB 8 4MB entries 4-way
  Need some rework for struct x86_cache_info.
- Use aprint_error_dev() for error output.
Calculate way and number of entries correctly from CPUID leaf 18H.
Add yet another Shared L2 TLB (2M/4M pages).
XXX need redesign.

Add 3way and 6way of L2 cache or TLB on AMD CPU.
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.

From the latest Intel SDM:
- Add Xeon Phi 7215, 7285 and 7295
- Add Coffee Lake

(martin)