---
- branch: netbsd-8
  date: Mon Apr  9 18:04:32 UTC 2018
  files:
  - new: 1.22.10.2
    old: 1.22.10.1
    path: src/sys/arch/x86/include/cacheinfo.h
    pathrev: src/sys/arch/x86/include/cacheinfo.h@1.22.10.2
    type: modified
  - new: 1.74.6.3
    old: 1.74.6.2
    path: src/usr.sbin/cpuctl/arch/i386.c
    pathrev: src/usr.sbin/cpuctl/arch/i386.c@1.74.6.3
    type: modified
  id: 20180409T180432Z.69f67bf83e77641b16323920d6d31bfafdafd253
  log: "Pull up following revision(s) (requested by msaitoh in ticket #715):\n\n\tsys/arch/x86/include/cacheinfo.h:
    revision 1.24-1.26\n\tusr.sbin/cpuctl/arch/i386.c: revision 1.81-1.84\n\n- Parse
    the TLB info from `cpuid leaf 18H' on Intel processor. Currently,\n  this change
    doesn't decode perfectly.  Tested with Gemini Lake. It has\n  two L2 Shared TLB.
    One is 4MB and another is 2MB/4MB but former isn't\n  printed yet:\n        cpu0:
    ITLB 1 4KB entries 48-way\n        cpu0: DTLB 1 4KB entries 32-way\n        cpu0:
    L2 STLB 8 4MB entries 4-way\n  Need some rework for struct x86_cache_info.\n-
    Use aprint_error_dev() for error output.\n Calculate way and number of entries
    correctly from CPUID leaf 18H.\n Add yet another Shared L2 TLB (2M/4M pages).\nXXX
    need redesign.\n\n Add 3way and 6way of L2 cache or TLB on AMD CPU.\n AMD L3 cache
    association bitfield is not 8bit but 4bit like others association\nbitfields.\n\nFrom
    the latest Intel SDM:\n- Add Xeon Phi 7215, 7285 and 7295\n- Add Coffee Lake\n"
  module: src
  subject: 'CVS commit: [netbsd-8] src'
  unixtime: '1523297072'
  user: martin