---
- branch: netbsd-9
  date: Fri Jan  1 12:31:19 UTC 2021
  files:
  - new: 1.17.4.3
    old: 1.17.4.2
    path: src/sys/arch/aarch64/aarch64/trap.c
    pathrev: src/sys/arch/aarch64/aarch64/trap.c@1.17.4.3
    type: modified
  id: 20210101T123119Z.77e5b1efd902f0c42bd41cbd9978b3bc0c244df3
  log: "Pull up following revision(s) (requested by rin in ticket #1169):\n\n\tsys/arch/aarch64/aarch64/trap.c:
    revision 1.21\n\tsys/arch/aarch64/aarch64/trap.c: revision 1.26\n\nPR port-arm/54702\nAdd
    support for earmv6hf binaries on COMPAT_NETBSD32 for aarch64:\n- Emulate ARMv6
    instructions with cache operations register (c7), that\n   are deprecated since
    ARMv7, and disabled on ARMv8 with LP64 kernel.\n\nMany thanks to ryo@ for helping
    me to add support of Thumb-mode,\nas well as providing exhaustive test cases:\n
    \  https://github.com/ryo/mcr_test/\n\nWe've confirmed:\n- Emulation works in
    Thumb-mode.\n- T32 16-bit length illegal instruction results in SIGILL, even if\n
    \  it is located nearby a boundary b/w mapped and unmapped pages.\n- T32 32-bit
    instruction results in SIGSEGV if it is located across\n   a boundary b/w mapped
    and unmapped pages.\n\nWhen emulating obsoleted arm32 instructions, use ufetch(9)
    rather than\ndereference tf_pc directly to retrieve an instruction.\nEven if tf_pc
    is valid when processor decodes the instruction, someone\ncan unmap its page before
    tf_pc is read in the exception handler.\nNow, SIGSEGV is delivered correctly to
    the process in this case, rather\nthan kernel panic.\n\nPointed out by maxv.\n\nDiscussed
    with ryo and skrll.\n"
  module: src
  subject: 'CVS commit: [netbsd-9] src/sys/arch/aarch64/aarch64'
  unixtime: '1609504279'
  user: martin