---
- branch: MAIN
  date: Sat Apr  9 12:06:39 UTC 2022
  files:
  - new: '1.6'
    old: '1.5'
    path: src/common/lib/libc/arch/sparc/atomic/membar_ops.S
    pathrev: src/common/lib/libc/arch/sparc/atomic/membar_ops.S@1.6
    type: modified
  id: 20220409T120639Z.9b4f11e757cc6807118e8d594386c20c67068b11
  log: |
    sparc: Fix membar_sync with LDSTUB.

    membar_sync is required to be a full sequential consistency barrier,
    equivalent to MEMBAR #StoreStore|LoadStore|StoreLoad|LoadLoad on
    sparcv9.  LDSTUB and SWAP are the only pre-v9 instructions that do
    this and SWAP doesn't exist on all v7 hardware, so use LDSTUB.

    Note: I'm having a hard time nailing down a reference for the
    ordering implied by LDSTUB and SWAP.  I'm _pretty sure_ SWAP has to
    imply store-load ordering since the SPARCv8 manual recommends it for
    Dekker's algorithm (which notoriously requires store-load ordering),
    and the formal memory model treats LDSTUB and SWAP the same for
    ordering.  But the v8 and v9 manuals aren't clear.

    GCC issues STBAR and LDSTUB, but (a) I don't see why STBAR is
    necessary here, (b) STBAR doesn't exist on v7 so it'd be a pain to
    use, and (c) from what I've heard (although again it's hard to nail
    down authoritative references here) all actual SPARC hardware is TSO
    or SC anyway so STBAR is a noop in all the silicon anyway.

    Either way, certainly this is better than what we had before, which
    was nothing implying ordering at all, just a store!
  module: src
  subject: 'CVS commit: src/common/lib/libc/arch/sparc/atomic'
  unixtime: '1649505999'
  user: riastradh