---
- branch: MAIN
  date: Tue Nov 15 14:33:34 UTC 2022
  files:
  - new: '1.25'
    old: '1.24'
    path: src/sys/arch/riscv/include/sysreg.h
    pathrev: src/sys/arch/riscv/include/sysreg.h@1.25
    type: modified
  - new: '1.14'
    old: '1.13'
    path: src/sys/arch/riscv/riscv/pmap_machdep.c
    pathrev: src/sys/arch/riscv/riscv/pmap_machdep.c@1.14
    type: modified
  - new: '1.24'
    old: '1.23'
    path: src/sys/arch/riscv/riscv/riscv_machdep.c
    pathrev: src/sys/arch/riscv/riscv/riscv_machdep.c@1.24
    type: modified
  - new: '1.6'
    old: '1.5'
    path: src/sys/arch/riscv/riscv/vm_machdep.c
    pathrev: src/sys/arch/riscv/riscv/vm_machdep.c@1.6
    type: modified
  id: 20221115T143334Z.9beae307a03e7399be4a3c110983fc25dca58320
  log: |
    Use similar macro-magic to aarch64 armreg.h to add per-csr
    read/write/set-bits/clear-bits inline functions.  Keep the
    open-coded 32-bit version of riscvreg_cycle_read() than reads
    a 64-bit cycle counter values.

    Added benefit of fixing these so that the inline asm uses __volatile
    and aren't opmtimised to nops by the compiler.
  module: src
  subject: 'CVS commit: src/sys/arch/riscv'
  unixtime: '1668522814'
  user: simonb