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netbsd-10 commitmail json YAML
src/sys/arch/aarch64/aarch64/cpuswitch.S@1.39.4.1
/
diff
/
nxr@1.39.4.1
src/sys/arch/aarch64/aarch64/locore.S@1.89.2.1 / diff / nxr@1.89.2.1
src/sys/arch/alpha/include/asm.h@1.44.20.1 / diff / nxr@1.44.20.1
src/sys/arch/arm/arm/armv6_start.S@1.37.4.1 / diff / nxr@1.37.4.1
src/sys/arch/arm/arm32/cpuswitch.S@1.105.12.1 / diff / nxr@1.105.12.1
src/sys/arch/evbmips/ingenic/cpu_startup.S@1.1.52.1 / diff / nxr@1.1.52.1
src/sys/arch/hppa/include/cpu.h@1.12.4.1 / diff / nxr@1.12.4.1
src/sys/arch/ia64/ia64/machdep.c@1.43.30.1 / diff / nxr@1.43.30.1
src/sys/arch/ia64/ia64/vm_machdep.c@1.17.4.1 / diff / nxr@1.17.4.1
src/sys/arch/mips/include/asm.h@1.71.4.1 / diff / nxr@1.71.4.1
src/sys/arch/mips/mips/locore.S@1.228.12.1 / diff / nxr@1.228.12.1
src/sys/arch/mips/mips/locore_mips3.S@1.115.20.1 / diff / nxr@1.115.20.1
src/sys/arch/powerpc/powerpc/locore_subr.S@1.66.4.1 / diff / nxr@1.66.4.1
src/sys/arch/riscv/riscv/cpu_switch.S@1.2.2.1 / diff / nxr@1.2.2.1
src/sys/arch/sparc/sparc/locore.s@1.283.4.1 / diff / nxr@1.283.4.1
src/sys/arch/sparc64/sparc64/locore.s@1.431.4.1 / diff / nxr@1.431.4.1
src/sys/arch/vax/vax/subr.S@1.41.2.1 / diff / nxr@1.41.2.1
src/sys/arch/aarch64/aarch64/locore.S@1.89.2.1 / diff / nxr@1.89.2.1
src/sys/arch/alpha/include/asm.h@1.44.20.1 / diff / nxr@1.44.20.1
src/sys/arch/arm/arm/armv6_start.S@1.37.4.1 / diff / nxr@1.37.4.1
src/sys/arch/arm/arm32/cpuswitch.S@1.105.12.1 / diff / nxr@1.105.12.1
src/sys/arch/evbmips/ingenic/cpu_startup.S@1.1.52.1 / diff / nxr@1.1.52.1
src/sys/arch/hppa/include/cpu.h@1.12.4.1 / diff / nxr@1.12.4.1
src/sys/arch/ia64/ia64/machdep.c@1.43.30.1 / diff / nxr@1.43.30.1
src/sys/arch/ia64/ia64/vm_machdep.c@1.17.4.1 / diff / nxr@1.17.4.1
src/sys/arch/mips/include/asm.h@1.71.4.1 / diff / nxr@1.71.4.1
src/sys/arch/mips/mips/locore.S@1.228.12.1 / diff / nxr@1.228.12.1
src/sys/arch/mips/mips/locore_mips3.S@1.115.20.1 / diff / nxr@1.115.20.1
src/sys/arch/powerpc/powerpc/locore_subr.S@1.66.4.1 / diff / nxr@1.66.4.1
src/sys/arch/riscv/riscv/cpu_switch.S@1.2.2.1 / diff / nxr@1.2.2.1
src/sys/arch/sparc/sparc/locore.s@1.283.4.1 / diff / nxr@1.283.4.1
src/sys/arch/sparc64/sparc64/locore.s@1.431.4.1 / diff / nxr@1.431.4.1
src/sys/arch/vax/vax/subr.S@1.41.2.1 / diff / nxr@1.41.2.1
Pull up following revision(s) (requested by riastradh in ticket #264):
sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
sys/arch/alpha/include/asm.h: revision 1.45
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/riscv/riscv/cpu_switch.S: revision 1.3
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
alpha: Add missing barriers in cpu_switchto.
Details in comments.
arm32: Add missing barriers in cpu_switchto.
Details in comments.
hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
mips: Add missing barriers in cpu_switchto.
Details in comments.
powerpc: Add missing barriers in cpu_switchto.
Details in comments.
riscv: Add missing barriers in cpu_switchto.
Details in comments.
sparc: Add missing barriers in cpu_switchto.
sparc64: Add missing barriers in cpu_switchto.
Details in comments.
vax: Note where cpu_switchto needs barriers.
Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
sys/arch/alpha/include/asm.h: revision 1.45
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/riscv/riscv/cpu_switch.S: revision 1.3
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
alpha: Add missing barriers in cpu_switchto.
Details in comments.
arm32: Add missing barriers in cpu_switchto.
Details in comments.
hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
mips: Add missing barriers in cpu_switchto.
Details in comments.
powerpc: Add missing barriers in cpu_switchto.
Details in comments.
riscv: Add missing barriers in cpu_switchto.
Details in comments.
sparc: Add missing barriers in cpu_switchto.
sparc64: Add missing barriers in cpu_switchto.
Details in comments.
vax: Note where cpu_switchto needs barriers.
Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.