---
- branch: matt-nb5-mips64
  date: Sun Mar 21 21:25:30 UTC 2010
  files:
  - new: 1.1.2.15
    old: 1.1.2.14
    path: src/sys/arch/mips/rmi/rmixl_intr.c
    pathrev: src/sys/arch/mips/rmi/rmixl_intr.c@1.1.2.15
    type: modified
  id: 20100321T212530Z.a2dbf73902e091aa61582fc4e9bb77499dad7794
  log: |
    - rework to make full use of RMI extended interrupt management
    provided by EIRR/EIMR registers
    - depends on rmixl_spl.S
    - add support for IRT based interrupt routing; for now we are still routing
    all IRT interrupts to CPU#0.
    - note that count/compare clock, IPI and FMN are handled by each CPU since
    these are local interrupt sources.
    - further changes are still needed for XLR and XLP support
  module: src
  subject: 'CVS commit: [matt-nb5-mips64] src/sys/arch/mips/rmi'
  unixtime: '1269206730'
  user: cliff