---
- branch: MAIN
  date: Sat Sep 18 12:25:07 UTC 2021
  files:
  - new: '1.34'
    old: '1.33'
    path: src/sys/arch/aarch64/aarch64/genassym.cf
    pathrev: src/sys/arch/aarch64/aarch64/genassym.cf@1.34
    type: modified
  - new: '1.24'
    old: '1.23'
    path: src/sys/arch/aarch64/aarch64/vectors.S
    pathrev: src/sys/arch/aarch64/aarch64/vectors.S@1.24
    type: modified
  - new: '1.39'
    old: '1.38'
    path: src/sys/arch/aarch64/include/cpu.h
    pathrev: src/sys/arch/aarch64/include/cpu.h@1.39
    type: modified
  - new: '1.2'
    old: '1.1'
    path: src/sys/arch/arm/cortex/gic_splfuncs.c
    pathrev: src/sys/arch/arm/cortex/gic_splfuncs.c@1.2
    type: modified
  - new: '1.15'
    old: '1.14'
    path: src/sys/arch/evbarm/conf/std.generic64
    pathrev: src/sys/arch/evbarm/conf/std.generic64@1.15
    type: modified
  id: 20210918T122507Z.e94142bd123e6f6bfe2220236c5d9ee8add37f05
  log: |
    gic_splx: performance optimizations

    Avoid any kind of register access (DAIF, PMR, etc), barriers, and atomic
    operations in the common case where no interrupt fires between spl being
    raised and lowered.

    This introduces a per-CPU return address (ci_splx_restart) used by the
    vector handler to restart a sequence in splx that compares the new ipl
    with the per-CPU hardware priority state stored in ci_hwpl.
  module: src
  subject: 'CVS commit: src/sys/arch'
  unixtime: '1631967907'
  user: jmcneill