---
- branch: MAIN
  date: Sat Mar 26 19:38:00 UTC 2022
  files:
  - new: '1.26'
    old: '1.25'
    path: src/sys/arch/mips/cavium/octeon_intr.c
    pathrev: src/sys/arch/mips/cavium/octeon_intr.c@1.26
    type: modified
  id: 20220326T193800Z.783e56e8df35c92db94ac458d5b0825f4a2e79eb
  log: |
    mips/cavium: Simplify membars around interrupt establishment.

    Previously I used xc_barrier to ensure the initialization of the
    struct octeon_intrhand was witnessed on all CPUs before publishing
    it, in order to avoid needing any barrier on the usage side to be
    issued by the interrupt handler.

    But there's no need to avoid atomic_load_consume at time of
    interrupt: on MIPS it's the same as atomic_load_relaxed anyway, so
    there's no additional memory barrier cost here.
  module: src
  subject: 'CVS commit: src/sys/arch/mips/cavium'
  unixtime: '1648323480'
  user: riastradh