Received: by mail.netbsd.org (Postfix, from userid 605) id C780814A574; Sat, 27 Aug 2011 17:06:00 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mail.netbsd.org (Postfix) with ESMTP id 8A4E614A572 for ; Sat, 27 Aug 2011 17:05:59 +0000 (UTC) X-Virus-Scanned: amavisd-new at NetBSD.org Received: from mail.netbsd.org ([127.0.0.1]) by localhost (mail.NetBSD.org [127.0.0.1]) (amavisd-new, port 10025) with ESMTP id scp+eB+Zl7uH for ; Sat, 27 Aug 2011 17:05:58 +0000 (UTC) Received: from cvs.netbsd.org (cvs.NetBSD.org [IPv6:2001:4f8:3:7:2e0:81ff:fe30:95bd]) by mail.netbsd.org (Postfix) with ESMTP id 99F5814A44D for ; Sat, 27 Aug 2011 17:05:58 +0000 (UTC) Received: by cvs.netbsd.org (Postfix, from userid 500) id 710D6175DD; Sat, 27 Aug 2011 17:05:58 +0000 (UTC) MIME-Version: 1.0 Content-Disposition: inline Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII" Date: Sat, 27 Aug 2011 17:05:58 +0000 From: "Manuel Bouyer" Subject: CVS commit: src/sys To: source-changes@NetBSD.org X-Mailer: log_accum Message-Id: <20110827170558.710D6175DD@cvs.netbsd.org> Sender: source-changes-owner@NetBSD.org List-Id: source-changes.NetBSD.org Precedence: bulk Reply-To: source-changes-d@NetBSD.org Mail-Reply-To: "Manuel Bouyer" Mail-Followup-To: source-changes-d@NetBSD.org Module Name: src Committed By: bouyer Date: Sat Aug 27 17:05:58 UTC 2011 Modified Files: src/sys/arch/evbmips/conf: LOONGSON src/sys/conf: files src/sys/dev/ata: ata_wdc.c src/sys/dev/ic: wdc.c Log Message: The loongon2f+cs5526+jmicron PATA->SATA bridge cause an interresting issue: 1) because the CS5536 is not associated with a x86 CPU, interrupts are not ack'ed as it expects so interrupts cannot configured as edge-triggered (as is expected for a PCIIDE in compat mode) 2) the PATA->SATA bridge ignores the WDC_IDS (interrupt disable bit) so the PATA IRQ line gets asserted when resetting or running some polled commands. It also wrongly asserts IRQ when the (nonexistent) slave device is selected 2) wouldn't be an issue with edge-triggered interrupt because we would get a spurious interrupt and continue operation, a new interrupt only shows up when the PATA IRQ line goes low and high again. But because of 1), we get an unclearable interrupt instead, and the system loops on the interrupt handler. To workaround this, introduce a WDC_NO_IDS compile option which runs all polled commands (including reset) at splbio() and without sleeps, so that the controller's interrupt is effectively disabled and won't be reenabled before the interrupt can be cleared. The conditions triggering this problem are speficic enough to handle this via a compile-time option; no need for a run-time (e.g. a config(9), device property or callback to disable interrupts) solution. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/conf/LOONGSON cvs rdiff -u -r1.1025 -r1.1026 src/sys/conf/files cvs rdiff -u -r1.93 -r1.94 src/sys/dev/ata/ata_wdc.c cvs rdiff -u -r1.262 -r1.263 src/sys/dev/ic/wdc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.