Received: by mail.netbsd.org (Postfix, from userid 605) id 430C014A1B6; Thu, 19 Jan 2012 08:28:54 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mail.netbsd.org (Postfix) with ESMTP id 5F9FA14A1B5 for ; Thu, 19 Jan 2012 08:28:53 +0000 (UTC) X-Virus-Scanned: amavisd-new at NetBSD.org Received: from mail.netbsd.org ([127.0.0.1]) by localhost (mail.NetBSD.org [127.0.0.1]) (amavisd-new, port 10025) with ESMTP id GvxNxXcDUOgO for ; Thu, 19 Jan 2012 08:28:51 +0000 (UTC) Received: from cvs.netbsd.org (cvs.NetBSD.org [IPv6:2001:4f8:3:7:2e0:81ff:fe30:95bd]) by mail.netbsd.org (Postfix) with ESMTP id 73EDD14A1AA for ; Thu, 19 Jan 2012 08:28:51 +0000 (UTC) Received: by cvs.netbsd.org (Postfix, from userid 500) id 4F693175DD; Thu, 19 Jan 2012 08:28:51 +0000 (UTC) MIME-Version: 1.0 Content-Disposition: inline Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII" Date: Thu, 19 Jan 2012 08:28:51 +0000 From: "Matt Thomas" Subject: CVS commit: [matt-nb5-mips64] src/sys/arch/mips To: source-changes@NetBSD.org X-Mailer: log_accum Message-Id: <20120119082851.4F693175DD@cvs.netbsd.org> Sender: source-changes-owner@NetBSD.org List-Id: source-changes.NetBSD.org Precedence: bulk Reply-To: source-changes-d@NetBSD.org Mail-Reply-To: "Matt Thomas" Mail-Followup-To: source-changes-d@NetBSD.org Module Name: src Committed By: matt Date: Thu Jan 19 08:28:50 UTC 2012 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: bus_space.h cache.h cache_mipsNN.h cache_r10k.h cache_r3k.h cache_r4k.h cache_r5k.h cache_tx39.h cpu.h cpuregs.h intr.h pmap.h psl.h src/sys/arch/mips/mips [matt-nb5-mips64]: bus_space_alignstride_chipdep.c cache.c cache_mipsNN.c cache_r10k.c cache_r3k.c cache_r4k.c cache_r4k_subr.S cache_r5k.c cache_tx39.c cpu_subr.c ipifuncs.c locore.S locore_mips3.S mipsX_subr.S mips_machdep.c pmap_syncicache.c pmap_tlb.c trap.c vm_machdep.c Log Message: When running an N32 kernel, run it with 64-bit addresses even though the kernel itself will only use 32-bit addresses. There are exceptions. bus_space_handles are now register_t instead of intptr_t. This allows them to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more KSEG2 space for the kernel to use. The cache range routines (but not index routines) now take a register_t instead of vaddr_t so they can too take a XKPHYS address. This allows the pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding massive icache invalidations. Since "cache" instruction effects are global to all CPUs and their caches, we can use the above to greatly simplify MP page isyncs. If using an O32 kernel with pages outside KSEG0, index ops still need to be performed since there isn't an a quick way of mapping the page. To generate a diff of this commit: cvs rdiff -u -r1.4.18.2 -r1.4.18.3 src/sys/arch/mips/include/bus_space.h cvs rdiff -u -r1.9.96.7 -r1.9.96.8 src/sys/arch/mips/include/cache.h cvs rdiff -u -r1.4.126.1 -r1.4.126.2 src/sys/arch/mips/include/cache_mipsNN.h cvs rdiff -u -r1.3 -r1.3.96.1 src/sys/arch/mips/include/cache_r10k.h \ src/sys/arch/mips/include/cache_r5k.h cvs rdiff -u -r1.3 -r1.3.126.1 src/sys/arch/mips/include/cache_r3k.h cvs rdiff -u -r1.11.96.2 -r1.11.96.3 src/sys/arch/mips/include/cache_r4k.h cvs rdiff -u -r1.6 -r1.6.18.1 src/sys/arch/mips/include/cache_tx39.h cvs rdiff -u -r1.90.16.39 -r1.90.16.40 src/sys/arch/mips/include/cpu.h cvs rdiff -u -r1.74.28.24 -r1.74.28.25 src/sys/arch/mips/include/cpuregs.h cvs rdiff -u -r1.3.96.17 -r1.3.96.18 src/sys/arch/mips/include/intr.h cvs rdiff -u -r1.54.26.22 -r1.54.26.23 src/sys/arch/mips/include/pmap.h cvs rdiff -u -r1.17.96.2 -r1.17.96.3 src/sys/arch/mips/include/psl.h cvs rdiff -u -r1.10.18.14 -r1.10.18.15 \ src/sys/arch/mips/mips/bus_space_alignstride_chipdep.c cvs rdiff -u -r1.33.96.11 -r1.33.96.12 src/sys/arch/mips/mips/cache.c cvs rdiff -u -r1.11.78.7 -r1.11.78.8 src/sys/arch/mips/mips/cache_mipsNN.c cvs rdiff -u -r1.4.96.1 -r1.4.96.2 src/sys/arch/mips/mips/cache_r10k.c \ src/sys/arch/mips/mips/cache_r3k.c cvs rdiff -u -r1.10.96.1 -r1.10.96.2 src/sys/arch/mips/mips/cache_r4k.c cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/mips/cache_r4k_subr.S cvs rdiff -u -r1.12.96.2 -r1.12.96.3 src/sys/arch/mips/mips/cache_r5k.c cvs rdiff -u -r1.6.28.1 -r1.6.28.2 src/sys/arch/mips/mips/cache_tx39.c cvs rdiff -u -r1.1.2.22 -r1.1.2.23 src/sys/arch/mips/mips/cpu_subr.c cvs rdiff -u -r1.1.2.6 -r1.1.2.7 src/sys/arch/mips/mips/ipifuncs.c cvs rdiff -u -r1.167.38.23 -r1.167.38.24 src/sys/arch/mips/mips/locore.S cvs rdiff -u -r1.93.38.14 -r1.93.38.15 src/sys/arch/mips/mips/locore_mips3.S cvs rdiff -u -r1.26.36.1.2.53 -r1.26.36.1.2.54 \ src/sys/arch/mips/mips/mipsX_subr.S cvs rdiff -u -r1.205.4.1.2.1.2.59 -r1.205.4.1.2.1.2.60 \ src/sys/arch/mips/mips/mips_machdep.c cvs rdiff -u -r1.1.2.2 -r1.1.2.3 src/sys/arch/mips/mips/pmap_syncicache.c cvs rdiff -u -r1.1.2.21 -r1.1.2.22 src/sys/arch/mips/mips/pmap_tlb.c cvs rdiff -u -r1.217.12.39 -r1.217.12.40 src/sys/arch/mips/mips/trap.c cvs rdiff -u -r1.121.6.1.2.23 -r1.121.6.1.2.24 \ src/sys/arch/mips/mips/vm_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.