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Date: Sun, 12 Apr 2015 20:00:42 +0000
From: "Manuel Bouyer" <bouyer@netbsd.org>
Subject: CVS commit: src/sys/arch/arm/omap
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Module Name:	src
Committed By:	bouyer
Date:		Sun Apr 12 20:00:42 UTC 2015

Modified Files:
	src/sys/arch/arm/omap: tifb.c

Log Message:
flushing the framebuffer from interrupt has several problems:
- As pointed out by Jared McNeill, this doesn't work for cold
  or ddb. Some specific handing for these cases would be needed,
  but there's no easy way to know if we're in ddb or not.
- periodic bus_dmamap_sync() of the whole framebuffer isn't cheap (about
  3% CPU constant on the beaglebone back).

instead map the framebuffer BUS_DMA_PREFETCHABLE (undocumented flag, but
is MI and properly handled by arm). This allows write-combining,
which, in addition with a shadow framebuffer for rasops(9) gives
a good performance boost too (difference with the cached+sync from intr
isn't noticeable on a boot sequence).
For X11, the framebuffer was already mapped BUS_DMA_PREFETCHABLE.
A few tests shows that mapping it fully cached doesn't make a noticeable
difference either (with or without xorg's shadow framebuffer).


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/omap/tifb.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.