Received: by mail.netbsd.org (Postfix, from userid 605) id C9D2E84E51; Tue, 13 Mar 2018 16:48:07 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mail.netbsd.org (Postfix) with ESMTP id 1062584D39 for ; Tue, 13 Mar 2018 16:48:06 +0000 (UTC) X-Virus-Scanned: amavisd-new at netbsd.org Received: from mail.netbsd.org ([IPv6:::1]) by localhost (mail.netbsd.org [IPv6:::1]) (amavisd-new, port 10025) with ESMTP id cDnrvBp9p0PH for ; Tue, 13 Mar 2018 16:48:05 +0000 (UTC) Received: from cvs.NetBSD.org (ivanova.netbsd.org [199.233.217.197]) by mail.netbsd.org (Postfix) with ESMTP id 3E13284E6B for ; Tue, 13 Mar 2018 16:48:05 +0000 (UTC) Received: by cvs.NetBSD.org (Postfix, from userid 500) id 3A727FB40; Tue, 13 Mar 2018 16:48:05 +0000 (UTC) Content-Disposition: inline Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII" MIME-Version: 1.0 Date: Tue, 13 Mar 2018 16:48:05 +0000 From: "Soren Jacobsen" Subject: CVS commit: [netbsd-6] src/sys/arch/sparc/sparc To: source-changes@NetBSD.org X-Mailer: log_accum Message-Id: <20180313164805.3A727FB40@cvs.NetBSD.org> Sender: source-changes-owner@NetBSD.org List-Id: source-changes.NetBSD.org Precedence: bulk Reply-To: source-changes-d@NetBSD.org Mail-Reply-To: "Soren Jacobsen" Mail-Followup-To: source-changes-d@NetBSD.org List-Unsubscribe: Module Name: src Committed By: snj Date: Tue Mar 13 16:48:05 UTC 2018 Modified Files: src/sys/arch/sparc/sparc [netbsd-6]: timer.c timer_sun4m.c timerreg.h Log Message: Pull up following revision(s) (requested by mrg in ticket #1519): sys/arch/sparc/sparc/timer_sun4m.c: 1.33 1.34 1.31 sys/arch/sparc/sparc/timer.c: 1.33 sys/arch/sparc/sparc/timer.c: 1.33 1.34 sys/arch/sparc/sparc/timerreg.h: 1.33 1.34 1.31 1.10 fix time goes backwards problems on sparc. there are a few things here: - there's a race between reading the limit register (which clears the interrupt and the limit bit) and increasing the latest offset. this can happen easily if an interrupt comes between the read and the call to tickle_tc() that increases the offset (i obverved this actually happening.) - in early boot, sometimes the counter can cycle twice before the tickle happens. to handle these issues, add two workarounds: - if the limit bit isn't set, but the counter value is less than the previous value, and the offset hasn't changed, use the same fixup as if the limit bit was set. this handles the first case above. - add a hard-workaround for never allowing returning a smaller value (except during 32 bit overflow): if the result is less than the last result, add fixups until it does (or until it would overflow.) the first workaround fixes general run-time issues, and the second fixes issues only seen during boot. also expand some comments in timer_sun4m.c and re-enable the sun4m sub-microsecond tmr_ustolim4m() support (but it's always called with at least 'tick' microseconds, so the end result is the same.) fix hang at 4B microseconds (1h12 or so), and simplify part of the previous To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.29.8.1 src/sys/arch/sparc/sparc/timer.c cvs rdiff -u -r1.28 -r1.28.8.1 src/sys/arch/sparc/sparc/timer_sun4m.c cvs rdiff -u -r1.9 -r1.9.118.1 src/sys/arch/sparc/sparc/timerreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.