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Date: Tue, 17 Dec 2019 12:56:45 +0000
From: "Martin Husemann" <martin@netbsd.org>
Subject: CVS commit: [netbsd-9] src/sys/arch/x86/x86
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Module Name:	src
Committed By:	martin
Date:		Tue Dec 17 12:56:45 UTC 2019

Modified Files:
	src/sys/arch/x86/x86 [netbsd-9]: bus_space.c

Log Message:
Pull up following revision(s) (requested by riastradh in ticket #566):

	sys/arch/x86/x86/bus_space.c: revision 1.42
	sys/arch/x86/x86/bus_space.c: revision 1.43

Use LFENCE/SFENCE/MFENCE in x86 bus_space_barrier.

These are needed for BUS_SPACE_MAP_PREFETCHABLE mappings.  On x86,
these are WC-type memory regions, which means -- unlike normal
WB-type memory regions -- loads can be reordered with loads,
requiring LFENCE, and stores can be reordered with stores, requiring
SFENCE.

Reference: AMD64 Architecture Programmer's Manual, Volume 2: System
Programming, Sec. 7.4.1 `Memory Barrier Interaction with Memory
Types', Table 7-3 `Memory Access Ordering Rules'.

Skip fences in bus_space_barrier on I/O space.

I/O operations are issued in program order.  Not that I/O operations
are usually a performance bottleneck anyway, but maybe it is slightly
cheaper to avoid stalling on store buffers or pending loads, and
there's very little cost to the skipping criterion here.


To generate a diff of this commit:
cvs rdiff -u -r1.41 -r1.41.4.1 src/sys/arch/x86/x86/bus_space.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.