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Date: Fri, 1 Jan 2021 12:31:19 +0000
From: "Martin Husemann" <martin@netbsd.org>
Subject: CVS commit: [netbsd-9] src/sys/arch/aarch64/aarch64
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Module Name:	src
Committed By:	martin
Date:		Fri Jan  1 12:31:19 UTC 2021

Modified Files:
	src/sys/arch/aarch64/aarch64 [netbsd-9]: trap.c

Log Message:
Pull up following revision(s) (requested by rin in ticket #1169):

	sys/arch/aarch64/aarch64/trap.c: revision 1.21
	sys/arch/aarch64/aarch64/trap.c: revision 1.26

PR port-arm/54702
Add support for earmv6hf binaries on COMPAT_NETBSD32 for aarch64:
- Emulate ARMv6 instructions with cache operations register (c7), that
   are deprecated since ARMv7, and disabled on ARMv8 with LP64 kernel.

Many thanks to ryo@ for helping me to add support of Thumb-mode,
as well as providing exhaustive test cases:
   https://github.com/ryo/mcr_test/

We've confirmed:
- Emulation works in Thumb-mode.
- T32 16-bit length illegal instruction results in SIGILL, even if
   it is located nearby a boundary b/w mapped and unmapped pages.
- T32 32-bit instruction results in SIGSEGV if it is located across
   a boundary b/w mapped and unmapped pages.

When emulating obsoleted arm32 instructions, use ufetch(9) rather than
dereference tf_pc directly to retrieve an instruction.
Even if tf_pc is valid when processor decodes the instruction, someone
can unmap its page before tf_pc is read in the exception handler.
Now, SIGSEGV is delivered correctly to the process in this case, rather
than kernel panic.

Pointed out by maxv.

Discussed with ryo and skrll.


To generate a diff of this commit:
cvs rdiff -u -r1.17.4.2 -r1.17.4.3 src/sys/arch/aarch64/aarch64/trap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.