Received: from localhost (localhost [127.0.0.1]) by mail.netbsd.org (Postfix) with ESMTP id 3768D84EE5 for ; Sun, 30 Jul 2023 11:41:49 +0000 (UTC) X-Virus-Scanned: amavisd-new at netbsd.org Received: from mail.netbsd.org ([IPv6:::1]) by localhost (mail.netbsd.org [IPv6:::1]) (amavisd-new, port 10025) with ESMTP id l3BhAPbBVyTQ for ; Sun, 30 Jul 2023 11:41:48 +0000 (UTC) Received: from cvs.NetBSD.org (ivanova.netbsd.org [199.233.217.197]) by mail.netbsd.org (Postfix) with ESMTP id 8248384E6F for ; Sun, 30 Jul 2023 11:41:48 +0000 (UTC) Received: by cvs.NetBSD.org (Postfix, from userid 500) id 7B1B4FBDB; Sun, 30 Jul 2023 11:41:48 +0000 (UTC) Content-Disposition: inline Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII" MIME-Version: 1.0 Date: Sun, 30 Jul 2023 11:41:48 +0000 From: "Martin Husemann" Subject: CVS commit: [netbsd-9] src/sys/arch/mips/cavium/dev To: source-changes@NetBSD.org Approved: for-source-only Reply-To: martin@netbsd.org X-Mailer: log_accum Message-Id: <20230730114148.7B1B4FBDB@cvs.NetBSD.org> Module Name: src Committed By: martin Date: Sun Jul 30 11:41:48 UTC 2023 Modified Files: src/sys/arch/mips/cavium/dev [netbsd-9]: octeon_rnm.c Log Message: Pull up following revision(s) (requested by gutteridge in ticket #256): sys/arch/mips/cavium/dev/octeon_rnm.c: revision 1.16 (patch) octrnm(4): Raise delay on startup. According to CN50XX-HRM-V0.99E and CN78XX-HM-0.99E: The entropy is provided by the jitter of 125 of 128 free-running oscillators XORed into a 128-bit LFSR. The LFSR accumulates entropy over 81 cycles, after which it is fed into a SHA-1 engine. [...] The SHA-1 engine runs once every 81 cycles. [...] The hardware produces new 64-bit random number every 81 cycles. The last sentence means that we only need to wait 81 cycles _between_ consecutive SHA-1 outputs (which isn't relevant anyway because we reconfigure it into raw mode later), but the first two quotes might mean that we need to wait 81+81 cycles for the _first_ output to be produced on boot when running the self-test. Now, in this case, the self-test is run with the LFSR unhooked, by clearing the RNM_CTL_STATUS[ENT_EN] bit, so that SHA-1 is computed from a known input -- this is really just paranoia to make sure that _some_ functions of the device (which is conjured out of thin air at a fixed virtual address, with no firmware bindings to guide us) behave as we expect. And it's not clear if it really does take 81+81 cycles for the first SHA-1 output to appear when the LFSR isn't feeding into it anyway. But experimentally, delay of 81+81 cycles seems to work whereas a delay of only 81 cycles crashes. PR kern/57280 To generate a diff of this commit: cvs rdiff -u -r1.2.4.2 -r1.2.4.3 src/sys/arch/mips/cavium/dev/octeon_rnm.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.