 @@ -1,14 +1,14 @@
-/*	$NetBSD: locore.s,v 1.284 2008/07/10 15:38:40 nakayama Exp $	*/
+/*	$NetBSD: locore.s,v 1.285 2008/10/05 02:00:53 nakayama Exp $	*/
 /*
  * Copyright (c) 1996-2002 Eduardo Horvath
  * Copyright (c) 1996 Paul Kranenburg
  * Copyright (c) 1996
  * 	The President and Fellows of Harvard College.
  *	All rights reserved.
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.
  *	All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
 @@ -3646,35 +3646,35 @@ Lsoftint_regular:
 	bgeu,pn	%xcc, 3f
 	 or	%g3, %lo(_C_LABEL(intrlev)), %g3
 	LDPTR	[%g3 + %g5], %g5	! We have a pointer to the handler
 	brz,pn	%g5, 3f			! NULL means it isn't registered yet.  Skip it.
 	 nop
 setup_sparcintr:
 	LDPTR	[%g5+IH_PEND], %g6	! Read pending flag
 	brnz,pn	%g6, ret_from_intr_vector ! Skip it if it's running
 	 ldub	[%g5+IH_PIL], %g6	! Read interrupt mask
 	sethi	%hi(CPUINFO_VA+CI_INTRPENDING), %g1
 	sll	%g6, PTRSHFT, %g3	! Find start of table for this IPL
 	or	%g1, %lo(CPUINFO_VA+CI_INTRPENDING), %g1
-	 add	%g1, %g3, %g1
+	add	%g1, %g3, %g1
 :
 	LDPTR	[%g1], %g3		! Load list head
 	STPTR	%g3, [%g5+IH_PEND]	! Link our intrhand node in
 	mov	%g5, %g7
 	CASPTR	[%g1] ASI_N, %g3, %g7
 	cmp	%g7, %g3		! Did it work?
 	bne,pn	CCCR, 1b		! No, try again
-	 nop
+	 EMPTY
 :
 	mov	1, %g7
 	sll	%g7, %g6, %g6
 	wr	%g6, 0, SET_SOFTINT	! Invoke a softint
 ret_from_intr_vector:
 #if KTR_COMPILE & KTR_INTR
 	CATR(KTR_TRAP, "ret_from_intr_vector: tl %d, tstate %p, tpc %p",
 		 %g3, %g4, %g5, 10, 11, 12)
 	rdpr	%tl, %g5
 	stx	%g5, [%g3 + KTR_PARM1]
 	rdpr	%tstate, %g5
 	stx	%g5, [%g3 + KTR_PARM2]
 @@ -4118,27 +4118,27 @@ sparc_intr_retry:
 	or	%l4, %lo(CPUINFO_VA+CI_INTRPENDING), %l4
 	add	%l2, %l4, %l4
 :
 	membar	#StoreLoad		! Make sure any failed casxa insns complete
 	LDPTR	[%l4], %l2		! Check a slot
 	cmp	%l2, -1
 	beq,pn	CCCR, intrcmplt		! Empty list?
 	 mov	-1, %l7
 	membar	#LoadStore
 	CASPTR	[%l4] ASI_N, %l2, %l7	! Grab the entire list
 	cmp	%l7, %l2
 	bne,pn	CCCR, 1b
-	 nop
+	 EMPTY
 :
 	add	%sp, CC64FSZ+STKB, %o2	! tf = %sp + CC64FSZ + STKB
 	LDPTR	[%l2 + IH_PEND], %l7	! save ih->ih_pending
 	membar	#LoadStore
 	STPTR	%g0, [%l2 + IH_PEND]	! Clear pending flag
 	membar	#Sync
 	LDPTR	[%l2 + IH_FUN], %o4	! ih->ih_fun
 	LDPTR	[%l2 + IH_ARG], %o0	! ih->ih_arg
 	wrpr	%g0, PSTATE_INTR, %pstate	! Reenable interrupts
 	jmpl	%o4, %o7		! handled = (*ih->ih_fun)(...)
 	 movrz	%o0, %o2, %o0		! arg = (arg == 0) ? arg : tf
 	wrpr	%g0, PSTATE_KERN, %pstate	! Disable interrupts
 @@ -5654,66 +5654,68 @@ ENTRY(sp_tlb_flush_all)
  * Does not modify %o0
+ *
  */
 	.align 8
 ENTRY(blast_dcache)
 /*
  * We turn off interrupts for the duration to prevent RED exceptions.
  */
 #ifdef PROF
 	save	%sp, -CC64FSZ, %sp
 #endif
 	rdpr	%pstate, %o3
-	set	(2 * NBPG) - 8, %o1
+	set	(2 * NBPG) - 32, %o1
 	andn	%o3, PSTATE_IE, %o4			! Turn off PSTATE_IE bit
 	wrpr	%o4, 0, %pstate
 :
 	stxa	%g0, [%o1] ASI_DCACHE_TAG
 	brnz,pt	%o1, 1b
-	 dec	8, %o1
+	 dec	32, %o1
 	sethi	%hi(KERNBASE), %o2
 	flush	%o2
 	membar	#Sync
 #ifdef PROF
 	wrpr	%o3, %pstate
 	ret
 	 restore
 #else
 	retl
 	 wrpr	%o3, %pstate
 #endif
 /*
  * blast_icache()
+ *
  * Clear out all of I$ regardless of contents
  * Does not modify %o0
+ *
  */
 	.align 8
 ENTRY(blast_icache)
 /*
  * We turn off interrupts for the duration to prevent RED exceptions.
  */
 	rdpr	%pstate, %o3
-	set	(2 * NBPG) - 8, %o1
+	set	(2 * NBPG) - 32, %o1
 	andn	%o3, PSTATE_IE, %o4			! Turn off PSTATE_IE bit
 	wrpr	%o4, 0, %pstate
 :
 	stxa	%g0, [%o1] ASI_ICACHE_TAG
 	brnz,pt	%o1, 1b
-	 dec	8, %o1
+	 dec	32, %o1
 	sethi	%hi(KERNBASE), %o2
 	flush	%o2
 	membar	#Sync
 	retl
 	 wrpr	%o3, %pstate
 /*
  * dcache_flush_page(paddr_t pa)
+ *
  * Clear one page from D$.
+ *
  */
 	.align 8
 ENTRY(dcache_flush_page)
 #ifndef _LP64
 	COMBINE(%o0, %o1, %o0)
 @@ -5734,27 +5736,26 @@ ENTRY(dcache_flush_page)
 	bl,pn	%icc, 2f
 	 inc	32, %o4
 	xor	%o3, %o2, %o3
 	andcc	%o3, %o1, %g0
 	bne,pt	%xcc, 1b
 	 membar	#LoadStore
 	stxa	%g0, [%o0] ASI_DCACHE_TAG
 	ba,pt	%icc, 1b
 	 membar	#StoreLoad
 :
 	wr	%g0, ASI_PRIMARY_NOFAULT, %asi
 	sethi	%hi(KERNBASE), %o5
 	flush	%o5
 	retl
 	 membar	#Sync
 /*
  * icache_flush_page(paddr_t pa)
+ *
  * Clear one page from I$.
+ *
  */
 	.align 8
 ENTRY(icache_flush_page)
 @@ -5767,36 +5768,36 @@ ENTRY(icache_flush_page)
 	!! Linux sez that I$ flushes are not needed for cheetah.
 	!!
 	!! Now do the I$
 	srlx	%o0, 13-8, %o2
 	mov	-1, %o1		! Generate mask for tag: bits [35..8]
 	srl	%o1, 32-35+7, %o1
 	clr	%o4
 	sll	%o1, 7, %o1	! Mask
 	set	(2*NBPG), %o5
 :
 	ldda	[%o4] ASI_ICACHE_TAG, %g0	! Tag goes in %g1
-	dec	16, %o5
+	dec	32, %o5
 	xor	%g1, %o2, %g1
 	andcc	%g1, %o1, %g0
 	bne,pt	%xcc, 2f
 	 membar	#LoadStore
 	stxa	%g0, [%o4] ASI_ICACHE_TAG
 	membar	#StoreLoad
 :
 	brnz,pt	%o5, 1b
-	 inc	16, %o4
+	 inc	32, %o4
 #endif
 	sethi	%hi(KERNBASE), %o5
 	flush	%o5
 	membar	#Sync
 	retl
 	 nop
 /*
  *	cache_flush_phys(paddr_t, psize_t, int);
+ *
  *	Clear a set of paddrs from the D$, I$ and if param3 is
  *	non-zero, E$.  (E$ is not supported yet).
  */
 @@ -5846,29 +5847,29 @@ ENTRY(cache_flush_phys)
 	membar	#LoadStore
 	stxa	%g0, [%o4] ASI_DCACHE_TAG ! Just right
 :
 #ifndef SPITFIRE
 	cmp	%o0, %g1
 	blt,pt	%xcc, 3f
 	 cmp	%o1, %g1
 	bgt,pt	%icc, 3f
 	 nop
 	stxa	%g0, [%o4] ASI_ICACHE_TAG
 :
 #endif
 	membar	#StoreLoad
-	dec	16, %o5
+	dec	32, %o5
 	brgz,pt	%o5, 1b
-	 inc	16, %o4
+	 inc	32, %o4
 	sethi	%hi(KERNBASE), %o5
 	flush	%o5
 	membar	#Sync
 	retl
 	 nop
 #ifdef COMPAT_16
 #ifdef _LP64
 /*
  * XXXXX Still needs lotsa cleanup after sendsig is complete and offsets are known
+ *
  * The following code is copied to the top of the user stack when each
 @@ -9738,31 +9739,31 @@ ENTRY(send_softint)
 	sethi	%hi(CPUINFO_VA+CI_INTRPENDING), %o3
 	LDPTR	[%o2 + IH_PEND], %o5
 	or	%o3, %lo(CPUINFO_VA+CI_INTRPENDING), %o3
 	brnz	%o5, 1f
 	 sll	%o1, PTRSHFT, %o5	! Find start of table for this IPL
 	add	%o3, %o5, %o3
 :
 	LDPTR	[%o3], %o5		! Load list head
 	STPTR	%o5, [%o2+IH_PEND]	! Link our intrhand node in
 	mov	%o2, %o4
 	CASPTR	[%o3] ASI_N, %o5, %o4
 	cmp	%o4, %o5		! Did it work?
 	bne,pn	CCCR, 2b		! No, try again
-	 nop
+	 EMPTY
-	mov	1, %o3			! Change from level to bitmask
+	mov	1, %o4			! Change from level to bitmask
-	sllx	%o3, %o1, %o3
+	sllx	%o4, %o1, %o4
-	wr	%o3, 0, SET_SOFTINT	! SET_SOFTINT
+	wr	%o4, 0, SET_SOFTINT	! SET_SOFTINT
 :
 	retl
 	 wrpr	%g1, 0, %pstate		! restore PSTATE.IE
 /*
  * Here is a very good random number generator.  This implementation is
  * based on _Two Fast Implementations of the `Minimal Standard' Random
  * Number Generator_, David G. Carta, Communications of the ACM, Jan 1990,
  * Vol 33 No 1.
  */
 /*
  * This should be rewritten using the mulx instr. if I ever understand what it
  * does.