Fri Oct 17 20:03:24 2008 UTC ()

use generic enable_interrupts() and disable_interrupts() instead of
armv6-specific interrupt control ops when _ARM_ARCH_6 not defined


(cliff)

diff -r1.47 -r1.48 src/sys/arch/arm/include/cpufunc.h

--- src/sys/arch/arm/include/cpufunc.h 2008/10/15 16:56:49	1.47
+++ src/sys/arch/arm/include/cpufunc.h 2008/10/17 20:03:24	1.48

 @@ -585,51 +585,59 @@ enable_interrupts(uint32_t mask)
 	return ret;
+}
 #define restore_interrupts(old_cpsr)					\
 	(__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
 static inline void cpsie(register_t psw) __attribute__((__unused__));
 static inline register_t cpsid(register_t psw) __attribute__((__unused__));
 static inline void
 cpsie(register_t psw)
+{
 #if _ARM_ARCH_6
 	if (!__builtin_constant_p(psw)) {
 		enable_interrupts(psw);
 		return;
+	}
 	switch (psw & (I32_bit|F32_bit)) {
 	case I32_bit:		__asm("cpsie\ti"); break;
 	case F32_bit:		__asm("cpsie\tf"); break;
 	case I32_bit|F32_bit:	__asm("cpsie\tif"); break;
+	}
 #else
 	enable_interrupts(psw);
 #endif
+}
 static inline register_t
 cpsid(register_t psw)
+{
 #if _ARM_ARCH_6
 	register_t oldpsw;
 	if (!__builtin_constant_p(psw))
 		return disable_interrupts(psw);
 	__asm("mrs	%0, cpsr" : "=r"(oldpsw));
 	switch (psw & (I32_bit|F32_bit)) {
 	case I32_bit:		__asm("cpsid\ti"); break;
 	case F32_bit:		__asm("cpsid\tf"); break;
 	case I32_bit|F32_bit:	__asm("cpsid\tif"); break;
+	}
 	return oldpsw;
 #else
 	return disable_interrupts(psw);
 #endif
+}
 #else /* ! __PROG32 */
 #define	disable_interrupts(mask)					\
 	(set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE),		\
 		 (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
 #define	enable_interrupts(mask)						\
 	(set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0))
 #define	restore_interrupts(old_r15)					\
 	(set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE),			\
 		 (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))