 @@ -1,14 +1,14 @@
-/*	com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp	*/
+/* $NetBSD: com.c,v 1.286 2008/10/25 17:50:29 matt Exp $ */
 /*-
  * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -56,27 +56,27 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)com.c	7.5 (Berkeley) 5/16/91
  */
 /*
  * COM driver, uses National Semiconductor NS16450/NS16550AF UART
  * Supports automatic hardware flow control on StarTech ST16C650A UART
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp");
+__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.286 2008/10/25 17:50:29 matt Exp $");
 #include "opt_com.h"
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
 #include "opt_lockdebug.h"
 #include "opt_multiprocessor.h"
 #include "opt_ntp.h"
 #include "rnd.h"
 #if NRND > 0 && defined(RND_COM)
 #include <sys/rnd.h>
 #endif
 @@ -394,26 +394,32 @@ com_attach_subr(struct com_softc *sc)
+	}
 	/* Probe for FIFO */
 	switch (sc->sc_type) {
 	case COM_TYPE_HAYESP:
 		goto fifodone;
 	case COM_TYPE_AU1x00:
 		sc->sc_fifolen = 16;
 		fifo_msg = "Au1X00 UART, working fifo";
 		SET(sc->sc_hwflags, COM_HW_FIFO);
 		goto fifodelay;
 	case COM_TYPE_16550_NOERS:
 		sc->sc_fifolen = 16;
 		fifo_msg = "ns16650, no ERS, working fifo";
 		SET(sc->sc_hwflags, COM_HW_FIFO);
 		goto fifodelay;
  	case COM_TYPE_OMAP:
  		sc->sc_fifolen = 64;
  		fifo_msg = "OMAP UART, working fifo";
  		SET(sc->sc_hwflags, COM_HW_FIFO);
  		goto fifodelay;
+  	}
 	sc->sc_fifolen = 1;
 	/* look for a NS 16550AF UART with FIFOs */
 	CSR_WRITE_1(regsp, COM_REG_FIFO,
 	    FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
 	delay(100);
 	if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK)
 @@ -424,52 +430,45 @@ com_attach_subr(struct com_softc *sc)
 #ifdef COM_16650
 			/*
 			 * IIR changes into the EFR if LCR is set to LCR_EERS
 			 * on 16650s. We also know IIR != 0 at this point.
 			 * Write 0 into the EFR, and read it. If the result
 			 * is 0, we have a 16650.
+			 *
 			 * Older 16650s were broken; the test to detect them
 			 * is taken from the Linux driver. Apparently
 			 * setting DLAB enable gives access to the EFR on
 			 * these chips.
 			 */
-			if (sc->sc_type != COM_TYPE_16550_NOERS) {
+			lcr = CSR_READ_1(regsp, COM_REG_LCR);
-				lcr = CSR_READ_1(regsp, COM_REG_LCR);
+			CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
-				CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
+			CSR_WRITE_1(regsp, COM_REG_EFR, 0);
-				CSR_WRITE_1(regsp, COM_REG_EFR, 0);
+			if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
 				CSR_WRITE_1(regsp, COM_REG_LCR,
 				    lcr | LCR_DLAB);
 				if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
-					CSR_WRITE_1(regsp, COM_REG_LCR,
+					CLR(sc->sc_hwflags, COM_HW_FIFO);
-					    lcr | LCR_DLAB);
+					sc->sc_fifolen = 0;
-					if (CSR_READ_1(regsp, COM_REG_EFR)
+				} else {
-					    == 0) {
+					SET(sc->sc_hwflags, COM_HW_FLOW);
-						CLR(sc->sc_hwflags,
+					sc->sc_fifolen = 32;
 						    COM_HW_FIFO);
 						sc->sc_fifolen = 0;
 					} else {
 						SET(sc->sc_hwflags,
 						    COM_HW_FLOW);
 						sc->sc_fifolen = 32;
 				} else
 					sc->sc_fifolen = 16;
 				CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
 			} else
 #endif
 				sc->sc_fifolen = 16;
 #ifdef COM_16650
 			CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
 			if (sc->sc_fifolen == 0)
 				fifo_msg = "st16650, broken fifo";
 			else if (sc->sc_fifolen == 32)
 				fifo_msg = "st16650a, working fifo";
 			else
 #endif
 				fifo_msg = "ns16550a, working fifo";
 		} else
 			fifo_msg = "ns16550, broken fifo";
 	else
 		fifo_msg = "ns8250 or ns16450, no fifo";
 	CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
 fifodelay:
 @@ -1451,32 +1450,31 @@ com_loadchannelregs(struct com_softc *sc
 	com_iflush(sc);
 	if (sc->sc_type == COM_TYPE_PXA2x0)
 		CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
 	else
 		CSR_WRITE_1(regsp, COM_REG_IER, 0);
 	if (sc->sc_type == COM_TYPE_OMAP) {
 		/* disable before changing settings */
 		CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
+	}
 	if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) {
-		if (sc->sc_type != COM_TYPE_AU1x00
+		KASSERT(sc->sc_type != COM_TYPE_AU1x00);
-		    && sc->sc_type != COM_TYPE_16550_NOERS) {
+		KASSERT(sc->sc_type != COM_TYPE_16550_NOERS);
-			/* no EFR on alchemy */
+		/* no EFR on alchemy */
-			CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
+		CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
-			CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
+		CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
+	}
 	if (sc->sc_type == COM_TYPE_AU1x00) {
 		/* alchemy has single separate 16-bit clock divisor register */
 		CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl +
 		    (sc->sc_dlbh << 8));
 	} else {
 		CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
 		CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
 		CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
+	}
 	CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
 	CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr);
 	CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo);