 @@ -1,14 +1,14 @@
-/* $NetBSD: if_msk.c,v 1.21 2008/06/20 16:45:13 cube Exp $ */
+/* $NetBSD: if_msk.c,v 1.22 2008/11/18 09:30:43 chris Exp $ */
 /*	$OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $	*/
 /*
  * Copyright (c) 1997, 1998, 1999, 2000
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -42,27 +42,27 @@
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.21 2008/06/20 16:45:13 cube Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.22 2008/11/18 09:30:43 chris Exp $");
 #include "bpfilter.h"
 #include "rnd.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/mutex.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/device.h>
 @@ -798,26 +798,46 @@ void msk_reset(struct sk_softc *sc)
 	CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET);
 	DELAY(1000);
 	CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET);
 	DELAY(2);
 	CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
 	sk_win_write_1(sc, SK_TESTCTL1, 2);
 	reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1));
 	if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
 		reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
 	else
 		reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
 	if (sc->sk_type == SK_YUKON_EC_U) {
 		uint32_t our;
 		CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON);
 		/* enable all clocks. */
 		sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0);
 		our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4));
 		our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST|
 			SK_Y2_REG4_ASPM_GPHY_LINK_DOWN|
 			SK_Y2_REG4_ASPM_INT_FIFO_EMPTY|
 			SK_Y2_REG4_ASPM_CLKRUN_REQUEST);
 		/* Set all bits to 0 except bits 15..12 */
 		sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our);
 		/* Set to default value */
 		sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0);
+	}
 	/* release PHY from PowerDown/Coma mode. */
 	sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1);
 	if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
 		sk_win_write_1(sc, SK_Y2_CLKGATE,
 		    SK_Y2_CLKGATE_LINK1_GATE_DIS |
 		    SK_Y2_CLKGATE_LINK2_GATE_DIS |
 		    SK_Y2_CLKGATE_LINK1_CORE_DIS |
 		    SK_Y2_CLKGATE_LINK2_CORE_DIS |
 		    SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS);
 	else
 		sk_win_write_1(sc, SK_Y2_CLKGATE, 0);
 	CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
 @@ -1793,28 +1813,32 @@ msk_txeof(struct sk_if_softc *sc_if, int
 	if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2)
 		ifp->if_flags &= ~IFF_OACTIVE;
 	if (prog > 0)
 		sc_if->sk_cdata.sk_tx_cons = cons;
+}
 void
 msk_tick(void *xsc_if)
+{
 	struct sk_if_softc *sc_if = xsc_if;
 	struct mii_data *mii = &sc_if->sk_mii;
 	int s;
 	s = splnet();
 	mii_tick(mii);
 	splx(s);
 	callout_schedule(&sc_if->sk_tick_ch, hz);
+}
 void
 msk_intr_yukon(struct sk_if_softc *sc_if)
+{
 	u_int8_t status;
 	status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
 	/* RX overrun */
 	if ((status & SK_GMAC_INT_RX_OVER) != 0) {
 		SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
 		    SK_RFCTL_RX_FIFO_OVER);

 @@ -1,14 +1,14 @@
-/* $NetBSD: if_skreg.h,v 1.12 2008/04/28 20:23:55 martin Exp $ */
+/* $NetBSD: if_skreg.h,v 1.13 2008/11/18 09:30:43 chris Exp $ */
 /*-
  * Copyright (c) 2003 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -194,26 +194,28 @@
 /* SK_CSR register */
 #define SK_CSR_SW_RESET			0x0001
 #define SK_CSR_SW_UNRESET		0x0002
 #define SK_CSR_MASTER_RESET		0x0004
 #define SK_CSR_MASTER_UNRESET		0x0008
 #define SK_CSR_MASTER_STOP		0x0010
 #define SK_CSR_MASTER_DONE		0x0020
 #define SK_CSR_SW_IRQ_CLEAR		0x0040
 #define SK_CSR_SW_IRQ_SET		0x0080
 #define SK_CSR_SLOTSIZE			0x0100 /* 1 == 64 bits, 0 == 32 */
 #define SK_CSR_BUSCLOCK			0x0200 /* 1 == 33/66 MHz, = 33 */
 #define SK_CSR_ASF_OFF			0x1000
 #define SK_CSR_ASF_ON			0x2000
 #define SK_CSR_WOL_OFF			__BIT(14)
 #define SK_CSR_WOL_ON			__BIT(15)
 /* SK_LED register */
 #define SK_LED_GREEN_OFF		0x01
 #define SK_LED_GREEN_ON			0x02
 /* SK_ISR register */
 #define SK_ISR_TX2_AS_CHECK		0x00000001
 #define SK_ISR_TX2_AS_EOF		0x00000002
 #define SK_ISR_TX2_AS_EOB		0x00000004
 #define SK_ISR_TX2_S_CHECK		0x00000008
 #define SK_ISR_TX2_S_EOF		0x00000010
 #define SK_ISR_TX2_S_EOB		0x00000020
 #define SK_ISR_TX1_AS_CHECK		0x00000040
 @@ -1494,30 +1496,45 @@
 /* device specific PCI registers */
 #define SK_PCI_OURREG1		0x0040
 #define SK_PCI_OURREG2		0x0044
 #define SK_PCI_CAPID		0x0048 /* 8 bits */
 #define SK_PCI_NEXTPTR		0x0049 /* 8 bits */
 #define SK_PCI_PWRMGMTCAP	0x004A /* 16 bits */
 #define SK_PCI_PWRMGMTCTRL	0x004C /* 16 bits */
 #define SK_PCI_PME_EVENT	0x004F
 #define SK_PCI_VPD_CAPID	0x0050
 #define SK_PCI_VPD_NEXTPTR	0x0051
 #define SK_PCI_VPD_ADDR		0x0052
 #define SK_PCI_VPD_DATA		0x0054
 #define SK_PCI_OURREG3		0x0080 /* Yukon EC U */
 #define SK_PCI_OURREG4		0x0084
 #define SK_PCI_OURREG5		0x0088
 #define SK_Y2_REG1_PHY1_COMA	0x10000000
 #define SK_Y2_REG1_PHY2_COMA	0x20000000
 /* SK_PCI_OURREG4 32bits (Yukon-ECU only) */
 #define SK_Y2_REG4_TIMER_VALUE_MSK	(0xff << 16)
 #define SK_Y2_REG4_FORCE_ASPM_REQUEST	__BIT(15)
 #define SK_Y2_REG4_ASPM_GPHY_LINK_DOWN	__BIT(14)
 #define SK_Y2_REG4_ASPM_INT_FIFO_EMPTY	__BIT(13)
 #define SK_Y2_REG4_ASPM_CLKRUN_REQUEST	__BIT(12)
 #define SK_Y2_REG4_ASPM_FORCE_CLKREQ_ENA	__BIT(4)
 #define SK_Y2_REG4_ASPM_CLKREQ_PAD	__BIT(3)
 #define SK_Y2_REG4_ASPM_A1_MODE_SELECT	__BIT(2)
 #define SK_Y2_REG4_CLK_GATE_PEX_UNIT_ENA	__BIT(1)
 #define SK_Y2_REG4_CLK_GATE_ROOT_COR_ENA	__BIT(0)
 #define SK_PSTATE_MASK		0x0003
 #define SK_PSTATE_D0		0x0000
 #define SK_PSTATE_D1		0x0001
 #define SK_PSTATE_D2		0x0002
 #define SK_PSTATE_D3		0x0003
 #define SK_PME_EN		0x0010
 #define SK_PME_STATUS		0x8000
 /*
  * VPD flag bit. Set to 0 to initiate a read, will become 1 when
  * read is complete. Set to 1 to initiate a write, will become 0
  * when write is finished.
  */