Sun Jan 4 02:16:41 2009 UTC ()
fix time_t format.


(christos)
diff -r1.180 -r1.180.8.1 src/sys/dev/pci/pccbb.c
cvs diff -r1.180 -r1.180.8.1 src/sys/dev/pci/pccbb.c (expand / switch to unified diff)

--- src/sys/dev/pci/pccbb.c 2008/10/25 18:46:38 1.180
+++ src/sys/dev/pci/pccbb.c 2008/10/25 18:46:38 1.180.8.1
@@ -1,3221 +0,0 @@ @@ -1,3221 +0,0 @@
1/* $NetBSD: pccbb.c,v 1.180 2008/10/25 18:46:38 christos Exp $ */ 
2 
3/* 
4 * Copyright (c) 1998, 1999 and 2000 
5 * HAYAKAWA Koichi. All rights reserved. 
6 * 
7 * Redistribution and use in source and binary forms, with or without 
8 * modification, are permitted provided that the following conditions 
9 * are met: 
10 * 1. Redistributions of source code must retain the above copyright 
11 * notice, this list of conditions and the following disclaimer. 
12 * 2. Redistributions in binary form must reproduce the above copyright 
13 * notice, this list of conditions and the following disclaimer in the 
14 * documentation and/or other materials provided with the distribution. 
15 * 3. All advertising materials mentioning features or use of this software 
16 * must display the following acknowledgement: 
17 * This product includes software developed by HAYAKAWA Koichi. 
18 * 4. The name of the author may not be used to endorse or promote products 
19 * derived from this software without specific prior written permission. 
20 * 
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
31 */ 
32 
33#include <sys/cdefs.h> 
34__KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.180 2008/10/25 18:46:38 christos Exp $"); 
35 
36/* 
37#define CBB_DEBUG 
38#define SHOW_REGS 
39*/ 
40 
41#include <sys/param.h> 
42#include <sys/systm.h> 
43#include <sys/kernel.h> 
44#include <sys/errno.h> 
45#include <sys/ioctl.h> 
46#include <sys/reboot.h> /* for bootverbose */ 
47#include <sys/syslog.h> 
48#include <sys/device.h> 
49#include <sys/malloc.h> 
50#include <sys/proc.h> 
51 
52#include <sys/intr.h> 
53#include <sys/bus.h> 
54 
55#include <dev/pci/pcivar.h> 
56#include <dev/pci/pcireg.h> 
57#include <dev/pci/pcidevs.h> 
58 
59#include <dev/pci/pccbbreg.h> 
60 
61#include <dev/cardbus/cardslotvar.h> 
62 
63#include <dev/cardbus/cardbusvar.h> 
64 
65#include <dev/pcmcia/pcmciareg.h> 
66#include <dev/pcmcia/pcmciavar.h> 
67 
68#include <dev/ic/i82365reg.h> 
69#include <dev/pci/pccbbvar.h> 
70 
71#ifndef __NetBSD_Version__ 
72struct cfdriver cbb_cd = { 
73 NULL, "cbb", DV_DULL 
74}; 
75#endif 
76 
77#ifdef CBB_DEBUG 
78#define DPRINTF(x) printf x 
79#define STATIC 
80#else 
81#define DPRINTF(x) 
82#define STATIC static 
83#endif 
84 
85int pccbb_burstup = 1; 
86 
87/* 
88 * delay_ms() is wait in milliseconds. It should be used instead 
89 * of delay() if you want to wait more than 1 ms. 
90 */ 
91static inline void 
92delay_ms(int millis, void *param) 
93{ 
94 if (cold) 
95 delay(millis * 1000); 
96 else 
97 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 
98} 
99 
100int pcicbbmatch(device_t, struct cfdata *, void *); 
101void pccbbattach(device_t, device_t, void *); 
102int pccbbdetach(device_t, int); 
103int pccbbintr(void *); 
104static void pci113x_insert(void *); 
105static int pccbbintr_function(struct pccbb_softc *); 
106 
107static int pccbb_detect_card(struct pccbb_softc *); 
108 
109static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 
110static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 
111#define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 
112#define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 
113 
114STATIC int cb_reset(struct pccbb_softc *); 
115STATIC int cb_detect_voltage(struct pccbb_softc *); 
116STATIC int cbbprint(void *, const char *); 
117 
118static int cb_chipset(u_int32_t, int *); 
119STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 
120 struct pcmciabus_attach_args *); 
121 
122STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 
123STATIC int pccbb_power(struct pccbb_softc *sc, int); 
124STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 
125STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 
126#if !rbus 
127static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 
128static int pccbb_io_close(cardbus_chipset_tag_t, int); 
129static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 
130static int pccbb_mem_close(cardbus_chipset_tag_t, int); 
131#endif /* !rbus */ 
132static void *pccbb_intr_establish(struct pccbb_softc *, 
133 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 
134static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 
135 
136static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 
137 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 
138static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 
139 
140static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 
141static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 
142static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 
143static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 
144 cardbusreg_t); 
145static void pccbb_chipinit(struct pccbb_softc *); 
146static void pccbb_intrinit(struct pccbb_softc *); 
147 
148STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 
149 struct pcmcia_mem_handle *); 
150STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 
151 struct pcmcia_mem_handle *); 
152STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 
153 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 
154STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 
155STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 
156 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 
157STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 
158 struct pcmcia_io_handle *); 
159STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 
160 bus_size_t, struct pcmcia_io_handle *, int *); 
161STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 
162STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 
163 struct pcmcia_function *, int, int (*)(void *), void *); 
164STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 
165STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 
166STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 
167STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 
168STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 
169 
170static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 
171static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 
172 
173static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 
174static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 
175 
176/* bus-space allocation and deallocation functions */ 
177#if rbus 
178 
179static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 
180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 
181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 
182static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 
183 bus_space_handle_t, bus_size_t); 
184 
185#endif /* rbus */ 
186 
187#if rbus 
188 
189static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 
190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 
191static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 
192 bus_space_handle_t, bus_size_t); 
193static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 
194 bus_size_t, bus_space_handle_t, int); 
195static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 
196 bus_space_handle_t, bus_size_t); 
197static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 
198 bus_space_tag_t); 
199void pccbb_winlist_show(struct pccbb_win_chain *); 
200 
201#endif /* rbus */ 
202 
203/* for config_defer */ 
204static void pccbb_pci_callback(device_t); 
205 
206static bool pccbb_suspend(device_t PMF_FN_PROTO); 
207static bool pccbb_resume(device_t PMF_FN_PROTO); 
208 
209#if defined SHOW_REGS 
210static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 
211 bus_space_tag_t memt, bus_space_handle_t memh); 
212#endif 
213 
214CFATTACH_DECL_NEW(cbb_pci, sizeof(struct pccbb_softc), 
215 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 
216 
217static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 
218 pccbb_pcmcia_mem_alloc, 
219 pccbb_pcmcia_mem_free, 
220 pccbb_pcmcia_mem_map, 
221 pccbb_pcmcia_mem_unmap, 
222 pccbb_pcmcia_io_alloc, 
223 pccbb_pcmcia_io_free, 
224 pccbb_pcmcia_io_map, 
225 pccbb_pcmcia_io_unmap, 
226 pccbb_pcmcia_intr_establish, 
227 pccbb_pcmcia_intr_disestablish, 
228 pccbb_pcmcia_socket_enable, 
229 pccbb_pcmcia_socket_disable, 
230 pccbb_pcmcia_socket_settype, 
231 pccbb_pcmcia_card_detect 
232}; 
233 
234#if rbus 
235static const struct cardbus_functions pccbb_funcs = { 
236 pccbb_rbus_cb_space_alloc, 
237 pccbb_rbus_cb_space_free, 
238 pccbb_cb_intr_establish, 
239 pccbb_cb_intr_disestablish, 
240 pccbb_ctrl, 
241 pccbb_power_ct, 
242 pccbb_make_tag, 
243 pccbb_free_tag, 
244 pccbb_conf_read, 
245 pccbb_conf_write, 
246}; 
247#else 
248static const struct cardbus_functions pccbb_funcs = { 
249 pccbb_ctrl, 
250 pccbb_power_ct, 
251 pccbb_mem_open, 
252 pccbb_mem_close, 
253 pccbb_io_open, 
254 pccbb_io_close, 
255 pccbb_cb_intr_establish, 
256 pccbb_cb_intr_disestablish, 
257 pccbb_make_tag, 
258 pccbb_conf_read, 
259 pccbb_conf_write, 
260}; 
261#endif 
262 
263int 
264pcicbbmatch(device_t parent, struct cfdata *match, void *aux) 
265{ 
266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 
267 
268 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 
269 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 
270 PCI_INTERFACE(pa->pa_class) == 0) { 
271 return 1; 
272 } 
273 
274 return 0; 
275} 
276 
277#define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 
278 | ((prod) << PCI_PRODUCT_SHIFT)) 
279 
280const struct yenta_chipinfo { 
281 pcireg_t yc_id; /* vendor tag | product tag */ 
282 int yc_chiptype; 
283 int yc_flags; 
284} yc_chipsets[] = { 
285 /* Texas Instruments chips */ 
286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 
287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 
289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 
291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 
293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 
295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 
297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 
299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 
301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 
303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 
305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 
307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 
309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 
311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 
313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 
315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 
317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 
319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 
320 
321 /* Ricoh chips */ 
322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 
323 PCCBB_PCMCIA_MEM_32}, 
324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 
325 PCCBB_PCMCIA_MEM_32}, 
326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 
327 PCCBB_PCMCIA_MEM_32}, 
328 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 
329 PCCBB_PCMCIA_MEM_32}, 
330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 
331 PCCBB_PCMCIA_MEM_32}, 
332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 
333 PCCBB_PCMCIA_MEM_32}, 
334 
335 /* Toshiba products */ 
336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 
337 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 
338 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 
339 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 
340 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 
341 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 
342 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 
343 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 
344 
345 /* Cirrus Logic products */ 
346 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 
347 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 
348 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 
349 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 
350 
351 /* O2 Micro products */ 
352 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 
353 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 
354 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 
355 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 
356 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 
357 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 
358 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 
359 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 
360 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 
361 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 
362 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 
363 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 
364 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 
365 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 
366 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 
367 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 
368 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 
369 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 
370 
371 /* sentinel, or Generic chip */ 
372 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 
373}; 
374 
375static int 
376cb_chipset(u_int32_t pci_id, int *flagp) 
377{ 
378 const struct yenta_chipinfo *yc; 
379 
380 /* Loop over except the last default entry. */ 
381 for (yc = yc_chipsets; yc < yc_chipsets + 
382 __arraycount(yc_chipsets) - 1; yc++) 
383 if (pci_id == yc->yc_id) 
384 break; 
385 
386 if (flagp != NULL) 
387 *flagp = yc->yc_flags; 
388 
389 return (yc->yc_chiptype); 
390} 
391 
392void 
393pccbbattach(device_t parent, device_t self, void *aux) 
394{ 
395 struct pccbb_softc *sc = device_private(self); 
396 struct pci_attach_args *pa = aux; 
397 pci_chipset_tag_t pc = pa->pa_pc; 
398 pcireg_t busreg, reg, sock_base; 
399 bus_addr_t sockbase; 
400 char devinfo[256]; 
401 int flags; 
402 
403#ifdef __HAVE_PCCBB_ATTACH_HOOK 
404 pccbb_attach_hook(parent, self, pa); 
405#endif 
406 
407 sc->sc_dev = self; 
408 
409 callout_init(&sc->sc_insert_ch, 0); 
410 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 
411 
412 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 
413 
414 aprint_naive("\n"); 
415 
416 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 
417 aprint_normal(": %s (rev. 0x%02x)", devinfo, 
418 PCI_REVISION(pa->pa_class)); 
419 DPRINTF((" (chipflags %x)", flags)); 
420 aprint_normal("\n"); 
421 
422 TAILQ_INIT(&sc->sc_memwindow); 
423 TAILQ_INIT(&sc->sc_iowindow); 
424 
425#if rbus 
426 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 
427 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 
428 
429#if 0 
430 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 
431 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 
432#endif 
433#endif /* rbus */ 
434 
435 sc->sc_flags &= ~CBB_MEMHMAPPED; 
436 
437 /* 
438 * MAP socket registers and ExCA registers on memory-space 
439 * When no valid address is set on socket base registers (on pci 
440 * config space), get it not polite way. 
441 */ 
442 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 
443 
444 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 
445 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 
446 /* The address must be valid. */ 
447 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 
448 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 
449 aprint_error_dev(self, 
450 "can't map socket base address 0x%lx\n", 
451 (unsigned long)sock_base); 
452 /* 
453 * I think it's funny: socket base registers must be 
454 * mapped on memory space, but ... 
455 */ 
456 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 
457 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 
458 &sc->sc_base_size)) { 
459 aprint_error_dev(self, 
460 "can't map socket base address" 
461 " 0x%lx: io mode\n",  
462 (unsigned long)sockbase); 
463 /* give up... allocate reg space via rbus. */ 
464 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 
465 } else 
466 sc->sc_flags |= CBB_MEMHMAPPED; 
467 } else { 
468 DPRINTF(("%s: socket base address 0x%lx\n", 
469 device_xname(self), 
470 (unsigned long)sockbase)); 
471 sc->sc_flags |= CBB_MEMHMAPPED; 
472 } 
473 } 
474 
475 sc->sc_mem_start = 0; /* XXX */ 
476 sc->sc_mem_end = 0xffffffff; /* XXX */ 
477 
478 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 
479 
480 /* pccbb_machdep.c end */ 
481 
482#if defined CBB_DEBUG 
483 { 
484 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 
485 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 
486 intrname[pa->pa_intrpin], pa->pa_intrline); 
487 } 
488#endif 
489 
490 /* setup softc */ 
491 sc->sc_pc = pc; 
492 sc->sc_iot = pa->pa_iot; 
493 sc->sc_memt = pa->pa_memt; 
494 sc->sc_dmat = pa->pa_dmat; 
495 sc->sc_tag = pa->pa_tag; 
496 
497 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 
498 
499 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 
500 
501 /* Disable legacy register mapping. */ 
502 switch (sc->sc_chipset) { 
503 case CB_RX5C46X: /* fallthrough */ 
504#if 0 
505 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 
506 case CB_RX5C47X: 
507#endif 
508 /* 
509 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 
510 * cannot be disabled by substituting 0 into PCI_LEGACY 
511 * register. Ricoh CardBus bridges have special bits on Bridge 
512 * control reg (addr 0x3e on PCI config space). 
513 */ 
514 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 
515 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 
516 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 
517 break; 
518 
519 default: 
520 /* XXX I don't know proper way to kill legacy I/O. */ 
521 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 
522 break; 
523 } 
524 
525 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 
526 aprint_error_dev(self, "couldn't establish power handler\n"); 
527 
528 config_defer(self, pccbb_pci_callback); 
529} 
530 
531int 
532pccbbdetach(device_t self, int flags) 
533{ 
534 struct pccbb_softc *sc = device_private(self); 
535 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 
536 bus_space_tag_t bmt = sc->sc_base_memt; 
537 bus_space_handle_t bmh = sc->sc_base_memh; 
538 uint32_t sockmask; 
539 int rc; 
540 
541 if ((rc = config_detach_children(self, flags)) != 0) 
542 return rc; 
543 
544 if (!LIST_EMPTY(&sc->sc_pil)) { 
545 panic("%s: interrupt handlers still registered", 
546 device_xname(self)); 
547 return EBUSY; 
548 } 
549 
550 if (sc->sc_ih != NULL) { 
551 pci_intr_disestablish(pc, sc->sc_ih); 
552 sc->sc_ih = NULL; 
553 } 
554 
555 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 
556 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 
557 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 
558 CB_SOCKET_MASK_POWER); 
559 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 
560 /* reset interrupt */ 
561 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 
562 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 
563 
564 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 
565 case CBB_MEMHMAPPED: 
566 bus_space_unmap(bmt, bmh, sc->sc_base_size); 
567 break; 
568 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 
569#if rbus 
570 { 
571 pcireg_t sockbase; 
572 
573 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 
574 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 
575 NULL); 
576 } 
577#else 
578 bus_space_free(bmt, bmh, 0x1000); 
579#endif 
580 } 
581 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 
582 
583 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 
584 aprint_error_dev(self, "i/o windows not empty"); 
585 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 
586 aprint_error_dev(self, "memory windows not empty"); 
587 
588 callout_stop(&sc->sc_insert_ch); 
589 callout_destroy(&sc->sc_insert_ch); 
590 return 0; 
591} 
592 
593/* 
594 * static void pccbb_pci_callback(device_t self) 
595 * 
596 * The actual attach routine: get memory space for YENTA register 
597 * space, setup YENTA register and route interrupt. 
598 * 
599 * This function should be deferred because this device may obtain 
600 * memory space dynamically. This function must avoid obtaining 
601 * memory area which has already kept for another device. 
602 */ 
603static void 
604pccbb_pci_callback(device_t self) 
605{ 
606 struct pccbb_softc *sc = device_private(self); 
607 pci_chipset_tag_t pc = sc->sc_pc; 
608 bus_addr_t sockbase; 
609 struct cbslot_attach_args cba; 
610 struct pcmciabus_attach_args paa; 
611 struct cardslot_attach_args caa; 
612 device_t csc; 
613 
614 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 
615 /* The socket registers aren't mapped correctly. */ 
616#if rbus 
617 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 
618 (sc->sc_chipset == CB_RX5C47X 
619 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 
620 0, &sockbase, &sc->sc_base_memh)) { 
621 return; 
622 } 
623 sc->sc_base_memt = sc->sc_memt; 
624 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 
625 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 
626 device_xname(self), (unsigned long)sockbase, 
627 (unsigned long)pci_conf_read(pc, sc->sc_tag, 
628 PCI_SOCKBASE))); 
629#else 
630 sc->sc_base_memt = sc->sc_memt; 
631#if !defined CBB_PCI_BASE 
632#define CBB_PCI_BASE 0x20000000 
633#endif 
634 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 
635 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 
636 /* cannot allocate memory space */ 
637 return; 
638 } 
639 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 
640 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 
641 device_xname(self), (unsigned long)sock_base, 
642 (unsigned long)pci_conf_read(pc, 
643 sc->sc_tag, PCI_SOCKBASE))); 
644#endif 
645 sc->sc_flags |= CBB_MEMHMAPPED; 
646 } 
647 
648 /* clear data structure for child device interrupt handlers */ 
649 LIST_INIT(&sc->sc_pil); 
650 
651 /* bus bridge initialization */ 
652 pccbb_chipinit(sc); 
653 
654 sc->sc_pil_intr_enable = 1; 
655 
656 { 
657 u_int32_t sockstat; 
658 
659 sockstat = bus_space_read_4(sc->sc_base_memt, 
660 sc->sc_base_memh, CB_SOCKET_STAT); 
661 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 
662 sc->sc_flags |= CBB_CARDEXIST; 
663 } 
664 } 
665 
666 /* 
667 * attach cardbus 
668 */ 
669 { 
670 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 
671 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 
672 
673 /* initialize cbslot_attach */ 
674 cba.cba_iot = sc->sc_iot; 
675 cba.cba_memt = sc->sc_memt; 
676 cba.cba_dmat = sc->sc_dmat; 
677 cba.cba_bus = (busreg >> 8) & 0x0ff; 
678 cba.cba_cc = (void *)sc; 
679 cba.cba_cf = &pccbb_funcs; 
680 cba.cba_intrline = 0; /* XXX dummy */ 
681 
682#if rbus 
683 cba.cba_rbus_iot = sc->sc_rbus_iot; 
684 cba.cba_rbus_memt = sc->sc_rbus_memt; 
685#endif 
686 
687 cba.cba_cacheline = PCI_CACHELINE(bhlc); 
688 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 
689 
690 aprint_verbose_dev(self, 
691 "cacheline 0x%x lattimer 0x%x\n", 
692 cba.cba_cacheline, 
693 cba.cba_max_lattimer); 
694 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 
695#if defined SHOW_REGS 
696 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 
697 sc->sc_base_memh); 
698#endif 
699 } 
700 
701 pccbb_pcmcia_attach_setup(sc, &paa); 
702 caa.caa_cb_attach = NULL; 
703 if (cba.cba_bus == 0) 
704 aprint_error_dev(self, 
705 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 
706 else 
707 caa.caa_cb_attach = &cba; 
708 caa.caa_16_attach = &paa; 
709 
710 pccbb_intrinit(sc); 
711 
712 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 
713 cbbprint))) { 
714 DPRINTF(("%s: found cardslot\n", __func__)); 
715 sc->sc_csc = device_private(csc); 
716 } 
717 
718 return; 
719} 
720 
721 
722 
723 
724 
725/* 
726 * static void pccbb_chipinit(struct pccbb_softc *sc) 
727 * 
728 * This function initialize YENTA chip registers listed below: 
729 * 1) PCI command reg, 
730 * 2) PCI and CardBus latency timer, 
731 * 3) route PCI interrupt, 
732 * 4) close all memory and io windows. 
733 * 5) turn off bus power. 
734 * 6) card detect and power cycle interrupts on. 
735 * 7) clear interrupt 
736 */ 
737static void 
738pccbb_chipinit(struct pccbb_softc *sc) 
739{ 
740 pci_chipset_tag_t pc = sc->sc_pc; 
741 pcitag_t tag = sc->sc_tag; 
742 bus_space_tag_t bmt = sc->sc_base_memt; 
743 bus_space_handle_t bmh = sc->sc_base_memh; 
744 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 
745 sysctrl; 
746 
747 /* 
748 * Set PCI command reg. 
749 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 
750 */ 
751 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 
752 /* I believe it is harmless. */ 
753 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 
754 PCI_COMMAND_MASTER_ENABLE); 
755 
756 /* All O2 Micro chips have broken parity-error reporting 
757 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 
758 * is known to have the defect---see PR kern/38698. 
759 */ 
760 if (sc->sc_chipset != CB_O2MICRO) 
761 csr |= PCI_COMMAND_PARITY_ENABLE; 
762 
763 csr |= PCI_COMMAND_SERR_ENABLE; 
764 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 
765 
766 /* 
767 * Set CardBus latency timer. 
768 */ 
769 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 
770 if (PCI_CB_LATENCY(lscp) < 0x20) { 
771 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 
772 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 
773 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 
774 } 
775 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 
776 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 
777 
778 /* 
779 * Set PCI latency timer. 
780 */ 
781 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 
782 if (PCI_LATTIMER(bhlc) < 0x10) { 
783 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 
784 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 
785 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 
786 } 
787 DPRINTF(("PCI latency timer 0x%x (%x)\n", 
788 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 
789 
790 
791 /* Route functional interrupts to PCI. */ 
792 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 
793 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 
794 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 
795 /* assert reset */ 
796 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 
797 /* Set master abort mode to 1, forward SERR# from secondary 
798 * to primary, and detect parity errors on secondary. 
799 */ 
800 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 
801 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 
802 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 
803 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 
804 
805 switch (sc->sc_chipset) { 
806 case CB_TI113X: 
807 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 
808 /* This bit is shared, but may read as 0 on some chips, so set 
809 it explicitly on both functions. */ 
810 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 
811 /* CSC intr enable */ 
812 cbctl |= PCI113X_CBCTRL_PCI_CSC; 
813 /* functional intr prohibit | prohibit ISA routing */ 
814 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 
815 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 
816 break; 
817 
818 case CB_TI1420: 
819 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 
820 mrburst = pccbb_burstup 
821 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 
822 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 
823 printf("%s: %swrite bursts enabled\n", 
824 device_xname(sc->sc_dev), 
825 pccbb_burstup ? "read/" : ""); 
826 } else if (pccbb_burstup) { 
827 printf("%s: enabling read/write bursts\n", 
828 device_xname(sc->sc_dev)); 
829 sysctrl |= PCI1420_SYSCTRL_MRBURST; 
830 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 
831 } else { 
832 printf("%s: disabling read bursts, " 
833 "enabling write bursts\n", 
834 device_xname(sc->sc_dev)); 
835 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 
836 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 
837 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 
838 } 
839 /*FALLTHROUGH*/ 
840 case CB_TI12XX: 
841 /* 
842 * Some TI 12xx (and [14][45]xx) based pci cards 
843 * sometimes have issues with the MFUNC register not 
844 * being initialized due to a bad EEPROM on board. 
845 * Laptops that this matters on have this register 
846 * properly initialized. 
847 * 
848 * The TI125X parts have a different register. 
849 */ 
850 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 
851 if (mfunc == 0) { 
852 mfunc &= ~PCI12XX_MFUNC_PIN0; 
853 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 
854 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 
855 PCI12XX_SYSCTRL_INTRTIE) == 0) { 
856 mfunc &= ~PCI12XX_MFUNC_PIN1; 
857 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 
858 } 
859 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 
860 } 
861 /* fallthrough */ 
862 
863 case CB_TI125X: 
864 /* 
865 * Disable zoom video. Some machines initialize this 
866 * improperly and experience has shown that this helps 
867 * prevent strange behavior. 
868 */ 
869 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 
870 
871 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 
872 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 
873 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 
874 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 
875 cbctl |= PCI12XX_CBCTRL_CSC; 
876 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 
877 break; 
878 
879 case CB_TOPIC95B: 
880 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 
881 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 
882 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 
883 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 
884 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 
885 device_xname(sc->sc_dev), slotctl)); 
886 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 
887 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 
888 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 
889 DPRINTF(("0x%x\n", slotctl)); 
890 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 
891 break; 
892 
893 case CB_TOPIC97: 
894 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 
895 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 
896 device_xname(sc->sc_dev), slotctl)); 
897 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 
898 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 
899 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 
900 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 
901 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 
902 DPRINTF(("0x%x\n", slotctl)); 
903 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 
904 /* make sure to assert LV card support bits */ 
905 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 
906 0x800 + 0x3e, 
907 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 
908 0x800 + 0x3e) | 0x03); 
909 break; 
910 } 
911 
912 /* Close all memory and I/O windows. */ 
913 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 
914 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 
915 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 
916 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 
917 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 
918 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 
919 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 
920 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 
921 
922 /* reset 16-bit pcmcia bus */ 
923 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 
924 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 
925 
926 /* turn off power */ 
927 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 
928} 
929 
930static void 
931pccbb_intrinit(struct pccbb_softc *sc) 
932{ 
933 pcireg_t sockmask; 
934 const char *intrstr = NULL; 
935 pci_intr_handle_t ih; 
936 pci_chipset_tag_t pc = sc->sc_pc; 
937 bus_space_tag_t bmt = sc->sc_base_memt; 
938 bus_space_handle_t bmh = sc->sc_base_memh; 
939 
940 /* Map and establish the interrupt. */ 
941 if (pci_intr_map(&sc->sc_pa, &ih)) { 
942 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 
943 return; 
944 } 
945 intrstr = pci_intr_string(pc, ih); 
946 
947 /* 
948 * XXX pccbbintr should be called under the priority lower 
949 * than any other hard interupts. 
950 */ 
951 KASSERT(sc->sc_ih == NULL); 
952 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 
953 
954 if (sc->sc_ih == NULL) { 
955 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 
956 if (intrstr != NULL) 
957 aprint_error(" at %s\n", intrstr); 
958 else 
959 aprint_error("\n"); 
960 return; 
961 } 
962 
963 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 
964 
965 /* CSC Interrupt: Card detect and power cycle interrupts on */ 
966 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 
967 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 
968 CB_SOCKET_MASK_POWER; 
969 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 
970 /* reset interrupt */ 
971 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 
972 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 
973} 
974 
975/* 
976 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 
977 * struct pcmciabus_attach_args *paa) 
978 * 
979 * This function attaches 16-bit PCcard bus. 
980 */ 
981STATIC void 
982pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 
983 struct pcmciabus_attach_args *paa) 
984{ 
985#if rbus 
986 rbus_tag_t rb; 
987#endif 
988 /* 
989 * We need to do a few things here: 
990 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 
991 * setting the IRQ numbers to 0. 
992 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 
993 * routing of CSC interrupts (e.g. card removal) to PCI while in 
994 * PCMCIA mode. We just leave this set all the time. 
995 * 3) Enable card insertion/removal interrupts in case the chip also 
996 * needs that while in PCMCIA mode. 
997 * 4) Clear any pending CSC interrupt. 
998 */ 
999 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 
1000 if (sc->sc_chipset == CB_TI113X) { 
1001 Pcic_write(sc, PCIC_CSC_INTR, 0); 
1002 } else { 
1003 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 
1004 Pcic_read(sc, PCIC_CSC); 
1005 } 
1006 
1007 /* initialize pcmcia bus attachment */ 
1008 paa->paa_busname = "pcmcia"; 
1009 paa->pct = &pccbb_pcmcia_funcs; 
1010 paa->pch = sc; 
1011 paa->iobase = 0; /* I don't use them */ 
1012 paa->iosize = 0; 
1013#if rbus 
1014 rb = sc->sc_rbus_iot; 
1015 paa->iobase = rb->rb_start + rb->rb_offset; 
1016 paa->iosize = rb->rb_end - rb->rb_start; 
1017#endif 
1018 
1019 return; 
1020} 
1021 
1022/* 
1023 * int pccbbintr(arg) 
1024 * void *arg; 
1025 * This routine handles the interrupt from Yenta PCI-CardBus bridge 
1026 * itself. 
1027 */ 
1028int 
1029pccbbintr(void *arg) 
1030{ 
1031 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 
1032 u_int32_t sockevent, sockstate; 
1033 bus_space_tag_t memt = sc->sc_base_memt; 
1034 bus_space_handle_t memh = sc->sc_base_memh; 
1035 
1036 if (!device_has_power(sc->sc_dev)) 
1037 return 0; 
1038 
1039 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 
1040 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 
1041 Pcic_read(sc, PCIC_CSC); 
1042 
1043 if (sockevent != 0) { 
1044 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 
1045 sockevent); 
1046 } 
1047 
1048 /* Sometimes a change of CSTSCHG# accompanies the first 
1049 * interrupt from an Atheros WLAN. That generates a 
1050 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 
1051 * isn't interesting to pccbb(4), so we used to ignore the 
1052 * interrupt. Now, let the child devices try to handle 
1053 * the interrupt, instead. The Atheros NIC produces 
1054 * interrupts more reliably, now: used to be that it would 
1055 * only interrupt if the driver avoided powering down the 
1056 * NIC's cardslot, and then the NIC would only work after 
1057 * it was reset a second time. 
1058 */ 
1059 if (sockevent == 0 || 
1060 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 
1061 /* This intr is not for me: it may be for my child devices. */ 
1062 if (sc->sc_pil_intr_enable) { 
1063 return pccbbintr_function(sc); 
1064 } else { 
1065 return 0; 
1066 } 
1067 } 
1068 
1069 if (sockevent & CB_SOCKET_EVENT_CD) { 
1070 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 
1071 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 
1072 /* A card should be removed. */ 
1073 if (sc->sc_flags & CBB_CARDEXIST) { 
1074 DPRINTF(("%s: 0x%08x", 
1075 device_xname(sc->sc_dev), sockevent)); 
1076 DPRINTF((" card removed, 0x%08x\n", sockstate)); 
1077 sc->sc_flags &= ~CBB_CARDEXIST; 
1078 if (sc->sc_csc->sc_status & 
1079 CARDSLOT_STATUS_CARD_16) { 
1080 cardslot_event_throw(sc->sc_csc, 
1081 CARDSLOT_EVENT_REMOVAL_16); 
1082 } else if (sc->sc_csc->sc_status & 
1083 CARDSLOT_STATUS_CARD_CB) { 
1084 /* Cardbus intr removed */ 
1085 cardslot_event_throw(sc->sc_csc, 
1086 CARDSLOT_EVENT_REMOVAL_CB); 
1087 } 
1088 } else if (sc->sc_flags & CBB_INSERTING) { 
1089 sc->sc_flags &= ~CBB_INSERTING; 
1090 callout_stop(&sc->sc_insert_ch); 
1091 } 
1092 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 
1093 /* 
1094 * The pccbbintr may called from powerdown hook when 
1095 * the system resumed, to detect the card 
1096 * insertion/removal during suspension. 
1097 */ 
1098 (sc->sc_flags & CBB_CARDEXIST) == 0) { 
1099 if (sc->sc_flags & CBB_INSERTING) { 
1100 callout_stop(&sc->sc_insert_ch); 
1101 } 
1102 callout_schedule(&sc->sc_insert_ch, hz / 5); 
1103 sc->sc_flags |= CBB_INSERTING; 
1104 } 
1105 } 
1106 
1107 /* XXX sockevent == 9 does occur in the wild. handle it. */ 
1108 if (sockevent & CB_SOCKET_EVENT_POWER) { 
1109 DPRINTF(("Powercycling because of socket event\n")); 
1110 /* XXX: Does not happen when attaching a 16-bit card */ 
1111 sc->sc_pwrcycle++; 
1112 wakeup(&sc->sc_pwrcycle); 
1113 } 
1114 
1115 return (1); 
1116} 
1117 
1118/* 
1119 * static int pccbbintr_function(struct pccbb_softc *sc) 
1120 * 
1121 * This function calls each interrupt handler registered at the 
1122 * bridge. The interrupt handlers are called in registered order. 
1123 */ 
1124static int 
1125pccbbintr_function(struct pccbb_softc *sc) 
1126{ 
1127 int retval = 0, val; 
1128 struct pccbb_intrhand_list *pil; 
1129 int s; 
1130 
1131 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 
1132 s = splraiseipl(pil->pil_icookie); 
1133 val = (*pil->pil_func)(pil->pil_arg); 
1134 splx(s); 
1135 
1136 retval = retval == 1 ? 1 : 
1137 retval == 0 ? val : val != 0 ? val : retval; 
1138 } 
1139 
1140 return retval; 
1141} 
1142 
1143static void 
1144pci113x_insert(void *arg) 
1145{ 
1146 struct pccbb_softc *sc = arg; 
1147 u_int32_t sockevent, sockstate; 
1148 
1149 if (!(sc->sc_flags & CBB_INSERTING)) { 
1150 /* We add a card only under inserting state. */ 
1151 return; 
1152 } 
1153 sc->sc_flags &= ~CBB_INSERTING; 
1154 
1155 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 
1156 CB_SOCKET_EVENT); 
1157 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 
1158 CB_SOCKET_STAT); 
1159 
1160 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 
1161 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 
1162 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 
1163 sc->sc_flags |= CBB_CARDEXIST; 
1164 /* call pccard interrupt handler here */ 
1165 if (sockstate & CB_SOCKET_STAT_16BIT) { 
1166 /* 16-bit card found */ 
1167 cardslot_event_throw(sc->sc_csc, 
1168 CARDSLOT_EVENT_INSERTION_16); 
1169 } else if (sockstate & CB_SOCKET_STAT_CB) { 
1170 /* cardbus card found */ 
1171 cardslot_event_throw(sc->sc_csc, 
1172 CARDSLOT_EVENT_INSERTION_CB); 
1173 } else { 
1174 /* who are you? */ 
1175 } 
1176 } else { 
1177 callout_schedule(&sc->sc_insert_ch, hz / 10); 
1178 } 
1179} 
1180 
1181#define PCCBB_PCMCIA_OFFSET 0x800 
1182static u_int8_t 
1183pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 
1184{ 
1185 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 
1186 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 
1187 
1188 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 
1189 PCCBB_PCMCIA_OFFSET + reg); 
1190} 
1191 
1192static void 
1193pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 
1194{ 
1195 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 
1196 PCCBB_PCMCIA_OFFSET + reg, val); 
1197 
1198 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 
1199 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 
1200} 
1201 
1202/* 
1203 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 
1204 */ 
1205STATIC int 
1206pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 
1207{ 
1208 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 
1209 
1210 switch (command) { 
1211 case CARDBUS_CD: 
1212 if (2 == pccbb_detect_card(sc)) { 
1213 int retval = 0; 
1214 int status = cb_detect_voltage(sc); 
1215 if (PCCARD_VCC_5V & status) { 
1216 retval |= CARDBUS_5V_CARD; 
1217 } 
1218 if (PCCARD_VCC_3V & status) { 
1219 retval |= CARDBUS_3V_CARD; 
1220 } 
1221 if (PCCARD_VCC_XV & status) { 
1222 retval |= CARDBUS_XV_CARD; 
1223 } 
1224 if (PCCARD_VCC_YV & status) { 
1225 retval |= CARDBUS_YV_CARD; 
1226 } 
1227 return retval; 
1228 } else { 
1229 return 0; 
1230 } 
1231 case CARDBUS_RESET: 
1232 return cb_reset(sc); 
1233 case CARDBUS_IO_ENABLE: /* fallthrough */ 
1234 case CARDBUS_IO_DISABLE: /* fallthrough */ 
1235 case CARDBUS_MEM_ENABLE: /* fallthrough */ 
1236 case CARDBUS_MEM_DISABLE: /* fallthrough */ 
1237 case CARDBUS_BM_ENABLE: /* fallthrough */ 
1238 case CARDBUS_BM_DISABLE: /* fallthrough */ 
1239 /* XXX: I think we don't need to call this function below. */ 
1240 return pccbb_cardenable(sc, command); 
1241 } 
1242 
1243 return 0; 
1244} 
1245 
1246STATIC int 
1247pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 
1248{ 
1249 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 
1250 
1251 return pccbb_power(sc, command); 
1252} 
1253 
1254/* 
1255 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 
1256 * This function returns true when it succeeds and returns false when 
1257 * it fails. 
1258 */ 
1259STATIC int 
1260pccbb_power(struct pccbb_softc *sc, int command) 
1261{ 
1262 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 
1263 bus_space_tag_t memt = sc->sc_base_memt; 
1264 bus_space_handle_t memh = sc->sc_base_memh; 
1265 int on = 0, pwrcycle, s, times; 
1266 struct timeval before, after, diff; 
1267 
1268 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 
1269 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 
1270 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 
1271 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 
1272 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 
1273 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 
1274 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 
1275 "UNKNOWN", 
1276 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 
1277 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 
1278 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 
1279 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 
1280 "UNKNOWN", command)); 
1281 
1282 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 
1283 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 
1284 
1285 switch (command & CARDBUS_VCCMASK) { 
1286 case CARDBUS_VCC_UC: 
1287 break; 
1288 case CARDBUS_VCC_5V: 
1289 on++; 
1290 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 
1291 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 
1292 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 
1293 } else { 
1294 aprint_error_dev(sc->sc_dev, 
1295 "BAD voltage request: no 5 V card\n"); 
1296 return 0; 
1297 } 
1298 break; 
1299 case CARDBUS_VCC_3V: 
1300 on++; 
1301 if (CB_SOCKET_STAT_3VCARD & status) { 
1302 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 
1303 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 
1304 } else { 
1305 aprint_error_dev(sc->sc_dev, 
1306 "BAD voltage request: no 3.3 V card\n"); 
1307 return 0; 
1308 } 
1309 break; 
1310 case CARDBUS_VCC_0V: 
1311 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 
1312 break; 
1313 default: 
1314 return 0; /* power NEVER changed */ 
1315 } 
1316 
1317 switch (command & CARDBUS_VPPMASK) { 
1318 case CARDBUS_VPP_UC: 
1319 break; 
1320 case CARDBUS_VPP_0V: 
1321 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 
1322 break; 
1323 case CARDBUS_VPP_VCC: 
1324 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 
1325 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 
1326 break; 
1327 case CARDBUS_VPP_12V: 
1328 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 
1329 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 
1330 break; 
1331 } 
1332 
1333 pwrcycle = sc->sc_pwrcycle; 
1334 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 
1335 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 
1336 
1337 microtime(&before); 
1338 s = splbio(); 
1339 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 
1340 
1341 /* 
1342 * Wait as long as 200ms for a power-cycle interrupt. If 
1343 * interrupts are enabled, but the socket has already 
1344 * changed to the desired status, keep waiting for the 
1345 * interrupt. "Consuming" the interrupt in this way keeps 
1346 * the interrupt from prematurely waking some subsequent 
1347 * pccbb_power call. 
1348 * 
1349 * XXX Not every bridge interrupts on the ->OFF transition. 
1350 * XXX That's ok, we will time-out after 200ms. 
1351 * 
1352 * XXX The power cycle event will never happen when attaching 
1353 * XXX a 16-bit card. That's ok, we will time-out after 
1354 * XXX 200ms. 
1355 */ 
1356 for (times = 5; --times >= 0; ) { 
1357 if (cold) 
1358 DELAY(40 * 1000); 
1359 else { 
1360 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 
1361 hz / 25); 
1362 if (pwrcycle == sc->sc_pwrcycle) 
1363 continue; 
1364 } 
1365 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 
1366 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 
1367 break; 
1368 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 
1369 break; 
1370 } 
1371 splx(s); 
1372 microtime(&after); 
1373 timersub(&after, &before, &diff); 
1374 aprint_debug_dev(sc->sc_dev, "wait took%s %ld.%06lds\n", 
1375 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 
1376 
1377 /* 
1378 * Ok, wait a bit longer for things to settle. 
1379 */ 
1380 if (on && sc->sc_chipset == CB_TOPIC95B) 
1381 delay_ms(100, sc); 
1382 
1383 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 
1384 
1385 if (on && sc->sc_chipset != CB_TOPIC95B) { 
1386 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 
1387 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 
1388 } 
1389 
1390 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 
1391 aprint_error_dev(sc->sc_dev, 
1392 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 
1393 sock_ctrl, status); 
1394 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 
1395 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 
1396 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 
1397 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 
1398 status &= ~CB_SOCKET_STAT_BADVCC; 
1399 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 
1400 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 
1401 CB_SOCKET_STAT)); 
1402 return 0; 
1403 } 
1404 
1405 if (sc->sc_chipset == CB_TOPIC97) { 
1406 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 
1407 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 
1408 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 
1409 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 
1410 else 
1411 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 
1412 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 
1413 } 
1414 
1415 return 1; /* power changed correctly */ 
1416} 
1417 
1418/* 
1419 * static int pccbb_detect_card(struct pccbb_softc *sc) 
1420 * return value: 0 if no card exists. 
1421 * 1 if 16-bit card exists. 
1422 * 2 if cardbus card exists. 
1423 */ 
1424static int 
1425pccbb_detect_card(struct pccbb_softc *sc) 
1426{ 
1427 bus_space_handle_t base_memh = sc->sc_base_memh; 
1428 bus_space_tag_t base_memt = sc->sc_base_memt; 
1429 u_int32_t sockstat = 
1430 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 
1431 int retval = 0; 
1432 
1433 /* CD1 and CD2 asserted */ 
1434 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 
1435 /* card must be present */ 
1436 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 
1437 /* NOTACARD DEASSERTED */ 
1438 if (CB_SOCKET_STAT_CB & sockstat) { 
1439 /* CardBus mode */ 
1440 retval = 2; 
1441 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 
1442 /* 16-bit mode */ 
1443 retval = 1; 
1444 } 
1445 } 
1446 } 
1447 return retval; 
1448} 
1449 
1450/* 
1451 * STATIC int cb_reset(struct pccbb_softc *sc) 
1452 * This function resets CardBus card. 
1453 */ 
1454STATIC int 
1455cb_reset(struct pccbb_softc *sc) 
1456{ 
1457 /* 
1458 * Reset Assert at least 20 ms 
1459 * Some machines request longer duration. 
1460 */ 
1461 int reset_duration = 
1462 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 
1463 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 
1464 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 
1465 
1466 /* Reset bit Assert (bit 6 at 0x3E) */ 
1467 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 
1468 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 
1469 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 
1470 delay_ms(reset_duration, sc); 
1471 
1472 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 
1473 /* Reset bit Deassert (bit 6 at 0x3E) */ 
1474 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 
1475 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 
1476 bcr); 
1477 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 
1478 delay_ms(reset_duration, sc); 
1479 aprint_debug("%s: end of delay\n", __func__); 
1480 } 
1481 /* No card found on the slot. Keep Reset. */ 
1482 return 1; 
1483} 
1484 
1485/* 
1486 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 
1487 * This function detect card Voltage. 
1488 */ 
1489STATIC int 
1490cb_detect_voltage(struct pccbb_softc *sc) 
1491{ 
1492 u_int32_t psr; /* socket present-state reg */ 
1493 bus_space_tag_t iot = sc->sc_base_memt; 
1494 bus_space_handle_t ioh = sc->sc_base_memh; 
1495 int vol = PCCARD_VCC_UKN; /* set 0 */ 
1496 
1497 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 
1498 
1499 if (0x400u & psr) { 
1500 vol |= PCCARD_VCC_5V; 
1501 } 
1502 if (0x800u & psr) { 
1503 vol |= PCCARD_VCC_3V; 
1504 } 
1505 
1506 return vol; 
1507} 
1508 
1509STATIC int 
1510cbbprint(void *aux, const char *pcic) 
1511{ 
1512#if 0 
1513 struct cbslot_attach_args *cba = aux; 
1514 
1515 if (cba->cba_slot >= 0) { 
1516 aprint_normal(" slot %d", cba->cba_slot); 
1517 } 
1518#endif 
1519 return UNCONF; 
1520} 
1521 
1522/* 
1523 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 
1524 * This function enables and disables the card 
1525 */ 
1526STATIC int 
1527pccbb_cardenable(struct pccbb_softc *sc, int function) 
1528{ 
1529 u_int32_t command = 
1530 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 
1531 
1532 DPRINTF(("pccbb_cardenable:")); 
1533 switch (function) { 
1534 case CARDBUS_IO_ENABLE: 
1535 command |= PCI_COMMAND_IO_ENABLE; 
1536 break; 
1537 case CARDBUS_IO_DISABLE: 
1538 command &= ~PCI_COMMAND_IO_ENABLE; 
1539 break; 
1540 case CARDBUS_MEM_ENABLE: 
1541 command |= PCI_COMMAND_MEM_ENABLE; 
1542 break; 
1543 case CARDBUS_MEM_DISABLE: 
1544 command &= ~PCI_COMMAND_MEM_ENABLE; 
1545 break; 
1546 case CARDBUS_BM_ENABLE: 
1547 command |= PCI_COMMAND_MASTER_ENABLE; 
1548 break; 
1549 case CARDBUS_BM_DISABLE: 
1550 command &= ~PCI_COMMAND_MASTER_ENABLE; 
1551 break; 
1552 default: 
1553 return 0; 
1554 } 
1555 
1556 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 
1557 DPRINTF((" command reg 0x%x\n", command)); 
1558 return 1; 
1559} 
1560 
1561#if !rbus 
1562static int 
1563pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 
1564{ 
1565 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 
1566 int basereg; 
1567 int limitreg; 
1568 
1569 if ((win < 0) || (win > 2)) { 
1570#if defined DIAGNOSTIC 
1571 printf("cardbus_io_open: window out of range %d\n", win); 
1572#endif 
1573 return 0; 
1574 } 
1575 
1576 basereg = win * 8 + PCI_CB_IOBASE0; 
1577 limitreg = win * 8 + PCI_CB_IOLIMIT0; 
1578 
1579 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 
1580 start, basereg, end, limitreg)); 
1581 
1582 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 
1583 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 
1584 return 1; 
1585} 
1586 
1587/* 
1588 * int pccbb_io_close(cardbus_chipset_tag_t, int) 
1589 */ 
1590static int 
1591pccbb_io_close(cardbus_chipset_tag_t ct, int win) 
1592{ 
1593 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 
1594 int basereg; 
1595 int limitreg; 
1596 
1597 if ((win < 0) || (win > 2)) { 
1598#if defined DIAGNOSTIC 
1599 printf("cardbus_io_close: window out of range %d\n", win); 
1600#endif 
1601 return 0; 
1602 } 
1603 
1604 basereg = win * 8 + PCI_CB_IOBASE0; 
1605 limitreg = win * 8 + PCI_CB_IOLIMIT0; 
1606 
1607 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 
1608 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 
1609 return 1; 
1610} 
1611 
1612static int 
1613pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 
1614{ 
1615 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 
1616 int basereg; 
1617 int limitreg; 
1618 
1619 if ((win < 0) || (win > 2)) { 
1620#if defined DIAGNOSTIC 
1621 printf("cardbus_mem_open: window out of range %d\n", win); 
1622#endif 
1623 return 0; 
1624 } 
1625 
1626 basereg = win * 8 + PCI_CB_MEMBASE0; 
1627 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 
1628 
1629 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 
1630 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 
1631 return 1; 
1632} 
1633 
1634static int 
1635pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 
1636{ 
1637 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 
1638 int basereg; 
1639 int limitreg; 
1640 
1641 if ((win < 0) || (win > 2)) { 
1642#if defined DIAGNOSTIC 
1643 printf("cardbus_mem_close: window out of range %d\n", win); 
1644#endif 
1645 return 0; 
1646 } 
1647 
1648 basereg = win * 8 + PCI_CB_MEMBASE0; 
1649 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 
1650 
1651 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 
1652 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 
1653 return 1; 
1654} 
1655#endif 
1656 
1657/* 
1658 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 
1659 * int irq, 
1660 * int level, 
1661 * int (* func)(void *), 
1662 * void *arg) 
1663 * 
1664 * This function registers an interrupt handler at the bridge, in 
1665 * order not to call the interrupt handlers of child devices when 
1666 * a card-deletion interrupt occurs. 
1667 * 
1668 * The arguments irq and level are not used. 
1669 */ 
1670static void * 
1671pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 
1672 int level, int (*func)(void *), void *arg) 
1673{ 
1674 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 
1675 
1676 return pccbb_intr_establish(sc, irq, level, func, arg); 
1677} 
1678 
1679 
1680/* 
1681 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 
1682 * void *ih) 
1683 * 
1684 * This function removes an interrupt handler pointed by ih. 
1685 */ 
1686static void 
1687pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 
1688{ 
1689 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 
1690 
1691 pccbb_intr_disestablish(sc, ih); 
1692} 
1693 
1694 
1695void 
1696pccbb_intr_route(struct pccbb_softc *sc) 
1697{ 
1698 pcireg_t bcr, cbctrl; 
1699 
1700 /* initialize bridge intr routing */ 
1701 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 
1702 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 
1703 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 
1704 
1705 switch (sc->sc_chipset) { 
1706 case CB_TI113X: 
1707 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 
1708 /* functional intr enabled */ 
1709 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 
1710 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 
1711 break; 
1712 default: 
1713 break; 
1714 } 
1715} 
1716 
1717/* 
1718 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 
1719 * int irq, 
1720 * int level, 
1721 * int (* func)(void *), 
1722 * void *arg) 
1723 * 
1724 * This function registers an interrupt handler at the bridge, in 
1725 * order not to call the interrupt handlers of child devices when 
1726 * a card-deletion interrupt occurs. 
1727 * 
1728 * The arguments irq is not used because pccbb selects intr vector. 
1729 */ 
1730static void * 
1731pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 
1732 int level, int (*func)(void *), void *arg) 
1733{ 
1734 struct pccbb_intrhand_list *pil, *newpil; 
1735 
1736 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 
1737 
1738 if (LIST_EMPTY(&sc->sc_pil)) { 
1739 pccbb_intr_route(sc); 
1740 } 
1741 
1742 /* 
1743 * Allocate a room for interrupt handler structure. 
1744 */ 
1745 if (NULL == (newpil = 
1746 (struct pccbb_intrhand_list *)malloc(sizeof(struct 
1747 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 
1748 return NULL; 
1749 } 
1750 
1751 newpil->pil_func = func; 
1752 newpil->pil_arg = arg; 
1753 newpil->pil_icookie = makeiplcookie(level); 
1754 
1755 if (LIST_EMPTY(&sc->sc_pil)) { 
1756 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 
1757 } else { 
1758 for (pil = LIST_FIRST(&sc->sc_pil); 
1759 LIST_NEXT(pil, pil_next) != NULL; 
1760 pil = LIST_NEXT(pil, pil_next)); 
1761 LIST_INSERT_AFTER(pil, newpil, pil_next); 
1762 } 
1763 
1764 DPRINTF(("pccbb_intr_establish add pil. %p\n", 
1765 LIST_FIRST(&sc->sc_pil))); 
1766 
1767 return newpil; 
1768} 
1769 
1770/* 
1771 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 
1772 * void *ih) 
1773 * 
1774 * This function removes an interrupt handler pointed by ih. ih 
1775 * should be the value returned by cardbus_intr_establish() or 
1776 * NULL. 
1777 * 
1778 * When ih is NULL, this function will do nothing. 
1779 */ 
1780static void 
1781pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 
1782{ 
1783 struct pccbb_intrhand_list *pil; 
1784 pcireg_t reg; 
1785 
1786 DPRINTF(("pccbb_intr_disestablish start. %p\n", 
1787 LIST_FIRST(&sc->sc_pil))); 
1788 
1789 if (ih == NULL) { 
1790 /* intr handler is not set */ 
1791 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 
1792 return; 
1793 } 
1794 
1795#ifdef DIAGNOSTIC 
1796 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 
1797 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 
1798 if (pil == ih) { 
1799 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 
1800 break; 
1801 } 
1802 } 
1803 if (pil == NULL) { 
1804 panic("pccbb_intr_disestablish: %s cannot find pil %p", 
1805 device_xname(sc->sc_dev), ih); 
1806 } 
1807#endif 
1808 
1809 pil = (struct pccbb_intrhand_list *)ih; 
1810 LIST_REMOVE(pil, pil_next); 
1811 free(pil, M_DEVBUF); 
1812 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 
1813 
1814 if (LIST_EMPTY(&sc->sc_pil)) { 
1815 /* No interrupt handlers */ 
1816 
1817 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 
1818 
1819 /* stop routing PCI intr */ 
1820 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 
1821 reg |= CB_BCR_INTR_IREQ_ENABLE; 
1822 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 
1823 
1824 switch (sc->sc_chipset) { 
1825 case CB_TI113X: 
1826 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 
1827 /* functional intr disabled */ 
1828 reg &= ~PCI113X_CBCTRL_PCI_INTR; 
1829 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 
1830 break; 
1831 default: 
1832 break; 
1833 } 
1834 } 
1835} 
1836 
1837#if defined SHOW_REGS 
1838static void 
1839cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 
1840 bus_space_handle_t memh) 
1841{ 
1842 int i; 
1843 printf("PCI config regs:"); 
1844 for (i = 0; i < 0x50; i += 4) { 
1845 if (i % 16 == 0) 
1846 printf("\n 0x%02x:", i); 
1847 printf(" %08x", pci_conf_read(pc, tag, i)); 
1848 } 
1849 for (i = 0x80; i < 0xb0; i += 4) { 
1850 if (i % 16 == 0) 
1851 printf("\n 0x%02x:", i); 
1852 printf(" %08x", pci_conf_read(pc, tag, i)); 
1853 } 
1854 
1855 if (memh == 0) { 
1856 printf("\n"); 
1857 return; 
1858 } 
1859 
1860 printf("\nsocket regs:"); 
1861 for (i = 0; i <= 0x10; i += 0x04) 
1862 printf(" %08x", bus_space_read_4(memt, memh, i)); 
1863 printf("\nExCA regs:"); 
1864 for (i = 0; i < 0x08; ++i) 
1865 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 
1866 printf("\n"); 
1867 return; 
1868} 
1869#endif 
1870 
1871/* 
1872 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 
1873 * int busno, int function) 
1874 * This is the function to make a tag to access config space of 
1875 * a CardBus Card. It works same as pci_conf_read. 
1876 */ 
1877static cardbustag_t 
1878pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 
1879{ 
1880 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 
1881 
1882 return pci_make_tag(sc->sc_pc, busno, 0, function); 
1883} 
1884 
1885static void 
1886pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 
1887{ 
1888} 
1889 
1890/* 
1891 * pccbb_conf_read 
1892 * 
1893 * This is the function to read the config space of a CardBus card. 
1894 * It works the same as pci_conf_read(9). 
1895 */ 
1896static cardbusreg_t 
1897pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 
1898{ 
1899 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 
1900 pcitag_t brtag = sc->sc_tag; 
1901 cardbusreg_t reg; 
1902 
1903 /* 
1904 * clear cardbus master abort status; it is OK to write without 
1905 * reading before because all bits are r/o or w1tc 
1906 */ 
1907 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 
1908 CBB_SECSTATUS_CBMABORT); 
1909 reg = pci_conf_read(sc->sc_pc, tag, offset); 
1910 /* check cardbus master abort status */ 
1911 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 
1912 & CBB_SECSTATUS_CBMABORT) 
1913 return (0xffffffff); 
1914 return reg; 
1915} 
1916 
1917/* 
1918 * pccbb_conf_write 
1919 * 
1920 * This is the function to write the config space of a CardBus 
1921 * card. It works the same as pci_conf_write(9). 
1922 */ 
1923static void 
1924pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 
1925 cardbusreg_t val) 
1926{ 
1927 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 
1928 
1929 pci_conf_write(sc->sc_pc, tag, reg, val); 
1930} 
1931 
1932#if 0 
1933STATIC int 
1934pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 
1935 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 
1936 int speed, int flags, 
1937 bus_space_handle_t * iohp) 
1938#endif 
1939/* 
1940 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 
1941 * bus_addr_t start, bus_size_t size, 
1942 * bus_size_t align, 
1943 * struct pcmcia_io_handle *pcihp 
1944 * 
1945 * This function only allocates I/O region for pccard. This function 
1946 * never maps the allocated region to pccard I/O area. 
1947 * 
1948 * XXX: The interface of this function is not very good, I believe. 
1949 */ 
1950STATIC int 
1951pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 
1952 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 
1953{ 
1954 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
1955 bus_addr_t ioaddr; 
1956 int flags = 0; 
1957 bus_space_tag_t iot; 
1958 bus_space_handle_t ioh; 
1959 bus_addr_t mask; 
1960#if rbus 
1961 rbus_tag_t rb; 
1962#endif 
1963 if (align == 0) { 
1964 align = size; /* XXX: funny??? */ 
1965 } 
1966 
1967 if (start != 0) { 
1968 /* XXX: assume all card decode lower 10 bits by its hardware */ 
1969 mask = 0x3ff; 
1970 /* enforce to use only masked address */ 
1971 start &= mask; 
1972 } else { 
1973 /* 
1974 * calculate mask: 
1975 * 1. get the most significant bit of size (call it msb). 
1976 * 2. compare msb with the value of size. 
1977 * 3. if size is larger, shift msb left once. 
1978 * 4. obtain mask value to decrement msb. 
1979 */ 
1980 bus_size_t size_tmp = size; 
1981 int shifts = 0; 
1982 
1983 mask = 1; 
1984 while (size_tmp) { 
1985 ++shifts; 
1986 size_tmp >>= 1; 
1987 } 
1988 mask = (1 << shifts); 
1989 if (mask < size) { 
1990 mask <<= 1; 
1991 } 
1992 --mask; 
1993 } 
1994 
1995 /* 
1996 * Allocate some arbitrary I/O space. 
1997 */ 
1998 
1999 iot = sc->sc_iot; 
2000 
2001#if rbus 
2002 rb = sc->sc_rbus_iot; 
2003 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 
2004 return 1; 
2005 } 
2006 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 
2007 (u_long) ioaddr, (u_long) size)); 
2008#else 
2009 if (start) { 
2010 ioaddr = start; 
2011 if (bus_space_map(iot, start, size, 0, &ioh)) { 
2012 return 1; 
2013 } 
2014 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 
2015 (u_long) ioaddr, (u_long) size)); 
2016 } else { 
2017 flags |= PCMCIA_IO_ALLOCATED; 
2018 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 
2019 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 
2020 size, align, 0, 0, &ioaddr, &ioh)) { 
2021 /* No room be able to be get. */ 
2022 return 1; 
2023 } 
2024 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 
2025 (u_long) ioaddr, (u_long) size)); 
2026 } 
2027#endif 
2028 
2029 pcihp->iot = iot; 
2030 pcihp->ioh = ioh; 
2031 pcihp->addr = ioaddr; 
2032 pcihp->size = size; 
2033 pcihp->flags = flags; 
2034 
2035 return 0; 
2036} 
2037 
2038/* 
2039 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 
2040 * struct pcmcia_io_handle *pcihp) 
2041 * 
2042 * This function only frees I/O region for pccard. 
2043 * 
2044 * XXX: The interface of this function is not very good, I believe. 
2045 */ 
2046void 
2047pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 
2048 struct pcmcia_io_handle *pcihp) 
2049{ 
2050 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2051#if !rbus 
2052 bus_space_tag_t iot = pcihp->iot; 
2053#endif 
2054 bus_space_handle_t ioh = pcihp->ioh; 
2055 bus_size_t size = pcihp->size; 
2056 
2057#if rbus 
2058 rbus_tag_t rb = sc->sc_rbus_iot; 
2059 
2060 rbus_space_free(rb, ioh, size, NULL); 
2061#else 
2062 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 
2063 bus_space_free(iot, ioh, size); 
2064 else 
2065 bus_space_unmap(iot, ioh, size); 
2066#endif 
2067} 
2068 
2069/* 
2070 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 
2071 * bus_addr_t offset, bus_size_t size, 
2072 * struct pcmcia_io_handle *pcihp, 
2073 * int *windowp) 
2074 * 
2075 * This function maps the allocated I/O region to pccard. This function 
2076 * never allocates any I/O region for pccard I/O area. I don't 
2077 * understand why the original authors of pcmciabus separated alloc and 
2078 * map. I believe the two must be unite. 
2079 * 
2080 * XXX: no wait timing control? 
2081 */ 
2082int 
2083pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 
2084 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 
2085{ 
2086 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2087 struct pcic_handle *ph = &sc->sc_pcmcia_h; 
2088 bus_addr_t ioaddr = pcihp->addr + offset; 
2089 int i, win; 
2090#if defined CBB_DEBUG 
2091 static const char *width_names[] = { "dynamic", "io8", "io16" }; 
2092#endif 
2093 
2094 /* Sanity check I/O handle. */ 
2095 
2096 if (sc->sc_iot != pcihp->iot) { 
2097 panic("pccbb_pcmcia_io_map iot is bogus"); 
2098 } 
2099 
2100 /* XXX Sanity check offset/size. */ 
2101 
2102 win = -1; 
2103 for (i = 0; i < PCIC_IO_WINS; i++) { 
2104 if ((ph->ioalloc & (1 << i)) == 0) { 
2105 win = i; 
2106 ph->ioalloc |= (1 << i); 
2107 break; 
2108 } 
2109 } 
2110 
2111 if (win == -1) { 
2112 return 1; 
2113 } 
2114 
2115 *windowp = win; 
2116 
2117 /* XXX this is pretty gross */ 
2118 
2119 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 
2120 win, width_names[width], (u_long) ioaddr, (u_long) size)); 
2121 
2122 /* XXX wtf is this doing here? */ 
2123 
2124#if 0 
2125 printf(" port 0x%lx", (u_long) ioaddr); 
2126 if (size > 1) { 
2127 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 
2128 } 
2129#endif 
2130 
2131 ph->io[win].addr = ioaddr; 
2132 ph->io[win].size = size; 
2133 ph->io[win].width = width; 
2134 
2135 /* actual dirty register-value changing in the function below. */ 
2136 pccbb_pcmcia_do_io_map(sc, win); 
2137 
2138 return 0; 
2139} 
2140 
2141/* 
2142 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 
2143 * 
2144 * This function changes register-value to map I/O region for pccard. 
2145 */ 
2146static void 
2147pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 
2148{ 
2149 static u_int8_t pcic_iowidth[3] = { 
2150 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 
2151 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 
2152 PCIC_IOCTL_IO0_DATASIZE_8BIT, 
2153 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 
2154 PCIC_IOCTL_IO0_DATASIZE_16BIT, 
2155 }; 
2156 
2157#define PCIC_SIA_START_LOW 0 
2158#define PCIC_SIA_START_HIGH 1 
2159#define PCIC_SIA_STOP_LOW 2 
2160#define PCIC_SIA_STOP_HIGH 3 
2161 
2162 int regbase_win = 0x8 + win * 0x04; 
2163 u_int8_t ioctl, enable; 
2164 struct pcic_handle *ph = &sc->sc_pcmcia_h; 
2165 
2166 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 
2167 "width %d\n", win, (unsigned long)ph->io[win].addr, 
2168 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 
2169 
2170 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 
2171 ph->io[win].addr & 0xff); 
2172 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 
2173 (ph->io[win].addr >> 8) & 0xff); 
2174 
2175 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 
2176 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 
2177 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 
2178 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 
2179 
2180 ioctl = Pcic_read(sc, PCIC_IOCTL); 
2181 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 
2182 switch (win) { 
2183 case 0: 
2184 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 
2185 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 
2186 PCIC_IOCTL_IO0_DATASIZE_MASK); 
2187 ioctl |= pcic_iowidth[ph->io[win].width]; 
2188 enable |= PCIC_ADDRWIN_ENABLE_IO0; 
2189 break; 
2190 case 1: 
2191 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 
2192 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 
2193 PCIC_IOCTL_IO1_DATASIZE_MASK); 
2194 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 
2195 enable |= PCIC_ADDRWIN_ENABLE_IO1; 
2196 break; 
2197 } 
2198 Pcic_write(sc, PCIC_IOCTL, ioctl); 
2199 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 
2200#if defined(CBB_DEBUG) 
2201 { 
2202 u_int8_t start_low = 
2203 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 
2204 u_int8_t start_high = 
2205 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 
2206 u_int8_t stop_low = 
2207 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 
2208 u_int8_t stop_high = 
2209 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 
2210 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 
2211 "stop %02x %02x, ioctl %02x enable %02x\n", 
2212 start_low, start_high, stop_low, stop_high, ioctl, enable); 
2213 } 
2214#endif 
2215} 
2216 
2217/* 
2218 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 
2219 * 
2220 * This function unmaps I/O region. No return value. 
2221 */ 
2222STATIC void 
2223pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 
2224{ 
2225 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2226 struct pcic_handle *ph = &sc->sc_pcmcia_h; 
2227 int reg; 
2228 
2229 if (win >= PCIC_IO_WINS || win < 0) { 
2230 panic("pccbb_pcmcia_io_unmap: window out of range"); 
2231 } 
2232 
2233 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 
2234 switch (win) { 
2235 case 0: 
2236 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 
2237 break; 
2238 case 1: 
2239 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 
2240 break; 
2241 } 
2242 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 
2243 
2244 ph->ioalloc &= ~(1 << win); 
2245} 
2246 
2247static int 
2248pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 
2249{ 
2250 u_int8_t stat; 
2251 int i; 
2252 
2253 /* wait an initial 10ms for quick cards */ 
2254 stat = Pcic_read(sc, PCIC_IF_STATUS); 
2255 if (stat & PCIC_IF_STATUS_READY) 
2256 return (0); 
2257 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 
2258 for (i = 0; i < 50; i++) { 
2259 stat = Pcic_read(sc, PCIC_IF_STATUS); 
2260 if (stat & PCIC_IF_STATUS_READY) 
2261 return (0); 
2262 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 
2263 PCIC_IF_STATUS_CARDDETECT_PRESENT) 
2264 return (ENXIO); 
2265 /* wait .1s (100ms) each iteration now */ 
2266 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 
2267 } 
2268 
2269 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 
2270 return (EWOULDBLOCK); 
2271} 
2272 
2273/* 
2274 * Perform long (msec order) delay. timo is in milliseconds. 
2275 */ 
2276static void 
2277pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 
2278{ 
2279#ifdef DIAGNOSTIC 
2280 if (timo <= 0) 
2281 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 
2282 if (!curlwp) 
2283 panic("pccbb_pcmcia_delay: called in interrupt context"); 
2284#endif 
2285 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 
2286 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 
2287} 
2288 
2289/* 
2290 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 
2291 * 
2292 * This function enables the card. All information is stored in 
2293 * the first argument, pcmcia_chipset_handle_t. 
2294 */ 
2295STATIC void 
2296pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 
2297{ 
2298 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2299 struct pcic_handle *ph = &sc->sc_pcmcia_h; 
2300 pcireg_t spsr; 
2301 int voltage; 
2302 int win; 
2303 u_int8_t power, intr; 
2304#ifdef DIAGNOSTIC 
2305 int reg; 
2306#endif 
2307 
2308 /* this bit is mostly stolen from pcic_attach_card */ 
2309 
2310 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 
2311 
2312 /* get card Vcc info */ 
2313 spsr = 
2314 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 
2315 CB_SOCKET_STAT); 
2316 if (spsr & CB_SOCKET_STAT_5VCARD) { 
2317 DPRINTF(("5V card\n")); 
2318 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 
2319 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 
2320 DPRINTF(("3V card\n")); 
2321 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 
2322 } else { 
2323 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 
2324 return; 
2325 } 
2326 
2327 /* disable interrupts; assert RESET */ 
2328 intr = Pcic_read(sc, PCIC_INTR); 
2329 intr &= PCIC_INTR_ENABLE; 
2330 Pcic_write(sc, PCIC_INTR, intr); 
2331 
2332 /* zero out the address windows */ 
2333 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 
2334 
2335 /* power down the socket to reset it, clear the card reset pin */ 
2336 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 
2337 
2338 /* power off; assert output enable bit */ 
2339 power = PCIC_PWRCTL_OE; 
2340 Pcic_write(sc, PCIC_PWRCTL, power); 
2341 
2342 /* power up the socket */ 
2343 if (pccbb_power(sc, voltage) == 0) 
2344 return; 
2345 
2346 /* 
2347 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 
2348 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 
2349 * RESET Width (Th (Hi-z RESET)) = 1ms 
2350 * RESET Width (Tw (RESET)) = 10us 
2351 *  
2352 * some machines require some more time to be settled 
2353 * for example old toshiba topic bridges! 
2354 * (100ms is added here). 
2355 */  
2356 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 
2357 
2358 /* negate RESET */ 
2359 intr |= PCIC_INTR_RESET; 
2360 Pcic_write(sc, PCIC_INTR, intr); 
2361 
2362 /* 
2363 * RESET Setup Time (Tsu (RESET)) = 20ms 
2364 */ 
2365 pccbb_pcmcia_delay(sc, 20, "pccen2"); 
2366 
2367#ifdef DIAGNOSTIC 
2368 reg = Pcic_read(sc, PCIC_IF_STATUS); 
2369 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 
2370 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 
2371#endif 
2372 
2373 /* wait for the chip to finish initializing */ 
2374 if (pccbb_pcmcia_wait_ready(sc)) { 
2375#ifdef DIAGNOSTIC 
2376 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 
2377#endif 
2378 /* XXX return a failure status?? */ 
2379 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 
2380 Pcic_write(sc, PCIC_PWRCTL, 0); 
2381 return; 
2382 } 
2383 
2384 /* reinstall all the memory and io mappings */ 
2385 for (win = 0; win < PCIC_MEM_WINS; ++win) 
2386 if (ph->memalloc & (1 << win)) 
2387 pccbb_pcmcia_do_mem_map(sc, win); 
2388 for (win = 0; win < PCIC_IO_WINS; ++win) 
2389 if (ph->ioalloc & (1 << win)) 
2390 pccbb_pcmcia_do_io_map(sc, win); 
2391} 
2392 
2393/* 
2394 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 
2395 * 
2396 * This function disables the card. All information is stored in 
2397 * the first argument, pcmcia_chipset_handle_t. 
2398 */ 
2399STATIC void 
2400pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 
2401{ 
2402 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2403 u_int8_t intr; 
2404 
2405 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 
2406 
2407 /* disable interrupts; assert RESET */ 
2408 intr = Pcic_read(sc, PCIC_INTR); 
2409 intr &= PCIC_INTR_ENABLE; 
2410 Pcic_write(sc, PCIC_INTR, intr); 
2411 
2412 /* zero out the address windows */ 
2413 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 
2414 
2415 /* power down the socket to reset it, clear the card reset pin */ 
2416 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 
2417 
2418 /* disable socket: negate output enable bit and power off */ 
2419 Pcic_write(sc, PCIC_PWRCTL, 0); 
2420 
2421 /* 
2422 * Vcc Falling Time (Tpf) = 300ms 
2423 */ 
2424 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 
2425} 
2426 
2427STATIC void 
2428pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 
2429{ 
2430 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2431 u_int8_t intr; 
2432 
2433 /* set the card type */ 
2434 
2435 intr = Pcic_read(sc, PCIC_INTR); 
2436 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 
2437 if (type == PCMCIA_IFTYPE_IO) 
2438 intr |= PCIC_INTR_CARDTYPE_IO; 
2439 else 
2440 intr |= PCIC_INTR_CARDTYPE_MEM; 
2441 Pcic_write(sc, PCIC_INTR, intr); 
2442 
2443 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 
2444 device_xname(sc->sc_dev), 
2445 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 
2446} 
2447 
2448/* 
2449 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 
2450 * 
2451 * This function detects whether a card is in the slot or not. 
2452 * If a card is inserted, return 1. Otherwise, return 0. 
2453 */ 
2454STATIC int 
2455pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 
2456{ 
2457 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2458 
2459 DPRINTF(("pccbb_pcmcia_card_detect\n")); 
2460 return pccbb_detect_card(sc) == 1 ? 1 : 0; 
2461} 
2462 
2463#if 0 
2464STATIC int 
2465pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 
2466 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 
2467 bus_space_tag_t * memtp bus_space_handle_t * memhp) 
2468#endif 
2469/* 
2470 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 
2471 * bus_size_t size, 
2472 * struct pcmcia_mem_handle *pcmhp) 
2473 * 
2474 * This function only allocates memory region for pccard. This 
2475 * function never maps the allocated region to pccard memory area. 
2476 * 
2477 * XXX: Why the argument of start address is not in? 
2478 */ 
2479STATIC int 
2480pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 
2481 struct pcmcia_mem_handle *pcmhp) 
2482{ 
2483 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2484 bus_space_handle_t memh; 
2485 bus_addr_t addr; 
2486 bus_size_t sizepg; 
2487#if rbus 
2488 rbus_tag_t rb; 
2489#endif 
2490 
2491 /* Check that the card is still there. */ 
2492 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 
2493 PCIC_IF_STATUS_CARDDETECT_PRESENT) 
2494 return 1; 
2495 
2496 /* out of sc->memh, allocate as many pages as necessary */ 
2497 
2498 /* convert size to PCIC pages */ 
2499 /* 
2500 * This is not enough; when the requested region is on the page 
2501 * boundaries, this may calculate wrong result. 
2502 */ 
2503 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 
2504#if 0 
2505 if (sizepg > PCIC_MAX_MEM_PAGES) { 
2506 return 1; 
2507 } 
2508#endif 
2509 
2510 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 
2511 return 1; 
2512 } 
2513 
2514 addr = 0; /* XXX gcc -Wuninitialized */ 
2515 
2516#if rbus 
2517 rb = sc->sc_rbus_memt; 
2518 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 
2519 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 
2520 &addr, &memh)) { 
2521 return 1; 
2522 } 
2523#else 
2524 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 
2525 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 
2526 0, /* boundary */ 
2527 0, /* flags */ 
2528 &addr, &memh)) { 
2529 return 1; 
2530 } 
2531#endif 
2532 
2533 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 
2534 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 
2535 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 
2536 
2537 pcmhp->memt = sc->sc_memt; 
2538 pcmhp->memh = memh; 
2539 pcmhp->addr = addr; 
2540 pcmhp->size = size; 
2541 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 
2542 /* What is mhandle? I feel it is very dirty and it must go trush. */ 
2543 pcmhp->mhandle = 0; 
2544 /* No offset??? Funny. */ 
2545 
2546 return 0; 
2547} 
2548 
2549/* 
2550 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 
2551 * struct pcmcia_mem_handle *pcmhp) 
2552 * 
2553 * This function release the memory space allocated by the function 
2554 * pccbb_pcmcia_mem_alloc(). 
2555 */ 
2556STATIC void 
2557pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 
2558 struct pcmcia_mem_handle *pcmhp) 
2559{ 
2560#if rbus 
2561 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2562 
2563 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 
2564#else 
2565 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 
2566#endif 
2567} 
2568 
2569/* 
2570 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 
2571 * 
2572 * This function release the memory space allocated by the function 
2573 * pccbb_pcmcia_mem_alloc(). 
2574 */ 
2575STATIC void 
2576pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 
2577{ 
2578 int regbase_win; 
2579 bus_addr_t phys_addr; 
2580 bus_addr_t phys_end; 
2581 struct pcic_handle *ph = &sc->sc_pcmcia_h; 
2582 
2583#define PCIC_SMM_START_LOW 0 
2584#define PCIC_SMM_START_HIGH 1 
2585#define PCIC_SMM_STOP_LOW 2 
2586#define PCIC_SMM_STOP_HIGH 3 
2587#define PCIC_CMA_LOW 4 
2588#define PCIC_CMA_HIGH 5 
2589 
2590 u_int8_t start_low, start_high = 0; 
2591 u_int8_t stop_low, stop_high; 
2592 u_int8_t off_low, off_high; 
2593 u_int8_t mem_window; 
2594 int reg; 
2595 
2596 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 
2597 int mem8 = 
2598 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 
2599 || (kind == PCMCIA_MEM_ATTR); 
2600 
2601 regbase_win = 0x10 + win * 0x08; 
2602 
2603 phys_addr = ph->mem[win].addr; 
2604 phys_end = phys_addr + ph->mem[win].size; 
2605 
2606 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 
2607 (unsigned long)phys_addr, (unsigned long)phys_end, 
2608 (unsigned long)ph->mem[win].offset)); 
2609 
2610#define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 
2611#define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 
2612#define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 
2613 
2614 /* bit 19:12 */ 
2615 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 
2616 /* bit 23:20 and bit 7 on */ 
2617 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 
2618 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 
2619 /* bit 31:24, for 32-bit address */ 
2620 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 
2621 
2622 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 
2623 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 
2624 
2625 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 
2626 Pcic_write(sc, 0x40 + win, mem_window); 
2627 } 
2628 
2629 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 
2630 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 
2631 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 
2632 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 
2633 
2634 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 
2635 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 
2636 
2637 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 
2638 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 
2639 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 
2640 | ((kind == PCMCIA_MEM_ATTR) ? 
2641 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 
2642 
2643 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 
2644 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 
2645 
2646 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 
2647 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 
2648 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 
2649 
2650#if defined(CBB_DEBUG) 
2651 { 
2652 int r1, r2, r3, r4, r5, r6, r7 = 0; 
2653 
2654 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 
2655 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 
2656 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 
2657 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 
2658 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 
2659 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 
2660 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 
2661 r7 = Pcic_read(sc, 0x40 + win); 
2662 } 
2663 
2664 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 
2665 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 
2666 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 
2667 printf(" %02x", r7); 
2668 } 
2669 printf("\n"); 
2670 } 
2671#endif 
2672} 
2673 
2674/* 
2675 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 
2676 * bus_addr_t card_addr, bus_size_t size, 
2677 * struct pcmcia_mem_handle *pcmhp, 
2678 * bus_addr_t *offsetp, int *windowp) 
2679 * 
2680 * This function maps memory space allocated by the function 
2681 * pccbb_pcmcia_mem_alloc(). 
2682 */ 
2683STATIC int 
2684pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 
2685 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 
2686 bus_addr_t *offsetp, int *windowp) 
2687{ 
2688 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2689 struct pcic_handle *ph = &sc->sc_pcmcia_h; 
2690 bus_addr_t busaddr; 
2691 long card_offset; 
2692 int win; 
2693 
2694 /* Check that the card is still there. */ 
2695 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 
2696 PCIC_IF_STATUS_CARDDETECT_PRESENT) 
2697 return 1; 
2698 
2699 for (win = 0; win < PCIC_MEM_WINS; ++win) { 
2700 if ((ph->memalloc & (1 << win)) == 0) { 
2701 ph->memalloc |= (1 << win); 
2702 break; 
2703 } 
2704 } 
2705 
2706 if (win == PCIC_MEM_WINS) { 
2707 return 1; 
2708 } 
2709 
2710 *windowp = win; 
2711 
2712 /* XXX this is pretty gross */ 
2713 
2714 if (sc->sc_memt != pcmhp->memt) { 
2715 panic("pccbb_pcmcia_mem_map memt is bogus"); 
2716 } 
2717 
2718 busaddr = pcmhp->addr; 
2719 
2720 /* 
2721 * compute the address offset to the pcmcia address space for the 
2722 * pcic. this is intentionally signed. The masks and shifts below 
2723 * will cause TRT to happen in the pcic registers. Deal with making 
2724 * sure the address is aligned, and return the alignment offset. 
2725 */ 
2726 
2727 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 
2728 card_addr -= *offsetp; 
2729 
2730 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 
2731 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 
2732 (u_long) card_addr)); 
2733 
2734 /* 
2735 * include the offset in the size, and decrement size by one, since 
2736 * the hw wants start/stop 
2737 */ 
2738 size += *offsetp - 1; 
2739 
2740 card_offset = (((long)card_addr) - ((long)busaddr)); 
2741 
2742 ph->mem[win].addr = busaddr; 
2743 ph->mem[win].size = size; 
2744 ph->mem[win].offset = card_offset; 
2745 ph->mem[win].kind = kind; 
2746 
2747 pccbb_pcmcia_do_mem_map(sc, win); 
2748 
2749 return 0; 
2750} 
2751 
2752/* 
2753 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 
2754 * int window) 
2755 * 
2756 * This function unmaps memory space which mapped by the function 
2757 * pccbb_pcmcia_mem_map(). 
2758 */ 
2759STATIC void 
2760pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 
2761{ 
2762 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2763 struct pcic_handle *ph = &sc->sc_pcmcia_h; 
2764 int reg; 
2765 
2766 if (window >= PCIC_MEM_WINS) { 
2767 panic("pccbb_pcmcia_mem_unmap: window out of range"); 
2768 } 
2769 
2770 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 
2771 reg &= ~(1 << window); 
2772 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 
2773 
2774 ph->memalloc &= ~(1 << window); 
2775} 
2776 
2777/* 
2778 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 
2779 * struct pcmcia_function *pf, 
2780 * int ipl, 
2781 * int (*func)(void *), 
2782 * void *arg); 
2783 * 
2784 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 
2785 */ 
2786STATIC void * 
2787pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 
2788 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 
2789{ 
2790 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2791 
2792 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 
2793 /* what should I do? */ 
2794 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 
2795 DPRINTF(("%s does not provide edge nor pulse " 
2796 "interrupt\n", device_xname(sc->sc_dev))); 
2797 return NULL; 
2798 } 
2799 /* 
2800 * XXX Noooooo! The interrupt flag must set properly!! 
2801 * dumb pcmcia driver!! 
2802 */ 
2803 } 
2804 
2805 return pccbb_intr_establish(sc, 0, ipl, func, arg); 
2806} 
2807 
2808/* 
2809 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 
2810 * void *ih) 
2811 * 
2812 * This function disables PC-Card interrupt. 
2813 */ 
2814STATIC void 
2815pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 
2816{ 
2817 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 
2818 
2819 pccbb_intr_disestablish(sc, ih); 
2820} 
2821 
2822#if rbus 
2823/* 
2824 * static int 
2825 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 
2826 * bus_addr_t addr, bus_size_t size, 
2827 * bus_addr_t mask, bus_size_t align, 
2828 * int flags, bus_addr_t *addrp; 
2829 * bus_space_handle_t *bshp) 
2830 * 
2831 * This function allocates a portion of memory or io space for 
2832 * clients. This function is called from CardBus card drivers. 
2833 */ 
2834static int 
2835pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 
2836 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 
2837 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 
2838{ 
2839 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 
2840 
2841 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 
2842 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 
2843 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 
2844 
2845 if (align == 0) { 
2846 align = size; 
2847 } 
2848 
2849 if (rb->rb_bt == sc->sc_memt) { 
2850 if (align < 16) { 
2851 return 1; 
2852 } 
2853 /* 
2854 * XXX: align more than 0x1000 to avoid overwrapping 
2855 * memory windows for two or more devices. 0x1000 
2856 * means memory window's granularity. 
2857 * 
2858 * Two or more devices should be able to share same 
2859 * memory window region. However, overrapping memory 
2860 * window is not good because some devices, such as 
2861 * 3Com 3C575[BC], have a broken address decoder and 
2862 * intrude other's memory region. 
2863 */ 
2864 if (align < 0x1000) { 
2865 align = 0x1000; 
2866 } 
2867 } else if (rb->rb_bt == sc->sc_iot) { 
2868 if (align < 4) { 
2869 return 1; 
2870 } 
2871 /* XXX: hack for avoiding ISA image */ 
2872 if (mask < 0x0100) { 
2873 mask = 0x3ff; 
2874 addr = 0x300; 
2875 } 
2876 
2877 } else { 
2878 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 
2879 "NOT used. io: 0x%lx, mem: 0x%lx\n", 
2880 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 
2881 (unsigned long)sc->sc_memt)); 
2882 return 1; 
2883 /* XXX: panic here? */ 
2884 } 
2885 
2886 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 
2887 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 
2888 return 1; 
2889 } 
2890 
2891 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 
2892 
2893 return 0; 
2894} 
2895 
2896/* 
2897 * static int 
2898 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 
2899 * bus_space_handle_t *bshp, bus_size_t size); 
2900 * 
2901 * This function is called from CardBus card drivers. 
2902 */ 
2903static int 
2904pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 
2905 bus_space_handle_t bsh, bus_size_t size) 
2906{ 
2907 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 
2908 bus_space_tag_t bt = rb->rb_bt; 
2909 
2910 pccbb_close_win(sc, bt, bsh, size); 
2911 
2912 if (bt == sc->sc_memt) { 
2913 } else if (bt == sc->sc_iot) { 
2914 } else { 
2915 return 1; 
2916 /* XXX: panic here? */ 
2917 } 
2918 
2919 return rbus_space_free(rb, bsh, size, NULL); 
2920} 
2921#endif /* rbus */ 
2922 
2923#if rbus 
2924 
2925static int 
2926pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 
2927 bus_size_t size, bus_space_handle_t bsh, int flags) 
2928{ 
2929 struct pccbb_win_chain_head *head; 
2930 bus_addr_t align; 
2931 
2932 head = &sc->sc_iowindow; 
2933 align = 0x04; 
2934 if (sc->sc_memt == bst) { 
2935 head = &sc->sc_memwindow; 
2936 align = 0x1000; 
2937 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 
2938 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 
2939 (unsigned long)bst)); 
2940 } 
2941 
2942 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 
2943 aprint_error_dev(sc->sc_dev, 
2944 "pccbb_open_win: %s winlist insert failed\n", 
2945 (head == &sc->sc_memwindow) ? "mem" : "io"); 
2946 } 
2947 pccbb_winset(align, sc, bst); 
2948 
2949 return 0; 
2950} 
2951 
2952static int 
2953pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 
2954 bus_space_handle_t bsh, bus_size_t size) 
2955{ 
2956 struct pccbb_win_chain_head *head; 
2957 bus_addr_t align; 
2958 
2959 head = &sc->sc_iowindow; 
2960 align = 0x04; 
2961 if (sc->sc_memt == bst) { 
2962 head = &sc->sc_memwindow; 
2963 align = 0x1000; 
2964 } 
2965 
2966 if (pccbb_winlist_delete(head, bsh, size)) { 
2967 aprint_error_dev(sc->sc_dev, 
2968 "pccbb_close_win: %s winlist delete failed\n", 
2969 (head == &sc->sc_memwindow) ? "mem" : "io"); 
2970 } 
2971 pccbb_winset(align, sc, bst); 
2972 
2973 return 0; 
2974} 
2975 
2976static int 
2977pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 
2978 bus_size_t size, bus_space_handle_t bsh, int flags) 
2979{ 
2980 struct pccbb_win_chain *chainp, *elem; 
2981 
2982 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 
2983 M_NOWAIT)) == NULL) 
2984 return (1); /* fail */ 
2985 
2986 elem->wc_start = start; 
2987 elem->wc_end = start + (size - 1); 
2988 elem->wc_handle = bsh; 
2989 elem->wc_flags = flags; 
2990 
2991 TAILQ_FOREACH(chainp, head, wc_list) { 
2992 if (chainp->wc_end >= start) 
2993 break; 
2994 } 
2995 if (chainp != NULL) 
2996 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 
2997 else 
2998 TAILQ_INSERT_TAIL(head, elem, wc_list); 
2999 return (0); 
3000} 
3001 
3002static int 
3003pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 
3004 bus_size_t size) 
3005{ 
3006 struct pccbb_win_chain *chainp; 
3007 
3008 TAILQ_FOREACH(chainp, head, wc_list) { 
3009 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 
3010 break; 
3011 } 
3012 if (chainp == NULL) 
3013 return 1; /* fail: no candidate to remove */ 
3014 
3015 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 
3016 printf("pccbb_winlist_delete: window 0x%lx size " 
3017 "inconsistent: 0x%lx, 0x%lx\n", 
3018 (unsigned long)chainp->wc_start, 
3019 (unsigned long)(chainp->wc_end - chainp->wc_start), 
3020 (unsigned long)(size - 1)); 
3021 return 1; 
3022 } 
3023 
3024 TAILQ_REMOVE(head, chainp, wc_list); 
3025 free(chainp, M_DEVBUF); 
3026 
3027 return 0; 
3028} 
3029 
3030static void 
3031pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 
3032{ 
3033 pci_chipset_tag_t pc; 
3034 pcitag_t tag; 
3035 bus_addr_t mask = ~(align - 1); 
3036 struct { 
3037 cardbusreg_t win_start; 
3038 cardbusreg_t win_limit; 
3039 int win_flags; 
3040 } win[2]; 
3041 struct pccbb_win_chain *chainp; 
3042 int offs; 
3043 
3044 win[0].win_start = win[1].win_start = 0xffffffff; 
3045 win[0].win_limit = win[1].win_limit = 0; 
3046 win[0].win_flags = win[1].win_flags = 0; 
3047 
3048 chainp = TAILQ_FIRST(&sc->sc_iowindow); 
3049 offs = PCI_CB_IOBASE0; 
3050 if (sc->sc_memt == bst) { 
3051 chainp = TAILQ_FIRST(&sc->sc_memwindow); 
3052 offs = PCI_CB_MEMBASE0; 
3053 } 
3054 
3055 if (chainp != NULL) { 
3056 win[0].win_start = chainp->wc_start & mask; 
3057 win[0].win_limit = chainp->wc_end & mask; 
3058 win[0].win_flags = chainp->wc_flags; 
3059 chainp = TAILQ_NEXT(chainp, wc_list); 
3060 } 
3061 
3062 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 
3063 if (win[1].win_start == 0xffffffff) { 
3064 /* window 1 is not used */ 
3065 if ((win[0].win_flags == chainp->wc_flags) && 
3066 (win[0].win_limit + align >= 
3067 (chainp->wc_start & mask))) { 
3068 /* concatenate */ 
3069 win[0].win_limit = chainp->wc_end & mask; 
3070 } else { 
3071 /* make new window */ 
3072 win[1].win_start = chainp->wc_start & mask; 
3073 win[1].win_limit = chainp->wc_end & mask; 
3074 win[1].win_flags = chainp->wc_flags; 
3075 } 
3076 continue; 
3077 } 
3078 
3079 /* Both windows are engaged. */ 
3080 if (win[0].win_flags == win[1].win_flags) { 
3081 /* same flags */ 
3082 if (win[0].win_flags == chainp->wc_flags) { 
3083 if (win[1].win_start - (win[0].win_limit + 
3084 align) < 
3085 (chainp->wc_start & mask) - 
3086 ((chainp->wc_end & mask) + align)) { 
3087 /* 
3088 * merge window 0 and 1, and set win1 
3089 * to chainp 
3090 */ 
3091 win[0].win_limit = win[1].win_limit; 
3092 win[1].win_start = 
3093 chainp->wc_start & mask; 
3094 win[1].win_limit = 
3095 chainp->wc_end & mask; 
3096 } else { 
3097 win[1].win_limit = 
3098 chainp->wc_end & mask; 
3099 } 
3100 } else { 
3101 /* different flags */ 
3102 
3103 /* concatenate win0 and win1 */ 
3104 win[0].win_limit = win[1].win_limit; 
3105 /* allocate win[1] to new space */ 
3106 win[1].win_start = chainp->wc_start & mask; 
3107 win[1].win_limit = chainp->wc_end & mask; 
3108 win[1].win_flags = chainp->wc_flags; 
3109 } 
3110 } else { 
3111 /* the flags of win[0] and win[1] is different */ 
3112 if (win[0].win_flags == chainp->wc_flags) { 
3113 win[0].win_limit = chainp->wc_end & mask; 
3114 /* 
3115 * XXX this creates overlapping windows, so 
3116 * what should the poor bridge do if one is 
3117 * cachable, and the other is not? 
3118 */ 
3119 aprint_error_dev(sc->sc_dev, 
3120 "overlapping windows\n"); 
3121 } else { 
3122 win[1].win_limit = chainp->wc_end & mask; 
3123 } 
3124 } 
3125 } 
3126 
3127 pc = sc->sc_pc; 
3128 tag = sc->sc_tag; 
3129 pci_conf_write(pc, tag, offs, win[0].win_start); 
3130 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 
3131 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 
3132 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 
3133 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 
3134 (unsigned long)pci_conf_read(pc, tag, offs), 
3135 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 
3136 (unsigned long)pci_conf_read(pc, tag, offs + 8), 
3137 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 
3138 
3139 if (bst == sc->sc_memt) { 
3140 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 
3141 
3142 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 
3143 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 
3144 bcr |= CB_BCR_PREFETCH_MEMWIN0; 
3145 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 
3146 bcr |= CB_BCR_PREFETCH_MEMWIN1; 
3147 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 
3148 } 
3149} 
3150 
3151#endif /* rbus */ 
3152 
3153static bool 
3154pccbb_suspend(device_t dv PMF_FN_ARGS) 
3155{ 
3156 struct pccbb_softc *sc = device_private(dv); 
3157 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 
3158 bus_space_handle_t base_memh = sc->sc_base_memh; 
3159 pcireg_t reg; 
3160 
3161 if (sc->sc_pil_intr_enable) 
3162 (void)pccbbintr_function(sc); 
3163 sc->sc_pil_intr_enable = 0; 
3164 
3165 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 
3166 /* Disable interrupts. */ 
3167 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 
3168 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 
3169 /* XXX joerg Disable power to the socket? */ 
3170 
3171 /* XXX flush PCI write */ 
3172 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 
3173 
3174 /* reset interrupt */ 
3175 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 
3176 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 
3177 /* XXX flush PCI write */ 
3178 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 
3179 
3180 if (sc->sc_ih != NULL) { 
3181 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 
3182 sc->sc_ih = NULL; 
3183 } 
3184 
3185 return true; 
3186} 
3187 
3188static bool 
3189pccbb_resume(device_t dv PMF_FN_ARGS) 
3190{ 
3191 struct pccbb_softc *sc = device_private(dv); 
3192 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 
3193 bus_space_handle_t base_memh = sc->sc_base_memh; 
3194 pcireg_t reg; 
3195 
3196 pccbb_chipinit(sc); 
3197 pccbb_intrinit(sc); 
3198 /* setup memory and io space window for CB */ 
3199 pccbb_winset(0x1000, sc, sc->sc_memt); 
3200 pccbb_winset(0x04, sc, sc->sc_iot); 
3201 
3202 /* CSC Interrupt: Card detect interrupt on */ 
3203 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 
3204 /* Card detect intr is turned on. */ 
3205 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 
3206 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 
3207 /* reset interrupt */ 
3208 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 
3209 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 
3210 
3211 /* 
3212 * check for card insertion or removal during suspend period. 
3213 * XXX: the code can't cope with card swap (remove then 
3214 * insert). how can we detect such situation? 
3215 */ 
3216 (void)pccbbintr(sc); 
3217 
3218 sc->sc_pil_intr_enable = 1; 
3219 
3220 return true; 
3221}