Wed Feb 4 00:05:09 2009 UTC ()
Sprinkle _NOPROFILE so that profiling kernels boot.


(skrll)
diff -r1.26.2.5 -r1.26.2.6 src/sys/arch/hppa/hppa/trap.S
cvs diff -r1.26.2.5 -r1.26.2.6 src/sys/arch/hppa/hppa/trap.S (expand / switch to unified diff)

--- src/sys/arch/hppa/hppa/trap.S 2008/12/15 18:13:14 1.26.2.5
+++ src/sys/arch/hppa/hppa/trap.S 2009/02/04 00:05:09 1.26.2.6
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: trap.S,v 1.26.2.5 2008/12/15 18:13:14 skrll Exp $ */ 1/* $NetBSD: trap.S,v 1.26.2.6 2009/02/04 00:05:09 skrll Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 4 * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matthew Fredette. 8 * by Matthew Fredette.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -1310,27 +1310,27 @@ itlb_c: @@ -1310,27 +1310,27 @@ itlb_c:
1310/* 1310/*
1311 * This is a handler for interruption 20, "TLB dirty bit trap". It 1311 * This is a handler for interruption 20, "TLB dirty bit trap". It
1312 * is used on the PA7000 (PCX), PA7000 (PCX-S), and PA7100 (PCX-T). XXXNH 1312 * is used on the PA7000 (PCX), PA7000 (PCX-S), and PA7100 (PCX-T). XXXNH
1313 * Only shadowed registers are available, and they are: 1313 * Only shadowed registers are available, and they are:
1314 * 1314 *
1315 * %r1 = C trap number 1315 * %r1 = C trap number
1316 * %r8 = data address space identifier 1316 * %r8 = data address space identifier
1317 * %r9 = data address offset 1317 * %r9 = data address offset
1318 * %r16 = undefined 1318 * %r16 = undefined
1319 * %r17 = undefined 1319 * %r17 = undefined
1320 * %r24 = undefined 1320 * %r24 = undefined
1321 * %r25 = undefined 1321 * %r25 = undefined
1322 */ 1322 */
1323LEAF_ENTRY($tlbd_s) 1323LEAF_ENTRY_NOPROFILE($tlbd_s)
1324ALTENTRY($tlbd_t) 1324ALTENTRY($tlbd_t)
1325ALTENTRY($tlbd_x) 1325ALTENTRY($tlbd_x)
1326 TLB_STATS_PRE(tlbd) 1326 TLB_STATS_PRE(tlbd)
1327 TLB_PULL(1, TLABEL(all)) 1327 TLB_PULL(1, TLABEL(all))
1328 mfsp %sr1, %r16 1328 mfsp %sr1, %r16
1329 mtsp %r8, %sr1 1329 mtsp %r8, %sr1
1330 idtlba %r17,(%sr1, %r9) 1330 idtlba %r17,(%sr1, %r9)
1331 idtlbp %r25,(%sr1, %r9) 1331 idtlbp %r25,(%sr1, %r9)
1332 mtsp %r16, %sr1 1332 mtsp %r16, %sr1
1333 TLB_STATS_AFT(tlbd) 1333 TLB_STATS_AFT(tlbd)
1334 rfir 1334 rfir
1335 nop 1335 nop
1336EXIT($tlbd_s) 1336EXIT($tlbd_s)
@@ -1340,27 +1340,27 @@ EXIT($tlbd_s) @@ -1340,27 +1340,27 @@ EXIT($tlbd_s)
1340 * and interruption 16, "Non-access instruction TLB miss fault". It 1340 * and interruption 16, "Non-access instruction TLB miss fault". It
1341 * is used on the PA7000 (PCX), PA7000 (PCX-S), PA7100 (PCX-T) and 1341 * is used on the PA7000 (PCX), PA7000 (PCX-S), PA7100 (PCX-T) and
1342 * PA7200 (PCX-T') 1342 * PA7200 (PCX-T')
1343 * Only shadowed registers are available, and they are: 1343 * Only shadowed registers are available, and they are:
1344 * 1344 *
1345 * %r1 = C trap number 1345 * %r1 = C trap number
1346 * %r8 = instruction address space identifier 1346 * %r8 = instruction address space identifier
1347 * %r9 = instruction address offset 1347 * %r9 = instruction address offset
1348 * %r16 = undefined 1348 * %r16 = undefined
1349 * %r17 = undefined 1349 * %r17 = undefined
1350 * %r24 = undefined 1350 * %r24 = undefined
1351 * %r25 = undefined 1351 * %r25 = undefined
1352 */ 1352 */
1353LEAF_ENTRY($itlb_s) 1353LEAF_ENTRY_NOPROFILE($itlb_s)
1354ALTENTRY($itlb_t) 1354ALTENTRY($itlb_t)
1355ALTENTRY($itlb_x) 1355ALTENTRY($itlb_x)
1356 TLB_STATS_PRE(itlb) 1356 TLB_STATS_PRE(itlb)
1357 TLB_PULL(0, TLABEL(all)) 1357 TLB_PULL(0, TLABEL(all))
1358 extru,= %r25, 5, 1, %r0 /* gate needs a kernel pid */ 1358 extru,= %r25, 5, 1, %r0 /* gate needs a kernel pid */
1359 depi 0, 30, 15, %r25 1359 depi 0, 30, 15, %r25
1360 mfsp %sr1, %r16 1360 mfsp %sr1, %r16
1361 mtsp %r8, %sr1 1361 mtsp %r8, %sr1
1362 iitlba %r17,(%sr1, %r9) 1362 iitlba %r17,(%sr1, %r9)
1363 iitlbp %r25,(%sr1, %r9) 1363 iitlbp %r25,(%sr1, %r9)
1364 mtsp %r16, %sr1 1364 mtsp %r16, %sr1
1365 TLB_STATS_AFT(itlb) 1365 TLB_STATS_AFT(itlb)
1366 rfir 1366 rfir
@@ -1372,42 +1372,42 @@ EXIT($itlb_s) @@ -1372,42 +1372,42 @@ EXIT($itlb_s)
1372 * and interruption 17, "Non-access data TLB miss fault". It is 1372 * and interruption 17, "Non-access data TLB miss fault". It is
1373 * used on the PA7000 (PCX), PA7000 (PCX-S), PA7100 (PCX-T) and 1373 * used on the PA7000 (PCX), PA7000 (PCX-S), PA7100 (PCX-T) and
1374 * PA7200 (PCX-T') 1374 * PA7200 (PCX-T')
1375 * Only shadowed registers are available, and they are: 1375 * Only shadowed registers are available, and they are:
1376 * 1376 *
1377 * %r1 = C trap number 1377 * %r1 = C trap number
1378 * %r8 = data address space identifier 1378 * %r8 = data address space identifier
1379 * %r9 = data address offset 1379 * %r9 = data address offset
1380 * %r16 = undefined 1380 * %r16 = undefined
1381 * %r17 = undefined 1381 * %r17 = undefined
1382 * %r24 = undefined 1382 * %r24 = undefined
1383 * %r25 = undefined 1383 * %r25 = undefined
1384 */ 1384 */
1385LEAF_ENTRY($dtlb_s) 1385LEAF_ENTRY_NOPROFILE($dtlb_s)
1386ALTENTRY($dtlb_t) 1386ALTENTRY($dtlb_t)
1387ALTENTRY($dtlb_x) 1387ALTENTRY($dtlb_x)
1388 TLB_STATS_PRE(dtlb) 1388 TLB_STATS_PRE(dtlb)
1389 TLB_PULL(0, TLABEL(all)) 1389 TLB_PULL(0, TLABEL(all))
1390 mfsp %sr1, %r16 1390 mfsp %sr1, %r16
1391 mtsp %r8, %sr1 1391 mtsp %r8, %sr1
1392 idtlba %r17,(%sr1, %r9) 1392 idtlba %r17,(%sr1, %r9)
1393 idtlbp %r25,(%sr1, %r9) 1393 idtlbp %r25,(%sr1, %r9)
1394 mtsp %r16, %sr1 1394 mtsp %r16, %sr1
1395 TLB_STATS_AFT(dtlb) 1395 TLB_STATS_AFT(dtlb)
1396 rfir 1396 rfir
1397 nop 1397 nop
1398EXIT($dtlb_s) 1398EXIT($dtlb_s)
1399 1399
1400LEAF_ENTRY($dtlbna_s) 1400LEAF_ENTRY_NOPROFILE($dtlbna_s)
1401ALTENTRY($itlbna_s) 1401ALTENTRY($itlbna_s)
1402ALTENTRY($dtlbna_t) 1402ALTENTRY($dtlbna_t)
1403ALTENTRY($itlbna_t) 1403ALTENTRY($itlbna_t)
1404ALTENTRY($dtlbna_x) 1404ALTENTRY($dtlbna_x)
1405ALTENTRY($itlbna_x) 1405ALTENTRY($itlbna_x)
1406 TLB_STATS_PRE(dtlb) 1406 TLB_STATS_PRE(dtlb)
1407 TLB_PULL(0, $dtlbna_t_fake) 1407 TLB_PULL(0, $dtlbna_t_fake)
1408 mfsp %sr1, %r16 1408 mfsp %sr1, %r16
1409 mtsp %r8, %sr1 1409 mtsp %r8, %sr1
1410 idtlba %r17,(%sr1, %r9) 1410 idtlba %r17,(%sr1, %r9)
1411 idtlbp %r25,(%sr1, %r9) 1411 idtlbp %r25,(%sr1, %r9)
1412 mtsp %r16, %sr1 1412 mtsp %r16, %sr1
1413 TLB_STATS_AFT(dtlb) 1413 TLB_STATS_AFT(dtlb)
@@ -1495,27 +1495,27 @@ EXIT($dtlbna_s) @@ -1495,27 +1495,27 @@ EXIT($dtlbna_s)
1495 * is used on the PA7100LC (PCX-L), PA7300LC (PCX-L2). Only shadowed 1495 * is used on the PA7100LC (PCX-L), PA7300LC (PCX-L2). Only shadowed
1496 * registers are available, and they are: 1496 * registers are available, and they are:
1497 * 1497 *
1498 * %r1 = C trap number 1498 * %r1 = C trap number
1499 * %r8 = data address space identifier 1499 * %r8 = data address space identifier
1500 * %r9 = data address offset 1500 * %r9 = data address offset
1501 * %r16 = undefined 1501 * %r16 = undefined
1502 * %r17 = undefined 1502 * %r17 = undefined
1503 * %r24 = undefined 1503 * %r24 = undefined
1504 * %r25 = undefined 1504 * %r25 = undefined
1505 */ 1505 */
1506 1506
1507 .align 32 1507 .align 32
1508LEAF_ENTRY($tlbd_l) 1508LEAF_ENTRY_NOPROFILE($tlbd_l)
1509 TLB_STATS_PRE(tlbd) 1509 TLB_STATS_PRE(tlbd)
1510 TLB_PULL_L(1, TLABEL(all)) 1510 TLB_PULL_L(1, TLABEL(all))
1511 IDTLBAF(17) 1511 IDTLBAF(17)
1512 IDTLBPF(25) 1512 IDTLBPF(25)
1513#ifdef USE_HPT 1513#ifdef USE_HPT
1514 /* invalidate instead of update */ 1514 /* invalidate instead of update */
1515 mfctl %cr28, %r17 1515 mfctl %cr28, %r17
1516 ldw 0(%r17), %r24 1516 ldw 0(%r17), %r24
1517 VTAG(%r8, %r9, %r16) 1517 VTAG(%r8, %r9, %r16)
1518 sub,<> %r16, %r24, %r0 1518 sub,<> %r16, %r24, %r0
1519 stw %r0, 0(%r17) 1519 stw %r0, 0(%r17)
1520#endif 1520#endif
1521 TLB_STATS_AFT(tlbd) 1521 TLB_STATS_AFT(tlbd)
@@ -1533,39 +1533,39 @@ EXIT($tlbd_l) @@ -1533,39 +1533,39 @@ EXIT($tlbd_l)
1533 * %r8 = instruction address space identifier 1533 * %r8 = instruction address space identifier
1534 * %r9 = instruction address offset 1534 * %r9 = instruction address offset
1535 * %r16 = undefined 1535 * %r16 = undefined
1536 * %r17 = undefined 1536 * %r17 = undefined
1537 * %r24 = undefined 1537 * %r24 = undefined
1538 * %r25 = undefined 1538 * %r25 = undefined
1539 */ 1539 */
1540 1540
1541/* 1541/*
1542 * from 7100lc ers, pg.6: 1542 * from 7100lc ers, pg.6:
1543 * we found a post-silicon bug that makes cr28 1543 * we found a post-silicon bug that makes cr28
1544 * unreliable for the itlb miss handler 1544 * unreliable for the itlb miss handler
1545 */ 1545 */
1546LEAF_ENTRY($itlb_l) 1546LEAF_ENTRY_NOPROFILE($itlb_l)
1547 TLB_STATS_PRE(itlb) 1547 TLB_STATS_PRE(itlb)
1548 TLB_PULL_L(0, TLABEL(all)) 1548 TLB_PULL_L(0, TLABEL(all))
1549 extru,= %r25, 5, 1, %r0 /* gate needs a kernel pid */ 1549 extru,= %r25, 5, 1, %r0 /* gate needs a kernel pid */
1550 depi 0, 30, 15, %r25 1550 depi 0, 30, 15, %r25
1551 IITLBAF(17) 1551 IITLBAF(17)
1552 IITLBPF(25) 1552 IITLBPF(25)
1553 TLB_STATS_AFT(itlb) 1553 TLB_STATS_AFT(itlb)
1554 rfir 1554 rfir
1555 nop 1555 nop
1556EXIT($itlb_l) 1556EXIT($itlb_l)
1557 1557
1558LEAF_ENTRY($dtlbna_l) 1558LEAF_ENTRY_NOPROFILE($dtlbna_l)
1559ALTENTRY($itlbna_l) 1559ALTENTRY($itlbna_l)
1560 TLB_STATS_PRE(dtlb) 1560 TLB_STATS_PRE(dtlb)
1561 TLB_PULL_L(0, $dtlbna_l_fake) 1561 TLB_PULL_L(0, $dtlbna_l_fake)
1562 IDTLBAF(17) 1562 IDTLBAF(17)
1563 IDTLBPF(25) 1563 IDTLBPF(25)
1564 TLB_STATS_AFT(dtlb) 1564 TLB_STATS_AFT(dtlb)
1565 rfir 1565 rfir
1566 nop 1566 nop
1567$dtlbna_l_fake: 1567$dtlbna_l_fake:
1568 /* parse prober/w insns, have to decent to trap() to set regs proper */ 1568 /* parse prober/w insns, have to decent to trap() to set regs proper */
1569 mfctl %iir, %r16 1569 mfctl %iir, %r16
1570 extru %r16, 6, 6, %r24 1570 extru %r16, 6, 6, %r24
1571 comib,=,n 1, %r24, TLABEL(all) 1571 comib,=,n 1, %r24, TLABEL(all)
@@ -1574,27 +1574,27 @@ $dtlbna_l_fake: @@ -1574,27 +1574,27 @@ $dtlbna_l_fake:
1574 b TLABEL(all) 1574 b TLABEL(all)
1575 /* otherwise generate a flush-only tlb entry */ 1575 /* otherwise generate a flush-only tlb entry */
1576 copy %r0, %r17 1576 copy %r0, %r17
1577 zdep %r8, 30, 15, %r25 1577 zdep %r8, 30, 15, %r25
1578 depi -13, 11, 7, %r25 1578 depi -13, 11, 7, %r25
1579 ldo 2(%r25), %r25 /* 3? */ 1579 ldo 2(%r25), %r25 /* 3? */
1580 IDTLBAF(17) 1580 IDTLBAF(17)
1581 IDTLBPF(25) 1581 IDTLBPF(25)
1582 TLB_STATS_AFT(dtlb) 1582 TLB_STATS_AFT(dtlb)
1583 rfir 1583 rfir
1584 nop 1584 nop
1585EXIT($dtlbna_l) 1585EXIT($dtlbna_l)
1586 1586
1587LEAF_ENTRY($dtlb_l) 1587LEAF_ENTRY_NOPROFILE($dtlb_l)
1588 TLB_STATS_PRE(dtlb) 1588 TLB_STATS_PRE(dtlb)
1589 TLB_PULL_L(0, TLABEL(all)) 1589 TLB_PULL_L(0, TLABEL(all))
1590 IDTLBAF(17) 1590 IDTLBAF(17)
1591 IDTLBPF(25) 1591 IDTLBPF(25)
1592#ifdef USE_HPT 1592#ifdef USE_HPT
1593 /* 1593 /*
1594 * cache the next page mapping in the hpt. 1594 * cache the next page mapping in the hpt.
1595 * 1595 *
1596 * mapping for a page at the end of each 128k is uncachable 1596 * mapping for a page at the end of each 128k is uncachable
1597 * in the hvt since it'd be in the tlb itself and thus there 1597 * in the hvt since it'd be in the tlb itself and thus there
1598 * is no reason to cache it! 1598 * is no reason to cache it!
1599 * as a side effect this avoids recomputing hpt entry and 1599 * as a side effect this avoids recomputing hpt entry and
1600 * retraversing the whole page table each time. 1600 * retraversing the whole page table each time.
@@ -1646,49 +1646,49 @@ EXIT($dtlb_l) @@ -1646,49 +1646,49 @@ EXIT($dtlb_l)
1646 /* fix io mappings */ ! \ 1646 /* fix io mappings */ ! \
1647 extrd,s %r17, 42, 4, %r1 ! \ 1647 extrd,s %r17, 42, 4, %r1 ! \
1648 addi,<> 1, %r1, %r0 ! \ 1648 addi,<> 1, %r1, %r0 ! \
1649 depdi -1, 38, 32, %r17 ! \ 1649 depdi -1, 38, 32, %r17 ! \
1650 /* fix prom mappings */ ! \ 1650 /* fix prom mappings */ ! \
1651 extrd,s %r17, 46, 8, %r1 ! \ 1651 extrd,s %r17, 46, 8, %r1 ! \
1652 addi,<> 0x10, %r1, %r0 ! \ 1652 addi,<> 0x10, %r1, %r0 ! \
1653 depdi 0, 38, 4, %r17 ! \ 1653 depdi 0, 38, 4, %r17 ! \
1654 /* weak ordering, dyn bp */ ! \ 1654 /* weak ordering, dyn bp */ ! \
1655 depwi 1, 31, 2, %r16 ! \ 1655 depwi 1, 31, 2, %r16 ! \
1656 depdi 0, 44, 30, %r25 ! \ 1656 depdi 0, 44, 30, %r25 ! \
1657 depd %r16, 14, 15, %r25 1657 depd %r16, 14, 15, %r25
1658 1658
1659LEAF_ENTRY($tlbd_u) 1659LEAF_ENTRY_NOPROFILE($tlbd_u)
1660 TLB_STATS_PRE(tlbd) 1660 TLB_STATS_PRE(tlbd)
1661 TLB_PULL_L(1, TLABEL(all)) 1661 TLB_PULL_L(1, TLABEL(all))
1662 TLB_PCX2PCXU 1662 TLB_PCX2PCXU
1663 idtlbt %r17, %r25 1663 idtlbt %r17, %r25
1664 TLB_STATS_AFT(tlbd) 1664 TLB_STATS_AFT(tlbd)
1665 rfir 1665 rfir
1666 nop 1666 nop
1667EXIT($tlbd_u) 1667EXIT($tlbd_u)
1668 1668
1669LEAF_ENTRY($itlb_u) 1669LEAF_ENTRY_NOPROFILE($itlb_u)
1670 TLB_STATS_PRE(itlb) 1670 TLB_STATS_PRE(itlb)
1671 TLB_PULL_L(0, TLABEL(all)) 1671 TLB_PULL_L(0, TLABEL(all))
1672 extru,= %r25, 5, 1, %r0 /* gate needs a kernel pid */ 1672 extru,= %r25, 5, 1, %r0 /* gate needs a kernel pid */
1673 depi 0, 30, 15, %r25 1673 depi 0, 30, 15, %r25
1674 TLB_PCX2PCXU 1674 TLB_PCX2PCXU
1675 iitlbt %r17, %r25 1675 iitlbt %r17, %r25
1676 TLB_STATS_AFT(itlb) 1676 TLB_STATS_AFT(itlb)
1677 rfir 1677 rfir
1678 nop 1678 nop
1679EXIT($itlb_u) 1679EXIT($itlb_u)
1680 1680
1681LEAF_ENTRY($dtlbna_u) 1681LEAF_ENTRY_NOPROFILE($dtlbna_u)
1682ALTENTRY($itlbna_u) 1682ALTENTRY($itlbna_u)
1683 TLB_STATS_PRE(dtlb) 1683 TLB_STATS_PRE(dtlb)
1684 TLB_PULL_L(0, $dtlbna_u_fake) 1684 TLB_PULL_L(0, $dtlbna_u_fake)
1685 TLB_PCX2PCXU 1685 TLB_PCX2PCXU
1686 idtlbt %r17, %r25 1686 idtlbt %r17, %r25
1687 TLB_STATS_AFT(dtlb) 1687 TLB_STATS_AFT(dtlb)
1688 rfir 1688 rfir
1689 nop 1689 nop
1690$dtlbna_u_fake: 1690$dtlbna_u_fake:
1691 /* parse prober/w insns, have to decent to trap() to set regs proper */ 1691 /* parse prober/w insns, have to decent to trap() to set regs proper */
1692 mfctl %iir, %r16 1692 mfctl %iir, %r16
1693 extru %r16, 6, 6, %r24 1693 extru %r16, 6, 6, %r24
1694 comib,=,n 1, %r24, TLABEL(all) 1694 comib,=,n 1, %r24, TLABEL(all)
@@ -1696,27 +1696,27 @@ $dtlbna_u_fake: @@ -1696,27 +1696,27 @@ $dtlbna_u_fake:
1696 subi,<> 0x23, %r24, %r0 1696 subi,<> 0x23, %r24, %r0
1697 b TLABEL(all) 1697 b TLABEL(all)
1698 /* otherwise generate a flush-only tlb entry */ 1698 /* otherwise generate a flush-only tlb entry */
1699 copy %r0, %r17 1699 copy %r0, %r17
1700 zdep %r8, 30, 15, %r25 1700 zdep %r8, 30, 15, %r25
1701 depi -13, 11, 7, %r25 1701 depi -13, 11, 7, %r25
1702 ldo 2(%r25), %r25 /* 3? */ 1702 ldo 2(%r25), %r25 /* 3? */
1703 idtlbt %r17, %r25 1703 idtlbt %r17, %r25
1704 TLB_STATS_AFT(dtlb) 1704 TLB_STATS_AFT(dtlb)
1705 rfir 1705 rfir
1706 nop 1706 nop
1707EXIT($dtlbna_u) 1707EXIT($dtlbna_u)
1708 1708
1709LEAF_ENTRY($dtlb_u) 1709LEAF_ENTRY_NOPROFILE($dtlb_u)
1710 TLB_STATS_PRE(dtlb) 1710 TLB_STATS_PRE(dtlb)
1711 TLB_PULL_L(0, TLABEL(all)) 1711 TLB_PULL_L(0, TLABEL(all))
1712 TLB_PCX2PCXU 1712 TLB_PCX2PCXU
1713 idtlbt %r17, %r25 1713 idtlbt %r17, %r25
1714 TLB_STATS_AFT(dtlb) 1714 TLB_STATS_AFT(dtlb)
1715 rfir 1715 rfir
1716 nop 1716 nop
1717EXIT($dtlb_u) 1717EXIT($dtlb_u)
1718 1718
1719 .level 1.1 1719 .level 1.1
1720#endif /* HP8000_CPU */ 1720#endif /* HP8000_CPU */
1721 1721
1722#if defined(HP7000_CPU) || defined(HP7100_CPU) 1722#if defined(HP7000_CPU) || defined(HP7100_CPU)
@@ -1739,27 +1739,27 @@ ALTENTRY(desidhash_x) @@ -1739,27 +1739,27 @@ ALTENTRY(desidhash_x)
1739 MTCPU_T(22,DR_CPUCFG) 1739 MTCPU_T(22,DR_CPUCFG)
1740 MTCPU_T(22,DR_CPUCFG) 1740 MTCPU_T(22,DR_CPUCFG)
1741 nop 1741 nop
1742 nop 1742 nop
1743 bv 0(%rp) 1743 bv 0(%rp)
1744 extru %t1, 4, 5, %ret0 /* return chip revision */ 1744 extru %t1, 4, 5, %ret0 /* return chip revision */
1745EXIT(desidhash_s) 1745EXIT(desidhash_s)
1746#endif /* defined(HP7000_CPU) || defined(HP7100_CPU) */ 1746#endif /* defined(HP7000_CPU) || defined(HP7100_CPU) */
1747 1747
1748#ifdef HP7200_CPU 1748#ifdef HP7200_CPU
1749/* 1749/*
1750 * void desidhash_t(void) 1750 * void desidhash_t(void)
1751 */ 1751 */
1752LEAF_ENTRY(desidhash_t) 1752LEAF_ENTRY_NOPROFILE(desidhash_t)
1753 sync 1753 sync
1754 MFCPU_T(DR_CPUCFG,22) /* %t1 */ 1754 MFCPU_T(DR_CPUCFG,22) /* %t1 */
1755 MFCPU_T(DR_CPUCFG,22) 1755 MFCPU_T(DR_CPUCFG,22)
1756 nop 1756 nop
1757 nop 1757 nop
1758 depi 0, DR0_PCXT_IHE, 1, %t1 1758 depi 0, DR0_PCXT_IHE, 1, %t1
1759 depi 0, DR0_PCXT_DHE, 1, %t1 1759 depi 0, DR0_PCXT_DHE, 1, %t1
1760 depi 0, DR0_PCXT_DHPMC, 1, %t1 1760 depi 0, DR0_PCXT_DHPMC, 1, %t1
1761 depi 0, DR0_PCXT_ILPMC, 1, %t1 1761 depi 0, DR0_PCXT_ILPMC, 1, %t1
1762 sync 1762 sync
1763 MTCPU_T(22,DR_CPUCFG) 1763 MTCPU_T(22,DR_CPUCFG)
1764 MTCPU_T(22,DR_CPUCFG) 1764 MTCPU_T(22,DR_CPUCFG)
1765 nop 1765 nop
@@ -1777,27 +1777,27 @@ EXIT(desidhash_t) @@ -1777,27 +1777,27 @@ EXIT(desidhash_t)
1777 */ 1777 */
1778LEAF_ENTRY_NOPROFILE(ibtlb_l) 1778LEAF_ENTRY_NOPROFILE(ibtlb_l)
1779 rsm (PSW_R|PSW_I), %t4 1779 rsm (PSW_R|PSW_I), %t4
1780 nop ! nop ! nop ! nop ! nop ! nop ! nop /* XXXNH why? */ 1780 nop ! nop ! nop ! nop ! nop ! nop ! nop /* XXXNH why? */
1781 1781
1782 bv 0(%rp) 1782 bv 0(%rp)
1783 mtsm %t4 1783 mtsm %t4
1784EXIT(ibtlb_l) 1784EXIT(ibtlb_l)
1785 1785
1786/* 1786/*
1787 * void 1787 * void
1788 * hpti_l(addr,size) 1788 * hpti_l(addr,size)
1789*/ 1789*/
1790LEAF_ENTRY(hpti_l) 1790LEAF_ENTRY_NOPROFILE(hpti_l)
1791 ldo -1(%arg1), %arg1 1791 ldo -1(%arg1), %arg1
1792 depi 0, 31, 12, %arg1 1792 depi 0, 31, 12, %arg1
1793 ldi 0x1c0, %t1 /* cache size assumed 128k XXX */ 1793 ldi 0x1c0, %t1 /* cache size assumed 128k XXX */
1794 or %arg0, %t1, %arg0 1794 or %arg0, %t1, %arg0
1795 sync 1795 sync
1796 MTCPU_C(26,DR0_PCXL2_HTLB_ADDR) 1796 MTCPU_C(26,DR0_PCXL2_HTLB_ADDR)
1797 MTCPU_C(25,DR0_PCXL2_HTLB_CFG) 1797 MTCPU_C(25,DR0_PCXL2_HTLB_CFG)
1798 nop 1798 nop
1799 nop 1799 nop
1800 bv,n %r0(%rp) 1800 bv,n %r0(%rp)
1801 nop 1801 nop
1802EXIT(hpti_l) 1802EXIT(hpti_l)
1803 1803
@@ -1875,41 +1875,41 @@ EXIT(desidhash_l) @@ -1875,41 +1875,41 @@ EXIT(desidhash_l)
1875 * Only shadowed registers are available, and they are: 1875 * Only shadowed registers are available, and they are:
1876 * 1876 *
1877 * %r1 = C trap number 1877 * %r1 = C trap number
1878 * %r8 = data address space identifier 1878 * %r8 = data address space identifier
1879 * %r9 = data address offset 1879 * %r9 = data address offset
1880 * %r16 = undefined 1880 * %r16 = undefined
1881 * %r17 = undefined 1881 * %r17 = undefined
1882 * %r24 = undefined 1882 * %r24 = undefined
1883 * %r25 = undefined 1883 * %r25 = undefined
1884 */ 1884 */
1885 1885
1886#if defined(HP8000_CPU) || defined(HP8200_CPU) || defined(HP8500_CPU) 1886#if defined(HP8000_CPU) || defined(HP8200_CPU) || defined(HP8500_CPU)
1887 .level 2.0w 1887 .level 2.0w
1888LEAF_ENTRY(desidhash_u) 1888LEAF_ENTRY_NOPROFILE(desidhash_u)
1889 MFCPU_U(2,28) 1889 MFCPU_U(2,28)
1890 depdi 0, 54, 1, %r28 1890 depdi 0, 54, 1, %r28
1891 MTCPU_U(28,2) 1891 MTCPU_U(28,2)
1892 bv %r0(%rp) 1892 bv %r0(%rp)
1893 copy %r0, %ret0 /* XXX dunno how to get chip rev */ 1893 copy %r0, %ret0 /* XXX dunno how to get chip rev */
1894EXIT(desidhash_u) 1894EXIT(desidhash_u)
1895 1895
1896LEAF_ENTRY(ibtlb_u) 1896LEAF_ENTRY_NOPROFILE(ibtlb_u)
1897 /* TODO insert a locked large tlb entry */ 1897 /* TODO insert a locked large tlb entry */
1898 bv 0(%rp) 1898 bv 0(%rp)
1899 nop 1899 nop
1900EXIT(ibtlb_u) 1900EXIT(ibtlb_u)
1901 1901
1902LEAF_ENTRY(pbtlb_u) 1902LEAF_ENTRY_NOPROFILE(pbtlb_u)
1903 /* TODO purge a locked tlb entry */ 1903 /* TODO purge a locked tlb entry */
1904 bv 0(%rp) 1904 bv 0(%rp)
1905 nop 1905 nop
1906EXIT(pbtlb_u) 1906EXIT(pbtlb_u)
1907 .level 1.1 1907 .level 1.1
1908#endif /* HP8000_CPU */ 1908#endif /* HP8000_CPU */
1909 1909
1910 .align 64 1910 .align 64
1911 .export TLABEL(all), entry 1911 .export TLABEL(all), entry
1912ENTRY_NOPROFILE(TLABEL(all),0) 1912ENTRY_NOPROFILE(TLABEL(all),0)
1913 /* 1913 /*
1914 * at this point we have: 1914 * at this point we have:
1915 * - psw copied into ipsw 1915 * - psw copied into ipsw