 @@ -1,2642 +1,2641 @@
-/*	$NetBSD: gem.c,v 1.82 2009/03/14 21:04:19 dsl Exp $ */
+/*	$NetBSD: gem.c,v 1.83 2009/03/16 12:02:00 tsutsui Exp $ */
 /*
+ *
  * Copyright (C) 2001 Eduardo Horvath.
  * Copyright (c) 2001-2003 Thomas Moestl
  * All rights reserved.
+ *
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  */
 /*
  * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers
  * See `GEM Gigabit Ethernet ASIC Specification'
  *   http://www.sun.com/processors/manuals/ge.pdf
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.82 2009/03/14 21:04:19 dsl Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.83 2009/03/16 12:02:00 tsutsui Exp $");
 #include "opt_inet.h"
 #include "bpfilter.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/syslog.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <machine/endian.h>
 #include <uvm/uvm_extern.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #ifdef INET
 #include <netinet/in.h>
 #include <netinet/in_systm.h>
 #include <netinet/in_var.h>
 #include <netinet/ip.h>
 #include <netinet/tcp.h>
 #include <netinet/udp.h>
 #endif
 #if NBPFILTER > 0
 #include <net/bpf.h>
 #endif
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/mii_bitbang.h>
 #include <dev/ic/gemreg.h>
 #include <dev/ic/gemvar.h>
 #define TRIES	10000
 static void	gem_start(struct ifnet *);
 static void	gem_stop(struct ifnet *, int);
 int		gem_ioctl(struct ifnet *, u_long, void *);
 void		gem_tick(void *);
 void		gem_watchdog(struct ifnet *);
 void		gem_shutdown(void *);
 void		gem_pcs_start(struct gem_softc *sc);
 void		gem_pcs_stop(struct gem_softc *sc, int);
 int		gem_init(struct ifnet *);
 void		gem_init_regs(struct gem_softc *sc);
 static int	gem_ringsize(int sz);
 static int	gem_meminit(struct gem_softc *);
 void		gem_mifinit(struct gem_softc *);
 static int	gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int,
 		    u_int32_t, u_int32_t);
 void		gem_reset(struct gem_softc *);
 int		gem_reset_rx(struct gem_softc *sc);
 static void	gem_reset_rxdma(struct gem_softc *sc);
 static void	gem_rx_common(struct gem_softc *sc);
 int		gem_reset_tx(struct gem_softc *sc);
 int		gem_disable_rx(struct gem_softc *sc);
 int		gem_disable_tx(struct gem_softc *sc);
 static void	gem_rxdrain(struct gem_softc *sc);
 int		gem_add_rxbuf(struct gem_softc *sc, int idx);
 void		gem_setladrf(struct gem_softc *);
 /* MII methods & callbacks */
 static int	gem_mii_readreg(struct device *, int, int);
 static void	gem_mii_writereg(struct device *, int, int, int);
 static void	gem_mii_statchg(struct device *);
 static int	gem_ifflags_cb(struct ethercom *);
 void		gem_statuschange(struct gem_softc *);
 int		gem_ser_mediachange(struct ifnet *);
 void		gem_ser_mediastatus(struct ifnet *, struct ifmediareq *);
 struct mbuf	*gem_get(struct gem_softc *, int, int);
 int		gem_put(struct gem_softc *, int, struct mbuf *);
 void		gem_read(struct gem_softc *, int, int);
 int		gem_pint(struct gem_softc *);
 int		gem_eint(struct gem_softc *, u_int);
 int		gem_rint(struct gem_softc *);
 int		gem_tint(struct gem_softc *);
 void		gem_power(int, void *);
 #ifdef GEM_DEBUG
 static void gem_txsoft_print(const struct gem_softc *, int, int);
 #define	DPRINTF(sc, x)	if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \
 				printf x
 #else
 #define	DPRINTF(sc, x)	/* nothing */
 #endif
 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header))
 /*
  * gem_attach:
+ *
  *	Attach a Gem interface to the system.
  */
 void
 gem_attach(struct gem_softc *sc, const uint8_t *enaddr)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct mii_data *mii = &sc->sc_mii;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	struct ifmedia_entry *ifm;
 	int i, error;
 	u_int32_t v;
 	char *nullbuf;
 	/* Make sure the chip is stopped. */
 	ifp->if_softc = sc;
 	gem_reset(sc);
 	/*
 	 * Allocate the control data structures, and create and load the
 	 * DMA map for it. gem_control_data is 9216 bytes, we have space for
 	 * the padding buffer in the bus_dmamem_alloc()'d memory.
 	 */
 	if ((error = bus_dmamem_alloc(sc->sc_dmatag,
 	    sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE,
 , &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) {
 		aprint_error_dev(&sc->sc_dev,
 		   "unable to allocate control data, error = %d\n",
 		    error);
 		goto fail_0;
+	}
 	/* XXX should map this in with correct endianness */
 	if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg,
 	    sizeof(struct gem_control_data), (void **)&sc->sc_control_data,
 	    BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n",
 		    error);
 		goto fail_1;
+	}
 	nullbuf =
 	    (char *)sc->sc_control_data + sizeof(struct gem_control_data);
 	if ((error = bus_dmamap_create(sc->sc_dmatag,
 	    sizeof(struct gem_control_data), 1,
 	    sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
 		aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, "
 		    "error = %d\n", error);
 		goto fail_2;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap,
 	    sc->sc_control_data, sizeof(struct gem_control_data), NULL,
 )) != 0) {
 		aprint_error_dev(&sc->sc_dev,
 		    "unable to load control data DMA map, error = %d\n",
 		    error);
 		goto fail_3;
+	}
 	memset(nullbuf, 0, ETHER_MIN_TX);
 	if ((error = bus_dmamap_create(sc->sc_dmatag,
 	    ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) {
 		aprint_error_dev(&sc->sc_dev, "unable to create padding DMA map, "
 		    "error = %d\n", error);
 		goto fail_4;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap,
 	    nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) {
 		aprint_error_dev(&sc->sc_dev,
 		    "unable to load padding DMA map, error = %d\n",
 		    error);
 		goto fail_5;
+	}
 	bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX,
 	    BUS_DMASYNC_PREWRITE);
 	/*
 	 * Initialize the transmit job descriptors.
 	 */
 	SIMPLEQ_INIT(&sc->sc_txfreeq);
 	SIMPLEQ_INIT(&sc->sc_txdirtyq);
 	/*
 	 * Create the transmit buffer DMA maps.
 	 */
 	for (i = 0; i < GEM_TXQUEUELEN; i++) {
 		struct gem_txsoft *txs;
 		txs = &sc->sc_txsoft[i];
 		txs->txs_mbuf = NULL;
 		if ((error = bus_dmamap_create(sc->sc_dmatag,
 		    ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS,
 		    ETHER_MAX_LEN_JUMBO, 0, 0,
 		    &txs->txs_dmamap)) != 0) {
 			aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, "
 			    "error = %d\n", i, error);
 			goto fail_6;
+		}
 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
+	}
 	/*
 	 * Create the receive buffer DMA maps.
 	 */
 	for (i = 0; i < GEM_NRXDESC; i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1,
 		    MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
 			aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, "
 			    "error = %d\n", i, error);
 			goto fail_7;
+		}
 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
+	}
 	/* Initialize ifmedia structures and MII info */
 	mii->mii_ifp = ifp;
 	mii->mii_readreg = gem_mii_readreg;
 	mii->mii_writereg = gem_mii_writereg;
 	mii->mii_statchg = gem_mii_statchg;
 	sc->sc_ethercom.ec_mii = mii;
 	/*
 	 * Initialization based  on `GEM Gigabit Ethernet ASIC Specification'
 	 * Section 3.2.1 `Initialization Sequence'.
 	 * However, we can't assume SERDES or Serialink if neither
 	 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set
 	 * being set, as both are set on Sun X1141A (with SERDES).  So,
 	 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL.
 	 * Also, for Apple variants with 2 PHY's, we prefer the external
 	 * PHY over the internal PHY.
 	 */
 	gem_mifinit(sc);
 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) {
 		ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
 		    ether_mediastatus);
 		mii_attach(&sc->sc_dev, mii, 0xffffffff,
 		    MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG);
 		if (LIST_EMPTY(&mii->mii_phys)) {
 				/* No PHY attached */
 				aprint_error_dev(&sc->sc_dev, "PHY probe failed\n");
 				goto fail_7;
 		} else {
 			struct mii_softc *child;
 			/*
 			 * Walk along the list of attached MII devices and
 			 * establish an `MII instance' to `PHY number'
 			 * mapping.
 			 */
 			LIST_FOREACH(child, &mii->mii_phys, mii_list) {
 				/*
 				 * Note: we support just one PHY: the internal
 				 * or external MII is already selected for us
 				 * by the GEM_MIF_CONFIG  register.
 				 */
 				if (child->mii_phy > 1 || child->mii_inst > 0) {
 					aprint_error_dev(&sc->sc_dev,
 					    "cannot accommodate MII device"
 					    " %s at PHY %d, instance %d\n",
 					       device_xname(child->mii_dev),
 					       child->mii_phy, child->mii_inst);
 					continue;
+				}
 				sc->sc_phys[child->mii_inst] = child->mii_phy;
+			}
 			/*
 			 * Now select and activate the PHY we will use.
+			 *
 			 * The order of preference is External (MDI1),
 			 * then Internal (MDI0),
 			 */
 			if (sc->sc_phys[1]) {
 #ifdef GEM_DEBUG
 				aprint_debug_dev(&sc->sc_dev, "using external PHY\n");
 #endif
 				sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
 			} else {
 #ifdef GEM_DEBUG
 				aprint_debug_dev(&sc->sc_dev, "using internal PHY\n");
 				sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
 #endif
+			}
 			bus_space_write_4(t, h, GEM_MIF_CONFIG,
 			    sc->sc_mif_config);
 			if (sc->sc_variant != GEM_SUN_ERI)
 				bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
 				    GEM_MII_DATAPATH_MII);
 			/*
 			 * XXX - we can really do the following ONLY if the
 			 * PHY indeed has the auto negotiation capability!!
 			 */
 			ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
+		}
 	} else {
 		ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange,
 		    gem_ser_mediastatus);
 		/* SERDES or Serialink */
 		if (sc->sc_flags & GEM_SERDES) {
 			bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
 			    GEM_MII_DATAPATH_SERDES);
 		} else {
 			sc->sc_flags |= GEM_SERIAL;
 			bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
 			    GEM_MII_DATAPATH_SERIAL);
+		}
 		aprint_normal_dev(&sc->sc_dev, "using external PCS %s: ",
 		    sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink");
 		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL);
 		/* Check for FDX and HDX capabilities */
 		sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR);
 		if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) {
 			ifmedia_add(&sc->sc_mii.mii_media,
 			    IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL);
 			aprint_normal("1000baseSX-FDX, ");
+		}
 		if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) {
 			ifmedia_add(&sc->sc_mii.mii_media,
 			    IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL);
 			aprint_normal("1000baseSX-HDX, ");
+		}
 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
 		sc->sc_mii_media = IFM_AUTO;
 		aprint_normal("auto\n");
 		gem_pcs_stop(sc, 1);
+	}
 	/*
 	 * From this point forward, the attachment cannot fail.  A failure
 	 * before this point releases all resources that may have been
 	 * allocated.
 	 */
 	/* Announce ourselves. */
 	aprint_normal_dev(&sc->sc_dev, "Ethernet address %s",
 	    ether_sprintf(enaddr));
 	/* Get RX FIFO size */
 	sc->sc_rxfifosize = 64 *
 	    bus_space_read_4(t, h, GEM_RX_FIFO_SIZE);
 	aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024);
 	/* Get TX FIFO size */
 	v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE);
 	aprint_normal(", %uKB TX fifo\n", v / 16);
 	/* Initialize ifnet structure. */
 	strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ);
 	ifp->if_softc = sc;
 	ifp->if_flags =
 	    IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
 	sc->sc_if_flags = ifp->if_flags;
 	/*
 	 * The GEM hardware supports basic TCP checksum offloading only.
 	 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80)
 	 * have bugs in the receive checksum, so don't enable it for now.
 	if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) ||
 	    (GEM_IS_APPLE(sc) &&
 	    (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80)))
 		ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx;
 	*/
 	ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx;
 	ifp->if_start = gem_start;
 	ifp->if_ioctl = gem_ioctl;
 	ifp->if_watchdog = gem_watchdog;
 	ifp->if_stop = gem_stop;
 	ifp->if_init = gem_init;
 	IFQ_SET_READY(&ifp->if_snd);
 	/*
 	 * If we support GigE media, we support jumbo frames too.
 	 * Unless we are Apple.
 	 */
 	TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) {
 		if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T ||
 		    IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX ||
 		    IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX ||
 		    IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) {
 			if (!GEM_IS_APPLE(sc))
 				sc->sc_ethercom.ec_capabilities
 				    |= ETHERCAP_JUMBO_MTU;
 			sc->sc_flags |= GEM_GIGABIT;
 			break;
+		}
+	}
 	/* claim 802.1q capability */
 	sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
 	/* Attach the interface. */
 	if_attach(ifp);
 	ether_ifattach(ifp, enaddr);
 	ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb);
 	sc->sc_sh = shutdownhook_establish(gem_shutdown, sc);
 	if (sc->sc_sh == NULL)
 		panic("gem_config: can't establish shutdownhook");
 #if NRND > 0
 	rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev),
 			  RND_TYPE_NET, 0);
 #endif
 	evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR,
 	    NULL, device_xname(&sc->sc_dev), "interrupts");
 #ifdef GEM_COUNTERS
 	evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR,
 	    &sc->sc_ev_intr, device_xname(&sc->sc_dev), "tx interrupts");
 	evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR,
 	    &sc->sc_ev_intr, device_xname(&sc->sc_dev), "rx interrupts");
 	evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR,
 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx ring full");
 	evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR,
 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx malloc failure");
 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR,
 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 0desc");
 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR,
 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 1desc");
 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR,
 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 2desc");
 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR,
 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 3desc");
 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR,
 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >3desc");
 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR,
 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >7desc");
 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR,
 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >15desc");
 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR,
 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >31desc");
 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR,
 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >63desc");
 #endif
 #if notyet
 	/*
 	 * Add a suspend hook to make sure we come back up after a
 	 * resume.
 	 */
 	sc->sc_powerhook = powerhook_establish(device_xname(&sc->sc_dev),
 	    gem_power, sc);
 	if (sc->sc_powerhook == NULL)
 		aprint_error_dev(&sc->sc_dev, "WARNING: unable to establish power hook\n");
 #endif
 	callout_init(&sc->sc_tick_ch, 0);
 	return;
 	/*
 	 * Free any resources we've allocated during the failed attach
 	 * attempt.  Do this in reverse order and fall through.
 	 */
  fail_7:
 	for (i = 0; i < GEM_NRXDESC; i++) {
 		if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmatag,
 			    sc->sc_rxsoft[i].rxs_dmamap);
+	}
  fail_6:
 	for (i = 0; i < GEM_TXQUEUELEN; i++) {
 		if (sc->sc_txsoft[i].txs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmatag,
 			    sc->sc_txsoft[i].txs_dmamap);
+	}
 	bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap);
  fail_5:
 	bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap);
  fail_4:
 	bus_dmamem_unmap(sc->sc_dmatag, (void *)nullbuf, ETHER_MIN_TX);
  fail_3:
 	bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap);
  fail_2:
 	bus_dmamem_unmap(sc->sc_dmatag, (void *)sc->sc_control_data,
 	    sizeof(struct gem_control_data));
  fail_1:
 	bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg);
  fail_0:
 	return;
+}
 void
 gem_tick(void *arg)
+{
 	struct gem_softc *sc = arg;
 	int s;
 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) {
 		/*
 		 * We have to reset everything if we failed to get a
 		 * PCS interrupt.  Restarting the callout is handled
 		 * in gem_pcs_start().
 		 */
 		gem_init(&sc->sc_ethercom.ec_if);
 	} else {
 		s = splnet();
 		mii_tick(&sc->sc_mii);
 		splx(s);
 		callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
+	}
+}
 static int
 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, u_int32_t clr, u_int32_t set)
+{
 	int i;
 	u_int32_t reg;
 	for (i = TRIES; i--; DELAY(100)) {
 		reg = bus_space_read_4(sc->sc_bustag, h, r);
 		if ((reg & clr) == 0 && (reg & set) == set)
 			return (1);
+	}
 	return (0);
+}
 void
 gem_reset(struct gem_softc *sc)
+{
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h2;
 	int s;
 	s = splnet();
 	DPRINTF(sc, ("%s: gem_reset\n", device_xname(&sc->sc_dev)));
 	gem_reset_rx(sc);
 	gem_reset_tx(sc);
 	/* Do a full reset */
 	bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX);
 	if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
 		aprint_error_dev(&sc->sc_dev, "cannot reset device\n");
 	splx(s);
+}
 /*
  * gem_rxdrain:
+ *
  *	Drain the receive queue.
  */
 static void
 gem_rxdrain(struct gem_softc *sc)
+{
 	struct gem_rxsoft *rxs;
 	int i;
 	for (i = 0; i < GEM_NRXDESC; i++) {
 		rxs = &sc->sc_rxsoft[i];
 		if (rxs->rxs_mbuf != NULL) {
 			bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
 			bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap);
 			m_freem(rxs->rxs_mbuf);
 			rxs->rxs_mbuf = NULL;
+		}
+	}
+}
 /*
  * Reset the whole thing.
  */
 static void
 gem_stop(struct ifnet *ifp, int disable)
+{
 	struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
 	struct gem_txsoft *txs;
 	DPRINTF(sc, ("%s: gem_stop\n", device_xname(&sc->sc_dev)));
 	callout_stop(&sc->sc_tick_ch);
 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0)
 		gem_pcs_stop(sc, disable);
 	else
 		mii_down(&sc->sc_mii);
 	/* XXX - Should we reset these instead? */
 	gem_disable_tx(sc);
 	gem_disable_rx(sc);
 	/*
 	 * Release any queued transmit buffers.
 	 */
 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
 		if (txs->txs_mbuf != NULL) {
 			bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0,
 			    txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
 			bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap);
 			m_freem(txs->txs_mbuf);
 			txs->txs_mbuf = NULL;
+		}
 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
+	}
 	/*
 	 * Mark the interface down and cancel the watchdog timer.
 	 */
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 	sc->sc_if_flags = ifp->if_flags;
 	ifp->if_timer = 0;
 	if (disable)
 		gem_rxdrain(sc);
+}
 /*
  * Reset the receiver
  */
 int
 gem_reset_rx(struct gem_softc *sc)
+{
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2;
 	/*
 	 * Resetting while DMA is in progress can cause a bus hang, so we
 	 * disable DMA first.
 	 */
 	gem_disable_rx(sc);
 	bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
 	bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
 	/* Wait till it finishes */
 	if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0))
 		aprint_error_dev(&sc->sc_dev, "cannot disable read dma\n");
 	/* Finally, reset the ERX */
 	bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX);
 	bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
 	/* Wait till it finishes */
 	if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) {
 		aprint_error_dev(&sc->sc_dev, "cannot reset receiver\n");
 		return (1);
+	}
 	return (0);
+}
 /*
  * Reset the receiver DMA engine.
+ *
  * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW
  * etc in order to reset the receiver DMA engine only and not do a full
  * reset which amongst others also downs the link and clears the FIFOs.
  */
 static void
 gem_reset_rxdma(struct gem_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	int i;
 	if (gem_reset_rx(sc) != 0) {
 		gem_init(ifp);
 		return;
+	}
 	for (i = 0; i < GEM_NRXDESC; i++)
 		if (sc->sc_rxsoft[i].rxs_mbuf != NULL)
 			GEM_UPDATE_RXDESC(sc, i);
 	sc->sc_rxptr = 0;
 	GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
 	GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
 	/* Reprogram Descriptor Ring Base Addresses */
 	/* NOTE: we use only 32-bit DMA addresses here. */
 	bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
 	bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
 	/* Redo ERX Configuration */
 	gem_rx_common(sc);
 	/* Give the reciever a swift kick */
 	bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4);
+}
 /*
  * Common RX configuration for gem_init() and gem_reset_rxdma().
  */
 static void
 gem_rx_common(struct gem_softc *sc)
+{
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	u_int32_t v;
 	/* Encode Receive Descriptor ring size: four possible values */
 	v = gem_ringsize(GEM_NRXDESC /*XXX*/);
 	/* Set receive h/w checksum offset */
 #ifdef INET
 	v |= (ETHER_HDR_LEN + sizeof(struct ip) +
 	    ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
 	    ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT;
 #endif
 	/* Enable RX DMA */
 	bus_space_write_4(t, h, GEM_RX_CONFIG,
 	    v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
 	    (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN);
 	/*
 	 * The following value is for an OFF Threshold of about 3/4 full
 	 * and an ON Threshold of 1/4 full.
 	 */
 	bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
 	    (3 * sc->sc_rxfifosize / 256) |
 	    ((sc->sc_rxfifosize / 256) << 12));
 	bus_space_write_4(t, h, GEM_RX_BLANKING,
 	    (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6);
+}
 /*
  * Reset the transmitter
  */
 int
 gem_reset_tx(struct gem_softc *sc)
+{
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2;
 	/*
 	 * Resetting while DMA is in progress can cause a bus hang, so we
 	 * disable DMA first.
 	 */
 	gem_disable_tx(sc);
 	bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
 	bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
 	/* Wait till it finishes */
 	if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0))
 		aprint_error_dev(&sc->sc_dev, "cannot disable read dma\n");
 	/* Wait 5ms extra. */
 	delay(5000);
 	/* Finally, reset the ETX */
 	bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX);
 	bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
 	/* Wait till it finishes */
 	if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) {
 		aprint_error_dev(&sc->sc_dev, "cannot reset receiver\n");
 		return (1);
+	}
 	return (0);
+}
 /*
  * disable receiver.
  */
 int
 gem_disable_rx(struct gem_softc *sc)
+{
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	u_int32_t cfg;
 	/* Flip the enable bit */
 	cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
 	cfg &= ~GEM_MAC_RX_ENABLE;
 	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
 	bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
 	/* Wait for it to finish */
 	return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
+}
 /*
  * disable transmitter.
  */
 int
 gem_disable_tx(struct gem_softc *sc)
+{
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	u_int32_t cfg;
 	/* Flip the enable bit */
 	cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
 	cfg &= ~GEM_MAC_TX_ENABLE;
 	bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
 	bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
 	/* Wait for it to finish */
 	return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
+}
 /*
  * Initialize interface.
  */
 int
 gem_meminit(struct gem_softc *sc)
+{
 	struct gem_rxsoft *rxs;
 	int i, error;
 	/*
 	 * Initialize the transmit descriptor ring.
 	 */
 	memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
 	for (i = 0; i < GEM_NTXDESC; i++) {
 		sc->sc_txdescs[i].gd_flags = 0;
 		sc->sc_txdescs[i].gd_addr = 0;
+	}
 	GEM_CDTXSYNC(sc, 0, GEM_NTXDESC,
 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 	sc->sc_txfree = GEM_NTXDESC-1;
 	sc->sc_txnext = 0;
 	sc->sc_txwin = 0;
 	/*
 	 * Initialize the receive descriptor and receive job
 	 * descriptor rings.
 	 */
 	for (i = 0; i < GEM_NRXDESC; i++) {
 		rxs = &sc->sc_rxsoft[i];
 		if (rxs->rxs_mbuf == NULL) {
 			if ((error = gem_add_rxbuf(sc, i)) != 0) {
 				aprint_error_dev(&sc->sc_dev, "unable to allocate or map rx "
 				    "buffer %d, error = %d\n",
 				    i, error);
 				/*
 				 * XXX Should attempt to run with fewer receive
 				 * XXX buffers instead of just failing.
 				 */
 				gem_rxdrain(sc);
 				return (1);
+			}
 		} else
 			GEM_INIT_RXDESC(sc, i);
+	}
 	sc->sc_rxptr = 0;
 	sc->sc_meminited = 1;
 	GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
 	GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
 	return (0);
+}
 static int
 gem_ringsize(int sz)
+{
 	switch (sz) {
 	case 32:
 		return GEM_RING_SZ_32;
 	case 64:
 		return GEM_RING_SZ_64;
 	case 128:
 		return GEM_RING_SZ_128;
 	case 256:
 		return GEM_RING_SZ_256;
 	case 512:
 		return GEM_RING_SZ_512;
 	case 1024:
 		return GEM_RING_SZ_1024;
 	case 2048:
 		return GEM_RING_SZ_2048;
 	case 4096:
 		return GEM_RING_SZ_4096;
 	case 8192:
 		return GEM_RING_SZ_8192;
 	default:
 		printf("gem: invalid Receive Descriptor ring size %d\n", sz);
 		return GEM_RING_SZ_32;
+	}
+}
 /*
  * Start PCS
  */
 void
 gem_pcs_start(struct gem_softc *sc)
+{
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	uint32_t v;
 #ifdef GEM_DEBUG
 	aprint_debug_dev(&sc->sc_dev, "gem_pcs_start()\n");
 #endif
 	/*
 	 * Set up.  We must disable the MII before modifying the
 	 * GEM_MII_ANAR register
 	 */
 	if (sc->sc_flags & GEM_SERDES) {
 		bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
 		    GEM_MII_DATAPATH_SERDES);
 		bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL,
 		    GEM_MII_SLINK_LOOPBACK);
 	} else {
 		bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
 		    GEM_MII_DATAPATH_SERIAL);
 		bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0);
+	}
 	bus_space_write_4(t, h, GEM_MII_CONFIG, 0);
 	v = bus_space_read_4(t, h, GEM_MII_ANAR);
 	v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE);
 	if (sc->sc_mii_media == IFM_AUTO)
 		v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX);
 	else if (sc->sc_mii_media == IFM_FDX) {
 		v |= GEM_MII_ANEG_FUL_DUPLX;
 		v &= ~GEM_MII_ANEG_HLF_DUPLX;
 	} else if (sc->sc_mii_media == IFM_HDX) {
 		v &= ~GEM_MII_ANEG_FUL_DUPLX;
 		v |= GEM_MII_ANEG_HLF_DUPLX;
+	}
 	/* Configure link. */
 	bus_space_write_4(t, h, GEM_MII_ANAR, v);
 	bus_space_write_4(t, h, GEM_MII_CONTROL,
 	    GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN);
 	bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE);
 	gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT);
 	/* Start the 10 second timer */
 	callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc);
+}
 /*
  * Stop PCS
  */
 void
 gem_pcs_stop(struct gem_softc *sc, int disable)
+{
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 #ifdef GEM_DEBUG
 	aprint_debug_dev(&sc->sc_dev, "gem_pcs_stop()\n");
 #endif
 	/* Tell link partner that we're going away */
 	bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF);
 	/*
 	 * Disable PCS MII.  The documentation suggests that setting
 	 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto-
 	 * negotiation will shut down the link.  However, it appears
 	 * that we also need to unset the datapath mode.
 	 */
 	bus_space_write_4(t, h, GEM_MII_CONFIG, 0);
 	bus_space_write_4(t, h, GEM_MII_CONTROL,
 	    GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN);
 	bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII);
 	bus_space_write_4(t, h, GEM_MII_CONFIG, 0);
 	if (disable) {
 		if (sc->sc_flags & GEM_SERDES)
 			bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL,
 				GEM_MII_SLINK_POWER_OFF);
 		else
 			bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL,
 			    GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF);
+	}
 	sc->sc_flags &= ~GEM_LINK;
 	sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE;
 	sc->sc_mii.mii_media_status = IFM_AVALID;
+}
 /*
  * Initialization of interface; set up initialization block
  * and transmit/receive descriptor rings.
  */
 int
 gem_init(struct ifnet *ifp)
+{
 	struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	int rc = 0, s;
 	u_int max_frame_size;
 	u_int32_t v;
 	s = splnet();
 	DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(&sc->sc_dev)));
 	/*
 	 * Initialization sequence. The numbered steps below correspond
 	 * to the sequence outlined in section 6.3.5.1 in the Ethernet
 	 * Channel Engine manual (part of the PCIO manual).
 	 * See also the STP2002-STQ document from Sun Microsystems.
 	 */
 	/* step 1 & 2. Reset the Ethernet Channel */
 	gem_stop(ifp, 0);
 	gem_reset(sc);
 	DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(&sc->sc_dev)));
 	/* Re-initialize the MIF */
 	gem_mifinit(sc);
 	/* Set up correct datapath for non-SERDES/Serialink */
 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 &&
 	    sc->sc_variant != GEM_SUN_ERI)
 		bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
 		    GEM_MII_DATAPATH_MII);
 	/* Call MI reset function if any */
 	if (sc->sc_hwreset)
 		(*sc->sc_hwreset)(sc);
 	/* step 3. Setup data structures in host memory */
 	if (gem_meminit(sc) != 0)
 		return 1;
 	/* step 4. TX MAC registers & counters */
 	gem_init_regs(sc);
 	max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU);
 	max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN;
 	if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)
 		max_frame_size += ETHER_VLAN_ENCAP_LEN;
 	bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
 	    max_frame_size|/* burst size */(0x2000<<16));
 	/* step 5. RX MAC registers & counters */
 	gem_setladrf(sc);
 	/* step 6 & 7. Program Descriptor Ring Base Addresses */
 	/* NOTE: we use only 32-bit DMA addresses here. */
 	bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0);
 	bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
 	bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
 	bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
 	/* step 8. Global Configuration & Interrupt Mask */
 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0)
 		v = GEM_INTR_PCS;
 	else
 		v = GEM_INTR_MIF;
 	bus_space_write_4(t, h, GEM_INTMASK,
 		      ~(GEM_INTR_TX_INTME |
 			GEM_INTR_TX_EMPTY |
 			GEM_INTR_TX_MAC |
 			GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF|
 			GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL|
 			GEM_INTR_BERR | v));
 	bus_space_write_4(t, h, GEM_MAC_RX_MASK,
 			GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
 	bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */
 	bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK,
 	    GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME);
 	/* step 9. ETX Configuration: use mostly default values */
 	/* Enable TX DMA */
 	v = gem_ringsize(GEM_NTXDESC /*XXX*/);
 	bus_space_write_4(t, h, GEM_TX_CONFIG,
 		v|GEM_TX_CONFIG_TXDMA_EN|
 		((0x4FF<<10)&GEM_TX_CONFIG_TXFIFO_TH));
 	bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext);
 	/* step 10. ERX Configuration */
 	gem_rx_common(sc);
 	/* step 11. Configure Media */
 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 &&
 	    (rc = mii_ifmedia_change(&sc->sc_mii)) != 0)
 		goto out;
 	/* step 12. RX_MAC Configuration Register */
 	v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
 	v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC;
 	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
 	/* step 14. Issue Transmit Pending command */
 	/* Call MI initialization function if any */
 	if (sc->sc_hwinit)
 		(*sc->sc_hwinit)(sc);
 	/* step 15.  Give the reciever a swift kick */
 	bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0)
 		/* Configure PCS */
 		gem_pcs_start(sc);
 	else
 		/* Start the one second timer. */
 		callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
 	sc->sc_flags &= ~GEM_LINK;
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	ifp->if_timer = 0;
 	sc->sc_if_flags = ifp->if_flags;
 out:
 	splx(s);
 	return (0);
+}
 void
 gem_init_regs(struct gem_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	const u_char *laddr = CLLADDR(ifp->if_sadl);
 	u_int32_t v;
 	/* These regs are not cleared on reset */
 	if (!sc->sc_inited) {
 		/* Load recommended values */
 		bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00);
 		bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08);
 		bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04);
 		bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
 		/* Max frame and max burst size */
 		bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
 		    ETHER_MAX_LEN | (0x2000<<16));
 		bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07);
 		bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04);
 		bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
 		bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
 		bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
 		    ((laddr[5]<<8)|laddr[4])&0x3ff);
 		/* Secondary MAC addr set to 0:0:0:0:0:0 */
 		bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
 		bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
 		bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
 		/* MAC control addr set to 01:80:c2:00:00:01 */
 		bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
 		bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
 		bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
 		/* MAC filter addr set to 0:0:0:0:0:0 */
 		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
 		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
 		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
 		bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
 		bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
 		sc->sc_inited = 1;
+	}
 	/* Counters need to be zeroed */
 	bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
 	bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
 	bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
 	bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
 	bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
 	bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
 	bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
 	bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
 	bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
 	bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
 	bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
 	/* Set XOFF PAUSE time. */
 	bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
 	/*
 	 * Set the internal arbitration to "infinite" bursts of the
 	 * maximum length of 31 * 64 bytes so DMA transfers aren't
 	 * split up in cache line size chunks. This greatly improves
 	 * especially RX performance.
 	 * Enable silicon bug workarounds for the Apple variants.
 	 */
 	bus_space_write_4(t, h, GEM_CONFIG,
 	    GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT |
 	    ((sc->sc_flags & GEM_PCI) ?
 	    GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ?
 	    GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0));
 	/*
 	 * Set the station address.
 	 */
 	bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
 	bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
 	bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
 	/*
 	 * Enable MII outputs.  Enable GMII if there is a gigabit PHY.
 	 */
 	sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
 	v = GEM_MAC_XIF_TX_MII_ENA;
 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0)  {
 		if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
 			v |= GEM_MAC_XIF_FDPLX_LED;
 				if (sc->sc_flags & GEM_GIGABIT)
 					v |= GEM_MAC_XIF_GMII_MODE;
+		}
 	} else {
 		v |= GEM_MAC_XIF_GMII_MODE;
+	}
 	bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
+}
 #ifdef GEM_DEBUG
 static void
 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc)
+{
 	int i;
 	for (i = firstdesc;; i = GEM_NEXTTX(i)) {
 		printf("descriptor %d:\t", i);
 		printf("gd_flags:   0x%016" PRIx64 "\t",
 			GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags));
 		printf("gd_addr: 0x%016" PRIx64 "\n",
 			GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr));
 		if (i == lastdesc)
 			break;
+	}
+}
 #endif
 static void
 gem_start(struct ifnet *ifp)
+{
 	struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
 	struct mbuf *m0, *m;
 	struct gem_txsoft *txs;
 	bus_dmamap_t dmamap;
 	int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg;
 	uint64_t flags = 0;
 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
 		return;
 	/*
 	 * Remember the previous number of free descriptors and
 	 * the first descriptor we'll use.
 	 */
 	ofree = sc->sc_txfree;
 	firsttx = sc->sc_txnext;
 	DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n",
 	    device_xname(&sc->sc_dev), ofree, firsttx));
 	/*
 	 * Loop through the send queue, setting up transmit descriptors
 	 * until we drain the queue, or use up all available transmit
 	 * descriptors.
 	 */
 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL &&
 	    sc->sc_txfree != 0) {
 		/*
 		 * Grab a packet off the queue.
 		 */
 		IFQ_POLL(&ifp->if_snd, m0);
 		if (m0 == NULL)
 			break;
 		m = NULL;
 		dmamap = txs->txs_dmamap;
 		/*
 		 * Load the DMA map.  If this fails, the packet either
 		 * didn't fit in the alloted number of segments, or we were
 		 * short on resources.  In this case, we'll copy and try
 		 * again.
 		 */
 		if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0,
 		      BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 ||
 		      (m0->m_pkthdr.len < ETHER_MIN_TX &&
 		       dmamap->dm_nsegs == GEM_NTXSEGS)) {
 			if (m0->m_pkthdr.len > MCLBYTES) {
 				aprint_error_dev(&sc->sc_dev, "unable to allocate jumbo Tx "
 				    "cluster\n");
 				IFQ_DEQUEUE(&ifp->if_snd, m0);
 				m_freem(m0);
 				continue;
+			}
 			MGETHDR(m, M_DONTWAIT, MT_DATA);
 			if (m == NULL) {
 				aprint_error_dev(&sc->sc_dev, "unable to allocate Tx mbuf\n");
 				break;
+			}
 			MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner);
 			if (m0->m_pkthdr.len > MHLEN) {
 				MCLGET(m, M_DONTWAIT);
 				if ((m->m_flags & M_EXT) == 0) {
 					aprint_error_dev(&sc->sc_dev, "unable to allocate Tx "
 					    "cluster\n");
 					m_freem(m);
 					break;
+				}
+			}
 			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
 			m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
 			error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap,
 			    m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
 			if (error) {
 				aprint_error_dev(&sc->sc_dev, "unable to load Tx buffer, "
 				    "error = %d\n", error);
 				break;
+			}
+		}
 		/*
 		 * Ensure we have enough descriptors free to describe
 		 * the packet.
 		 */
 		if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ?
 		     (sc->sc_txfree - 1) : sc->sc_txfree)) {
 			/*
 			 * Not enough free descriptors to transmit this
 			 * packet.  We haven't committed to anything yet,
 			 * so just unload the DMA map, put the packet
 			 * back on the queue, and punt.  Notify the upper
 			 * layer that there are no more slots left.
+			 *
 			 * XXX We could allocate an mbuf and copy, but
 			 * XXX it is worth it?
 			 */
 			ifp->if_flags |= IFF_OACTIVE;
 			sc->sc_if_flags = ifp->if_flags;
 			bus_dmamap_unload(sc->sc_dmatag, dmamap);
 			if (m != NULL)
 				m_freem(m);
 			break;
+		}
 		IFQ_DEQUEUE(&ifp->if_snd, m0);
 		if (m != NULL) {
 			m_freem(m0);
 			m0 = m;
+		}
 		/*
 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
 		 */
 		/* Sync the DMA map. */
 		bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize,
 		    BUS_DMASYNC_PREWRITE);
 		/*
 		 * Initialize the transmit descriptors.
 		 */
 		for (nexttx = sc->sc_txnext, seg = 0;
 		     seg < dmamap->dm_nsegs;
 		     seg++, nexttx = GEM_NEXTTX(nexttx)) {
 			/*
 			 * If this is the first descriptor we're
 			 * enqueueing, set the start of packet flag,
 			 * and the checksum stuff if we want the hardware
 			 * to do it.
 			 */
 			sc->sc_txdescs[nexttx].gd_addr =
 			    GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr);
 			flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE;
 			if (nexttx == firsttx) {
 				flags |= GEM_TD_START_OF_PACKET;
 				if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
 					sc->sc_txwin = 0;
 					flags |= GEM_TD_INTERRUPT_ME;
+				}
 #ifdef INET
 				/* h/w checksum */
 				if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 &&
 				    m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) {
 					struct ether_header *eh;
 					uint16_t offset, start;
 					eh = mtod(m0, struct ether_header *);
 					switch (ntohs(eh->ether_type)) {
 					case ETHERTYPE_IP:
 						start = ETHER_HDR_LEN;
 						break;
 					case ETHERTYPE_VLAN:
 						start = ETHER_HDR_LEN +
 							ETHER_VLAN_ENCAP_LEN;
 						break;
 					default:
 						/* unsupported, drop it */
 						m_free(m0);
 						continue;
+					}
 					start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
 					offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start;
 					flags |= (start <<
 						  GEM_TD_CXSUM_STARTSHFT) |
 						 (offset <<
 						  GEM_TD_CXSUM_STUFFSHFT) |
 						 GEM_TD_CXSUM_ENABLE;
+				}
 #endif
+			}
 			if (seg == dmamap->dm_nsegs - 1) {
 				flags |= GEM_TD_END_OF_PACKET;
 			} else {
 				/* last flag set outside of loop */
 				sc->sc_txdescs[nexttx].gd_flags =
 					GEM_DMA_WRITE(sc, flags);
+			}
 			lasttx = nexttx;
+		}
 		if (m0->m_pkthdr.len < ETHER_MIN_TX) {
 			/* add padding buffer at end of chain */
 			flags &= ~GEM_TD_END_OF_PACKET;
 			sc->sc_txdescs[lasttx].gd_flags =
 			    GEM_DMA_WRITE(sc, flags);
 			sc->sc_txdescs[nexttx].gd_addr =
 			    GEM_DMA_WRITE(sc,
 			    sc->sc_nulldmamap->dm_segs[0].ds_addr);
 			flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) &
 			    GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET;
 			lasttx = nexttx;
 			nexttx = GEM_NEXTTX(nexttx);
 			seg++;
+		}
 		sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags);
 		KASSERT(lasttx != -1);
 		/*
 		 * Store a pointer to the packet so we can free it later,
 		 * and remember what txdirty will be once the packet is
 		 * done.
 		 */
 		txs->txs_mbuf = m0;
 		txs->txs_firstdesc = sc->sc_txnext;
 		txs->txs_lastdesc = lasttx;
 		txs->txs_ndescs = seg;
 #ifdef GEM_DEBUG
 		if (ifp->if_flags & IFF_DEBUG) {
 			printf("     gem_start %p transmit chain:\n", txs);
 			gem_txsoft_print(sc, txs->txs_firstdesc,
 			    txs->txs_lastdesc);
+		}
 #endif
 		/* Sync the descriptors we're using. */
 		GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs,
 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 		/* Advance the tx pointer. */
 		sc->sc_txfree -= txs->txs_ndescs;
 		sc->sc_txnext = nexttx;
 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
 		SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
 #if NBPFILTER > 0
 		/*
 		 * Pass the packet to any BPF listeners.
 		 */
 		if (ifp->if_bpf)
 			bpf_mtap(ifp->if_bpf, m0);
 #endif /* NBPFILTER > 0 */
+	}
 	if (txs == NULL || sc->sc_txfree == 0) {
 		/* No more slots left; notify upper layer. */
 		ifp->if_flags |= IFF_OACTIVE;
 		sc->sc_if_flags = ifp->if_flags;
+	}
 	if (sc->sc_txfree != ofree) {
 		DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n",
 		    device_xname(&sc->sc_dev), lasttx, firsttx));
 		/*
 		 * The entire packet chain is set up.
 		 * Kick the transmitter.
 		 */
 		DPRINTF(sc, ("%s: gem_start: kicking tx %d\n",
 			device_xname(&sc->sc_dev), nexttx));
 		bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK,
 			sc->sc_txnext);
 		/* Set a watchdog timer in case the chip flakes out. */
 		ifp->if_timer = 5;
 		DPRINTF(sc, ("%s: gem_start: watchdog %d\n",
 			device_xname(&sc->sc_dev), ifp->if_timer));
+	}
+}
 /*
  * Transmit interrupt.
  */
 int
 gem_tint(struct gem_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mac = sc->sc_h1;
 	struct gem_txsoft *txs;
 	int txlast;
 	int progress = 0;
 	u_int32_t v;
 	DPRINTF(sc, ("%s: gem_tint\n", device_xname(&sc->sc_dev)));
 	/* Unload collision counters ... */
 	v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) +
 	    bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT);
 	ifp->if_collisions += v +
 	    bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) +
 	    bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT);
 	ifp->if_oerrors += v;
 	/* ... then clear the hardware counters. */
 	bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0);
 	bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
 	bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
 	bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
 	/*
 	 * Go through our Tx list and free mbufs for those
 	 * frames that have been transmitted.
 	 */
 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
 		/*
 		 * In theory, we could harvest some descriptors before
 		 * the ring is empty, but that's a bit complicated.
+		 *
 		 * GEM_TX_COMPLETION points to the last descriptor
 		 * processed +1.
+		 *
 		 * Let's assume that the NIC writes back to the Tx
 		 * descriptors before it updates the completion
 		 * register.  If the NIC has posted writes to the
 		 * Tx descriptors, PCI ordering requires that the
 		 * posted writes flush to RAM before the register-read
 		 * finishes.  So let's read the completion register,
 		 * before syncing the descriptors, so that we
 		 * examine Tx descriptors that are at least as
 		 * current as the completion register.
 		 */
 		txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION);
 		DPRINTF(sc,
 			("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n",
 				txs->txs_lastdesc, txlast));
 		if (txs->txs_firstdesc <= txs->txs_lastdesc) {
 			if (txlast >= txs->txs_firstdesc &&
 			    txlast <= txs->txs_lastdesc)
 				break;
 		} else if (txlast >= txs->txs_firstdesc ||
 			   txlast <= txs->txs_lastdesc)
 			break;
 		GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs,
 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 #ifdef GEM_DEBUG	/* XXX DMA synchronization? */
 		if (ifp->if_flags & IFF_DEBUG) {
 			printf("    txsoft %p transmit chain:\n", txs);
 			gem_txsoft_print(sc, txs->txs_firstdesc,
 			    txs->txs_lastdesc);
+		}
 #endif
 		DPRINTF(sc, ("gem_tint: releasing a desc\n"));
 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
 		sc->sc_txfree += txs->txs_ndescs;
 		bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap,
 , txs->txs_dmamap->dm_mapsize,
 		    BUS_DMASYNC_POSTWRITE);
 		bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap);
 		if (txs->txs_mbuf != NULL) {
 			m_freem(txs->txs_mbuf);
 			txs->txs_mbuf = NULL;
+		}
 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
 		ifp->if_opackets++;
 		progress = 1;
+	}
 #if 0
 	DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x "
 		"GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n",
 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE),
 		((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1,
 			GEM_TX_DATA_PTR_HI) << 32) |
 			     bus_space_read_4(sc->sc_bustag, sc->sc_h1,
 			GEM_TX_DATA_PTR_LO),
 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION)));
 #endif
 	if (progress) {
 		if (sc->sc_txfree == GEM_NTXDESC - 1)
 			sc->sc_txwin = 0;
 		/* Freed some descriptors, so reset IFF_OACTIVE and restart. */
 		ifp->if_flags &= ~IFF_OACTIVE;
 		sc->sc_if_flags = ifp->if_flags;
 		ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5;
 		gem_start(ifp);
+	}
 	DPRINTF(sc, ("%s: gem_tint: watchdog %d\n",
 		device_xname(&sc->sc_dev), ifp->if_timer));
 	return (1);
+}
 /*
  * Receive interrupt.
  */
 int
 gem_rint(struct gem_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	struct gem_rxsoft *rxs;
 	struct mbuf *m;
 	u_int64_t rxstat;
 	u_int32_t rxcomp;
 	int i, len, progress = 0;
 	DPRINTF(sc, ("%s: gem_rint\n", device_xname(&sc->sc_dev)));
 	/*
 	 * Ignore spurious interrupt that sometimes occurs before
 	 * we are set up when we network boot.
 	 */
 	if (!sc->sc_meminited)
 		return 1;
 	/*
 	 * Read the completion register once.  This limits
 	 * how long the following loop can execute.
 	 */
 	rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
 	/*
 	 * XXX Read the lastrx only once at the top for speed.
 	 */
 	DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n",
 		sc->sc_rxptr, rxcomp));
 	/*
 	 * Go into the loop at least once.
 	 */
 	for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp;
 	     i = GEM_NEXTRX(i)) {
 		rxs = &sc->sc_rxsoft[i];
 		GEM_CDRXSYNC(sc, i,
 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 		rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
 		if (rxstat & GEM_RD_OWN) {
 			GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD);
 			/*
 			 * We have processed all of the receive buffers.
 			 */
 			break;
+		}
 		progress++;
 		ifp->if_ipackets++;
 		if (rxstat & GEM_RD_BAD_CRC) {
 			ifp->if_ierrors++;
 			aprint_error_dev(&sc->sc_dev, "receive error: CRC error\n");
 			GEM_INIT_RXDESC(sc, i);
 			continue;
+		}
 		bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
 #ifdef GEM_DEBUG
 		if (ifp->if_flags & IFF_DEBUG) {
 			printf("    rxsoft %p descriptor %d: ", rxs, i);
 			printf("gd_flags: 0x%016llx\t", (long long)
 				GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
 			printf("gd_addr: 0x%016llx\n", (long long)
 				GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
+		}
 #endif
 		/* No errors; receive the packet. */
 		len = GEM_RD_BUFLEN(rxstat);
 		/*
 		 * Allocate a new mbuf cluster.  If that fails, we are
 		 * out of memory, and must drop the packet and recycle
 		 * the buffer that's already attached to this descriptor.
 		 */
 		m = rxs->rxs_mbuf;
 		if (gem_add_rxbuf(sc, i) != 0) {
 			GEM_COUNTER_INCR(sc, sc_ev_rxnobuf);
 			ifp->if_ierrors++;
 			GEM_INIT_RXDESC(sc, i);
 			bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 			continue;
+		}
 		m->m_data += 2; /* We're already off by two */
 		m->m_pkthdr.rcvif = ifp;
 		m->m_pkthdr.len = m->m_len = len;
 #if NBPFILTER > 0
 		/*
 		 * Pass this up to any BPF listeners, but only
 		 * pass it up the stack if it's for us.
 		 */
 		if (ifp->if_bpf)
 			bpf_mtap(ifp->if_bpf, m);
 #endif /* NBPFILTER > 0 */
 #ifdef INET
 		/* hardware checksum */
 		if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) {
 			struct ether_header *eh;
 			struct ip *ip;
 			int32_t hlen, pktlen;
 			if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) {
 				pktlen = m->m_pkthdr.len - ETHER_HDR_LEN -
 					 ETHER_VLAN_ENCAP_LEN;
 				eh = (struct ether_header *) (mtod(m, char *) +
 					ETHER_VLAN_ENCAP_LEN);
 			} else {
 				pktlen = m->m_pkthdr.len - ETHER_HDR_LEN;
 				eh = mtod(m, struct ether_header *);
+			}
 			if (ntohs(eh->ether_type) != ETHERTYPE_IP)
 				goto swcsum;
 			ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN);
 			/* IPv4 only */
 			if (ip->ip_v != IPVERSION)
 				goto swcsum;
 			hlen = ip->ip_hl << 2;
 			if (hlen < sizeof(struct ip))
 				goto swcsum;
 			/*
 			 * bail if too short, has random trailing garbage,
 			 * truncated, fragment, or has ethernet pad.
 			 */
 			if ((ntohs(ip->ip_len) < hlen) ||
 			    (ntohs(ip->ip_len) != pktlen) ||
 			    (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)))
 				goto swcsum;
 			switch (ip->ip_p) {
 			case IPPROTO_TCP:
 				if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4))
 					goto swcsum;
 				if (pktlen < (hlen + sizeof(struct tcphdr)))
 					goto swcsum;
 				m->m_pkthdr.csum_flags = M_CSUM_TCPv4;
 				break;
 			case IPPROTO_UDP:
 				/* FALLTHROUGH */
 			default:
 				goto swcsum;
+			}
 			/* the uncomplemented sum is expected */
 			m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM;
 			/* if the pkt had ip options, we have to deduct them */
 			if (hlen > sizeof(struct ip)) {
 				uint16_t *opts;
 				uint32_t optsum, temp;
 				optsum = 0;
 				temp = hlen - sizeof(struct ip);
 				opts = (uint16_t *) ((char *) ip +
 					sizeof(struct ip));
 				while (temp > 1) {
 					optsum += ntohs(*opts++);
 					temp -= 2;
+				}
 				while (optsum >> 16)
 					optsum = (optsum >> 16) +
 						 (optsum & 0xffff);
-				/* Deduct ip opts sum from hwsum (rfc 1624). */
+				/* Deduct ip opts sum from hwsum. */
-				m->m_pkthdr.csum_data =
+				m->m_pkthdr.csum_data += (uint16_t)~optsum;
 					~((~m->m_pkthdr.csum_data) - ~optsum);
 				while (m->m_pkthdr.csum_data >> 16)
 					m->m_pkthdr.csum_data =
 						(m->m_pkthdr.csum_data >> 16) +
 						(m->m_pkthdr.csum_data &
 xffff);
+			}
 			m->m_pkthdr.csum_flags |= M_CSUM_DATA |
 						  M_CSUM_NO_PSEUDOHDR;
 		} else
 swcsum:
 			m->m_pkthdr.csum_flags = 0;
 #endif
 		/* Pass it on. */
 		(*ifp->if_input)(ifp, m);
+	}
 	if (progress) {
 		/* Update the receive pointer. */
 		if (i == sc->sc_rxptr) {
 			GEM_COUNTER_INCR(sc, sc_ev_rxfull);
 #ifdef GEM_DEBUG
 			if (ifp->if_flags & IFF_DEBUG)
 				printf("%s: rint: ring wrap\n",
 				    device_xname(&sc->sc_dev));
 #endif
+		}
 		sc->sc_rxptr = i;
 		bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
+	}
 #ifdef GEM_COUNTERS
 	if (progress <= 4) {
 		GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]);
 	} else if (progress < 32) {
 		if (progress < 16)
 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]);
 		else
 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]);
 	} else {
 		if (progress < 64)
 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]);
 		else
 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]);
+	}
 #endif
 	DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n",
 		sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)));
 	/* Read error counters ... */
 	ifp->if_ierrors +=
 	    bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) +
 	    bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) +
 	    bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) +
 	    bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL);
 	/* ... then clear the hardware counters. */
 	bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
 	bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
 	bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
 	bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
 	return (1);
+}
 /*
  * gem_add_rxbuf:
+ *
  *	Add a receive buffer to the indicated descriptor.
  */
 int
 gem_add_rxbuf(struct gem_softc *sc, int idx)
+{
 	struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
 	struct mbuf *m;
 	int error;
 	MGETHDR(m, M_DONTWAIT, MT_DATA);
 	if (m == NULL)
 		return (ENOBUFS);
 	MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner);
 	MCLGET(m, M_DONTWAIT);
 	if ((m->m_flags & M_EXT) == 0) {
 		m_freem(m);
 		return (ENOBUFS);
+	}
 #ifdef GEM_DEBUG
 /* bzero the packet to check DMA */
 	memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
 #endif
 	if (rxs->rxs_mbuf != NULL)
 		bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap);
 	rxs->rxs_mbuf = m;
 	error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap,
 	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
 	if (error) {
 		aprint_error_dev(&sc->sc_dev, "can't load rx DMA map %d, error = %d\n",
 		    idx, error);
 		panic("gem_add_rxbuf");	/* XXX */
+	}
 	bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 	GEM_INIT_RXDESC(sc, idx);
 	return (0);
+}
 int
 gem_eint(struct gem_softc *sc, u_int status)
+{
 	char bits[128];
 	u_int32_t r, v;
 	if ((status & GEM_INTR_MIF) != 0) {
 		printf("%s: XXXlink status changed\n", device_xname(&sc->sc_dev));
 		return (1);
+	}
 	if ((status & GEM_INTR_RX_TAG_ERR) != 0) {
 		gem_reset_rxdma(sc);
 		return (1);
+	}
 	if (status & GEM_INTR_BERR) {
 		if (sc->sc_flags & GEM_PCI)
 			r = GEM_ERROR_STATUS;
 		else
 			r = GEM_SBUS_ERROR_STATUS;
 		bus_space_read_4(sc->sc_bustag, sc->sc_h2, r);
 		v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r);
 		aprint_error_dev(&sc->sc_dev, "bus error interrupt: 0x%02x\n",
 		    v);
 		return (1);
+	}
 	snprintb(bits, sizeof(bits), GEM_INTR_BITS, status);
 	printf("%s: status=%s\n", device_xname(&sc->sc_dev), bits);
 	return (1);
+}
 /*
  * PCS interrupts.
  * We should receive these when the link status changes, but sometimes
  * we don't receive them for link up.  We compensate for this in the
  * gem_tick() callout.
  */
 int
 gem_pint(struct gem_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	u_int32_t v, v2;
 	/*
 	 * Clear the PCS interrupt from GEM_STATUS.  The PCS register is
 	 * latched, so we have to read it twice.  There is only one bit in
 	 * use, so the value is meaningless.
 	 */
 	bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS);
 	bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS);
 	if ((ifp->if_flags & IFF_UP) == 0)
 		return 1;
 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0)
 		return 1;
 	v = bus_space_read_4(t, h, GEM_MII_STATUS);
 	/* If we see remote fault, our link partner is probably going away */
 	if ((v & GEM_MII_STATUS_REM_FLT) != 0) {
 		gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0);
 		v = bus_space_read_4(t, h, GEM_MII_STATUS);
 	/* Otherwise, we may need to wait after auto-negotiation completes */
 	} else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) ==
 	    GEM_MII_STATUS_ANEG_CPT) {
 		gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS);
 		v = bus_space_read_4(t, h, GEM_MII_STATUS);
+	}
 	if ((v & GEM_MII_STATUS_LINK_STS) != 0) {
 		if (sc->sc_flags & GEM_LINK) {
 			return 1;
+		}
 		callout_stop(&sc->sc_tick_ch);
 		v = bus_space_read_4(t, h, GEM_MII_ANAR);
 		v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR);
 		sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX;
 		sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE;
 		v &= v2;
 		if (v & GEM_MII_ANEG_FUL_DUPLX) {
 			sc->sc_mii.mii_media_active |= IFM_FDX;
 #ifdef GEM_DEBUG
 			aprint_debug_dev(&sc->sc_dev, "link up: full duplex\n");
 #endif
 		} else if (v & GEM_MII_ANEG_HLF_DUPLX) {
 			sc->sc_mii.mii_media_active |= IFM_HDX;
 #ifdef GEM_DEBUG
 			aprint_debug_dev(&sc->sc_dev, "link up: half duplex\n");
 #endif
 		} else {
 #ifdef GEM_DEBUG
 			aprint_debug_dev(&sc->sc_dev, "duplex mismatch\n");
 #endif
+		}
 		gem_statuschange(sc);
 	} else {
 		if ((sc->sc_flags & GEM_LINK) == 0) {
 			return 1;
+		}
 		sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE;
 		sc->sc_mii.mii_media_status = IFM_AVALID;
 #ifdef GEM_DEBUG
 			aprint_debug_dev(&sc->sc_dev, "link down\n");
 #endif
 		gem_statuschange(sc);
 		/* Start the 10 second timer */
 		callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc);
+	}
 	return 1;
+}
 int
 gem_intr(void *v)
+{
 	struct gem_softc *sc = (struct gem_softc *)v;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	u_int32_t status;
 	int r = 0;
 #ifdef GEM_DEBUG
 	char bits[128];
 #endif
 	/* XXX We should probably mask out interrupts until we're done */
 	sc->sc_ev_intr.ev_count++;
 	status = bus_space_read_4(t, h, GEM_STATUS);
 #ifdef GEM_DEBUG
 	snprintb(bits, sizeof(bits), GEM_INTR_BITS, status);
 #endif
 	DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n",
 		device_xname(&sc->sc_dev), (status >> 19), bits));
 	if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
 		r |= gem_eint(sc, status);
 	/* We don't bother with GEM_INTR_TX_DONE */
 	if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) {
 		GEM_COUNTER_INCR(sc, sc_ev_txint);
 		r |= gem_tint(sc);
+	}
 	if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) {
 		GEM_COUNTER_INCR(sc, sc_ev_rxint);
 		r |= gem_rint(sc);
+	}
 	/* We should eventually do more than just print out error stats. */
 	if (status & GEM_INTR_TX_MAC) {
 		int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS);
 		if (txstat & ~GEM_MAC_TX_XMIT_DONE)
 			printf("%s: MAC tx fault, status %x\n",
 			    device_xname(&sc->sc_dev), txstat);
 		if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
 			gem_init(ifp);
+	}
 	if (status & GEM_INTR_RX_MAC) {
 		int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS);
 		/*
 		 * At least with GEM_SUN_GEM and some GEM_SUN_ERI
 		 * revisions GEM_MAC_RX_OVERFLOW happen often due to a
 		 * silicon bug so handle them silently. Moreover, it's
 		 * likely that the receiver has hung so we reset it.
 		 */
 		if (rxstat & GEM_MAC_RX_OVERFLOW) {
 			ifp->if_ierrors++;
 			gem_reset_rxdma(sc);
 		} else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
 			printf("%s: MAC rx fault, status 0x%02x\n",
 			    device_xname(&sc->sc_dev), rxstat);
+	}
 	if (status & GEM_INTR_PCS) {
 		r |= gem_pint(sc);
+	}
 /* Do we need to do anything with these?
 	if ((status & GEM_MAC_CONTROL_STATUS) != 0) {
 		status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS);
 		if ((status2 & GEM_MAC_PAUSED) != 0)
 			aprintf_debug_dev(&sc->sc_dev, "PAUSE received (%d slots)\n",
 			    GEM_MAC_PAUSE_TIME(status2));
 		if ((status2 & GEM_MAC_PAUSE) != 0)
 			aprintf_debug_dev(&sc->sc_dev, "transited to PAUSE state\n");
 		if ((status2 & GEM_MAC_RESUME) != 0)
 			aprintf_debug_dev(&sc->sc_dev, "transited to non-PAUSE state\n");
+	}
 	if ((status & GEM_INTR_MIF) != 0)
 		aprintf_debug_dev(&sc->sc_dev, "MIF interrupt\n");
 */
 #if NRND > 0
 	rnd_add_uint32(&sc->rnd_source, status);
 #endif
 	return (r);
+}
 void
 gem_watchdog(struct ifnet *ifp)
+{
 	struct gem_softc *sc = ifp->if_softc;
 	DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
 		"GEM_MAC_RX_CONFIG %x\n",
 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG),
 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS),
 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG)));
 	log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev));
 	++ifp->if_oerrors;
 	/* Try to get more packets going. */
 	gem_start(ifp);
+}
 /*
  * Initialize the MII Management Interface
  */
 void
 gem_mifinit(struct gem_softc *sc)
+{
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mif = sc->sc_h1;
 	/* Configure the MIF in frame mode */
 	sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
 	sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
 	bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config);
+}
 /*
  * MII interface
+ *
  * The GEM MII interface supports at least three different operating modes:
+ *
  * Bitbang mode is implemented using data, clock and output enable registers.
+ *
  * Frame mode is implemented by loading a complete frame into the frame
  * register and polling the valid bit for completion.
+ *
  * Polling mode uses the frame register but completion is indicated by
  * an interrupt.
+ *
  */
 static int
 gem_mii_readreg(struct device *self, int phy, int reg)
+{
 	struct gem_softc *sc = (void *)self;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mif = sc->sc_h1;
 	int n;
 	u_int32_t v;
 #ifdef GEM_DEBUG1
 	if (sc->sc_debug)
 		printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg);
 #endif
 	/* Construct the frame command */
 	v = (reg << GEM_MIF_REG_SHIFT)	| (phy << GEM_MIF_PHY_SHIFT) |
 		GEM_MIF_FRAME_READ;
 	bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
 	for (n = 0; n < 100; n++) {
 		DELAY(1);
 		v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
 		if (v & GEM_MIF_FRAME_TA0)
 			return (v & GEM_MIF_FRAME_DATA);
+	}
 	printf("%s: mii_read timeout\n", device_xname(&sc->sc_dev));
 	return (0);
+}
 static void
 gem_mii_writereg(struct device *self, int phy, int reg, int val)
+{
 	struct gem_softc *sc = (void *)self;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mif = sc->sc_h1;
 	int n;
 	u_int32_t v;
 #ifdef GEM_DEBUG1
 	if (sc->sc_debug)
 		printf("gem_mii_writereg: PHY %d reg %d val %x\n",
 			phy, reg, val);
 #endif
 	/* Construct the frame command */
 	v = GEM_MIF_FRAME_WRITE			|
 	    (phy << GEM_MIF_PHY_SHIFT)		|
 	    (reg << GEM_MIF_REG_SHIFT)		|
 	    (val & GEM_MIF_FRAME_DATA);
 	bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
 	for (n = 0; n < 100; n++) {
 		DELAY(1);
 		v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
 		if (v & GEM_MIF_FRAME_TA0)
 			return;
+	}
 	printf("%s: mii_write timeout\n", device_xname(&sc->sc_dev));
+}
 static void
 gem_mii_statchg(struct device *dev)
+{
 	struct gem_softc *sc = (void *)dev;
 #ifdef GEM_DEBUG
 	int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
 #endif
 #ifdef GEM_DEBUG
 	if (sc->sc_debug)
 		printf("gem_mii_statchg: status change: phy = %d\n",
 			sc->sc_phys[instance]);
 #endif
 	gem_statuschange(sc);
+}
 /*
  * Common status change for gem_mii_statchg() and gem_pint()
  */
 void
 gem_statuschange(struct gem_softc* sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mac = sc->sc_h1;
 	int gigabit;
 	u_int32_t rxcfg, txcfg, v;
 	if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 &&
 	    IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE)
 		sc->sc_flags |= GEM_LINK;
 	else
 		sc->sc_flags &= ~GEM_LINK;
 	if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000))
 		gigabit = 1;
 	else
 		gigabit = 0;
 	/*
 	 * The configuration done here corresponds to the steps F) and
 	 * G) and as far as enabling of RX and TX MAC goes also step H)
 	 * of the initialization sequence outlined in section 3.2.1 of
 	 * the GEM Gigabit Ethernet ASIC Specification.
 	 */
 	rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG);
 	rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE);
 	txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT;
 	if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
 		txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS;
 	else if (gigabit) {
 		rxcfg |= GEM_MAC_RX_CARR_EXTEND;
 		txcfg |= GEM_MAC_RX_CARR_EXTEND;
+	}
 	bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0);
 	bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4,
 	    BUS_SPACE_BARRIER_WRITE);
 	if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0))
 		aprint_normal_dev(&sc->sc_dev, "cannot disable TX MAC\n");
 	bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg);
 	bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0);
 	bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4,
 	    BUS_SPACE_BARRIER_WRITE);
 	if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
 		aprint_normal_dev(&sc->sc_dev, "cannot disable RX MAC\n");
 	bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg);
 	v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) &
 	    ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE);
 	bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v);
 	if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 &&
 	    gigabit != 0)
 		bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME,
 		    GEM_MAC_SLOT_TIME_CARR_EXTEND);
 	else
 		bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME,
 		    GEM_MAC_SLOT_TIME_NORMAL);
 	/* XIF Configuration */
 	if (sc->sc_flags & GEM_LINK)
 		v = GEM_MAC_XIF_LINK_LED;
 	else
 		v = 0;
 	v |= GEM_MAC_XIF_TX_MII_ENA;
 	/* If an external transceiver is connected, enable its MII drivers */
 	sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
 	if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) {
 		if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
 			/* External MII needs echo disable if half duplex. */
 			if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) &
 			    IFM_FDX) != 0)
 				/* turn on full duplex LED */
 				v |= GEM_MAC_XIF_FDPLX_LED;
 			else
 				/* half duplex -- disable echo */
 				v |= GEM_MAC_XIF_ECHO_DISABL;
 			if (gigabit)
 				v |= GEM_MAC_XIF_GMII_MODE;
 			else
 				v &= ~GEM_MAC_XIF_GMII_MODE;
 		} else
 			/* Internal MII needs buf enable */
 			v |= GEM_MAC_XIF_MII_BUF_ENA;
 	} else {
 		if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
 			v |= GEM_MAC_XIF_FDPLX_LED;
 		v |= GEM_MAC_XIF_GMII_MODE;
+	}
 	bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v);
 	if ((ifp->if_flags & IFF_RUNNING) != 0 &&
 	    (sc->sc_flags & GEM_LINK) != 0) {
 		bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG,
 		    txcfg | GEM_MAC_TX_ENABLE);
 		bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG,
 		    rxcfg | GEM_MAC_RX_ENABLE);
+	}
+}
 int
 gem_ser_mediachange(struct ifnet *ifp)
+{
 	struct gem_softc *sc = ifp->if_softc;
 	u_int s, t;
 	if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER)
 		return EINVAL;
 	s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media);
 	if (s == IFM_AUTO) {
 		if (sc->sc_mii_media != s) {
 #ifdef GEM_DEBUG
 			aprint_debug_dev(&sc->sc_dev, "setting media to auto\n");
 #endif
 			sc->sc_mii_media = s;
 			if (ifp->if_flags & IFF_UP) {
 				gem_pcs_stop(sc, 0);
 				gem_pcs_start(sc);
+			}
+		}
 		return 0;
+	}
 	if (s == IFM_1000_SX) {
 		t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media);
 		if (t == IFM_FDX || t == IFM_HDX) {
 			if (sc->sc_mii_media != t) {
 				sc->sc_mii_media = t;
 #ifdef GEM_DEBUG
 				aprint_debug_dev(&sc->sc_dev,
 				    "setting media to 1000baseSX-%s\n",
 				    t == IFM_FDX ? "FDX" : "HDX");
 #endif
 				if (ifp->if_flags & IFF_UP) {
 					gem_pcs_stop(sc, 0);
 					gem_pcs_start(sc);
+				}
+			}
 			return 0;
+		}
+	}
 	return EINVAL;
+}
 void
 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
 	struct gem_softc *sc = ifp->if_softc;
 	if ((ifp->if_flags & IFF_UP) == 0)
 		return;
 	ifmr->ifm_active = sc->sc_mii.mii_media_active;
 	ifmr->ifm_status = sc->sc_mii.mii_media_status;
+}
 static int
 gem_ifflags_cb(struct ethercom *ec)
+{
 	struct ifnet *ifp = &ec->ec_if;
 	struct gem_softc *sc = ifp->if_softc;
 	int change = ifp->if_flags ^ sc->sc_if_flags;
 	if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0)
 		return ENETRESET;
 	else if ((change & IFF_PROMISC) != 0)
 		gem_setladrf(sc);
 	return 0;
+}
 /*
  * Process an ioctl request.
  */
 int
 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data)
+{
 	struct gem_softc *sc = ifp->if_softc;
 	int s, error = 0;
 	s = splnet();
 	if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
 		error = 0;
 		if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
+			;
 		else if (ifp->if_flags & IFF_RUNNING) {
 			/*
 			 * Multicast list has changed; set the hardware filter
 			 * accordingly.
 			 */
 			gem_setladrf(sc);
+		}
+	}
 	/* Try to get things going again */
 	if (ifp->if_flags & IFF_UP)
 		gem_start(ifp);
 	splx(s);
 	return (error);
+}
 void
 gem_shutdown(void *arg)
+{
 	struct gem_softc *sc = (struct gem_softc *)arg;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	gem_stop(ifp, 1);
+}
 /*
  * Set up the logical address filter.
  */
 void
 gem_setladrf(struct gem_softc *sc)
+{
 	struct ethercom *ec = &sc->sc_ethercom;
 	struct ifnet *ifp = &ec->ec_if;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t h = sc->sc_h1;
 	u_int32_t crc;
 	u_int32_t hash[16];
 	u_int32_t v;
 	int i;
 	/* Get current RX configuration */
 	v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
 	/*
 	 * Turn off promiscuous mode, promiscuous group mode (all multicast),
 	 * and hash filter.  Depending on the case, the right bit will be
 	 * enabled.
 	 */
 	v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
 	    GEM_MAC_RX_PROMISC_GRP);
 	if ((ifp->if_flags & IFF_PROMISC) != 0) {
 		/* Turn on promiscuous mode */
 		v |= GEM_MAC_RX_PROMISCUOUS;
 		ifp->if_flags |= IFF_ALLMULTI;
 		goto chipit;
+	}
 	/*
 	 * Set up multicast address filter by passing all multicast addresses
 	 * through a crc generator, and then using the high order 8 bits as an
 	 * index into the 256 bit logical address filter.  The high order 4
 	 * bits selects the word, while the other 4 bits select the bit within
 	 * the word (where bit 0 is the MSB).
 	 */
 	/* Clear hash table */
 	memset(hash, 0, sizeof(hash));
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 			/*
 			 * We must listen to a range of multicast addresses.
 			 * For now, just accept all multicasts, rather than
 			 * trying to set only those filter bits needed to match
 			 * the range.  (At this time, the only use of address
 			 * ranges is for IP multicast routing, for which the
 			 * range is big enough to require all bits set.)
 			 * XXX should use the address filters for this
 			 */
 			ifp->if_flags |= IFF_ALLMULTI;
 			v |= GEM_MAC_RX_PROMISC_GRP;
 			goto chipit;
+		}
 		/* Get the LE CRC32 of the address */
 		crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo));
 		/* Just want the 8 most significant bits. */
 		crc >>= 24;
 		/* Set the corresponding bit in the filter. */
 		hash[crc >> 4] |= 1 << (15 - (crc & 15));
 		ETHER_NEXT_MULTI(step, enm);
+	}
 	v |= GEM_MAC_RX_HASH_FILTER;
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	/* Now load the hash table into the chip (if we are using it) */
 	for (i = 0; i < 16; i++) {
 		bus_space_write_4(t, h,
 		    GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
 		    hash[i]);
+	}
 chipit:
 	sc->sc_if_flags = ifp->if_flags;
 	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
+}
 #if notyet
 /*
  * gem_power:
+ *
  *	Power management (suspend/resume) hook.
  */
 void
 gem_power(int why, void *arg)
+{
 	struct gem_softc *sc = arg;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	int s;
 	s = splnet();
 	switch (why) {
 	case PWR_SUSPEND:
 	case PWR_STANDBY:
 		gem_stop(ifp, 1);
 		if (sc->sc_power != NULL)
 			(*sc->sc_power)(sc, why);
 		break;
 	case PWR_RESUME:
 		if (ifp->if_flags & IFF_UP) {
 			if (sc->sc_power != NULL)
 				(*sc->sc_power)(sc, why);
 			gem_init(ifp);
+		}
 		break;
 	case PWR_SOFTSUSPEND:
 	case PWR_SOFTSTANDBY:
 	case PWR_SOFTRESUME:
 		break;
+	}
 	splx(s);
+}
 #endif

 @@ -1,1605 +1,1604 @@
-/*	$NetBSD: hme.c,v 1.72 2009/03/14 21:04:20 dsl Exp $	*/
+/*	$NetBSD: hme.c,v 1.73 2009/03/16 12:02:00 tsutsui Exp $	*/
 /*-
  * Copyright (c) 1999 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Paul Kranenburg.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * HME Ethernet module driver.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.72 2009/03/14 21:04:20 dsl Exp $");
+__KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.73 2009/03/16 12:02:00 tsutsui Exp $");
 /* #define HMEDEBUG */
 #include "opt_inet.h"
 #include "bpfilter.h"
 #include "rnd.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/mbuf.h>
 #include <sys/syslog.h>
 #include <sys/socket.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #if NRND > 0
 #include <sys/rnd.h>
 #endif
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_ether.h>
 #include <net/if_media.h>
 #ifdef INET
 #include <netinet/in.h>
 #include <netinet/if_inarp.h>
 #include <netinet/in_systm.h>
 #include <netinet/in_var.h>
 #include <netinet/ip.h>
 #include <netinet/tcp.h>
 #include <netinet/udp.h>
 #endif
 #if NBPFILTER > 0
 #include <net/bpf.h>
 #include <net/bpfdesc.h>
 #endif
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <sys/bus.h>
 #include <dev/ic/hmereg.h>
 #include <dev/ic/hmevar.h>
 void		hme_start(struct ifnet *);
 void		hme_stop(struct hme_softc *,bool);
 int		hme_ioctl(struct ifnet *, u_long, void *);
 void		hme_tick(void *);
 void		hme_watchdog(struct ifnet *);
 void		hme_shutdown(void *);
 int		hme_init(struct hme_softc *);
 void		hme_meminit(struct hme_softc *);
 void		hme_mifinit(struct hme_softc *);
 void		hme_reset(struct hme_softc *);
 void		hme_setladrf(struct hme_softc *);
 /* MII methods & callbacks */
 static int	hme_mii_readreg(struct device *, int, int);
 static void	hme_mii_writereg(struct device *, int, int, int);
 static void	hme_mii_statchg(struct device *);
 int		hme_mediachange(struct ifnet *);
 struct mbuf	*hme_get(struct hme_softc *, int, uint32_t);
 int		hme_put(struct hme_softc *, int, struct mbuf *);
 void		hme_read(struct hme_softc *, int, uint32_t);
 int		hme_eint(struct hme_softc *, u_int);
 int		hme_rint(struct hme_softc *);
 int		hme_tint(struct hme_softc *);
 /* Default buffer copy routines */
 void	hme_copytobuf_contig(struct hme_softc *, void *, int, int);
 void	hme_copyfrombuf_contig(struct hme_softc *, void *, int, int);
 void	hme_zerobuf_contig(struct hme_softc *, int, int);
 void
 hme_config(struct hme_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct mii_data *mii = &sc->sc_mii;
 	struct mii_softc *child;
 	bus_dma_tag_t dmatag = sc->sc_dmatag;
 	bus_dma_segment_t seg;
 	bus_size_t size;
 	int rseg, error;
 	/*
 	 * HME common initialization.
+	 *
 	 * hme_softc fields that must be initialized by the front-end:
+	 *
 	 * the bus tag:
 	 *	sc_bustag
+	 *
 	 * the DMA bus tag:
 	 *	sc_dmatag
+	 *
 	 * the bus handles:
 	 *	sc_seb		(Shared Ethernet Block registers)
 	 *	sc_erx		(Receiver Unit registers)
 	 *	sc_etx		(Transmitter Unit registers)
 	 *	sc_mac		(MAC registers)
 	 *	sc_mif		(Management Interface registers)
+	 *
 	 * the maximum bus burst size:
 	 *	sc_burst
+	 *
 	 * (notyet:DMA capable memory for the ring descriptors & packet buffers:
 	 *	rb_membase, rb_dmabase)
+	 *
 	 * the local Ethernet address:
 	 *	sc_enaddr
+	 *
 	 */
 	/* Make sure the chip is stopped. */
 	hme_stop(sc, true);
 	/*
 	 * Allocate descriptors and buffers
 	 * XXX - do all this differently.. and more configurably,
 	 * eg. use things as `dma_load_mbuf()' on transmit,
 	 *     and a pool of `EXTMEM' mbufs (with buffers DMA-mapped
 	 *     all the time) on the receiver side.
+	 *
 	 * Note: receive buffers must be 64-byte aligned.
 	 * Also, apparently, the buffers must extend to a DMA burst
 	 * boundary beyond the maximum packet size.
 	 */
 #define _HME_NDESC	128
 #define _HME_BUFSZ	1600
 	/* Note: the # of descriptors must be a multiple of 16 */
 	sc->sc_rb.rb_ntbuf = _HME_NDESC;
 	sc->sc_rb.rb_nrbuf = _HME_NDESC;
 	/*
 	 * Allocate DMA capable memory
 	 * Buffer descriptors must be aligned on a 2048 byte boundary;
 	 * take this into account when calculating the size. Note that
 	 * the maximum number of descriptors (256) occupies 2048 bytes,
 	 * so we allocate that much regardless of _HME_NDESC.
 	 */
 	size =	2048 +					/* TX descriptors */
 +					/* RX descriptors */
 		sc->sc_rb.rb_ntbuf * _HME_BUFSZ +	/* TX buffers */
 		sc->sc_rb.rb_nrbuf * _HME_BUFSZ;	/* RX buffers */
 	/* Allocate DMA buffer */
 	if ((error = bus_dmamem_alloc(dmatag, size,
 , 0,
 				      &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(&sc->sc_dev, "DMA buffer alloc error %d\n",
 			error);
 		return;
+	}
 	/* Map DMA memory in CPU addressable space */
 	if ((error = bus_dmamem_map(dmatag, &seg, rseg, size,
 				    &sc->sc_rb.rb_membase,
 				    BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(&sc->sc_dev, "DMA buffer map error %d\n",
 			error);
 		bus_dmamap_unload(dmatag, sc->sc_dmamap);
 		bus_dmamem_free(dmatag, &seg, rseg);
 		return;
+	}
 	if ((error = bus_dmamap_create(dmatag, size, 1, size, 0,
 				    BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
 		aprint_error_dev(&sc->sc_dev, "DMA map create error %d\n",
 			error);
 		return;
+	}
 	/* Load the buffer */
 	if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap,
 	    sc->sc_rb.rb_membase, size, NULL,
 	    BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(&sc->sc_dev, "DMA buffer map load error %d\n",
 			error);
 		bus_dmamem_free(dmatag, &seg, rseg);
 		return;
+	}
 	sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
 	printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev),
 	    ether_sprintf(sc->sc_enaddr));
 	/* Initialize ifnet structure. */
 	strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ);
 	ifp->if_softc = sc;
 	ifp->if_start = hme_start;
 	ifp->if_ioctl = hme_ioctl;
 	ifp->if_watchdog = hme_watchdog;
 	ifp->if_flags =
 	    IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
 	sc->sc_if_flags = ifp->if_flags;
 	ifp->if_capabilities |=
 	    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
 	    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
 	IFQ_SET_READY(&ifp->if_snd);
 	/* Initialize ifmedia structures and MII info */
 	mii->mii_ifp = ifp;
 	mii->mii_readreg = hme_mii_readreg;
 	mii->mii_writereg = hme_mii_writereg;
 	mii->mii_statchg = hme_mii_statchg;
 	sc->sc_ethercom.ec_mii = mii;
 	ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus);
 	hme_mifinit(sc);
 	mii_attach(&sc->sc_dev, mii, 0xffffffff,
 			MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG);
 	child = LIST_FIRST(&mii->mii_phys);
 	if (child == NULL) {
 		/* No PHY attached */
 		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL);
 	} else {
 		/*
 		 * Walk along the list of attached MII devices and
 		 * establish an `MII instance' to `phy number'
 		 * mapping. We'll use this mapping in media change
 		 * requests to determine which phy to use to program
 		 * the MIF configuration register.
 		 */
 		for (; child != NULL; child = LIST_NEXT(child, mii_list)) {
 			/*
 			 * Note: we support just two PHYs: the built-in
 			 * internal device and an external on the MII
 			 * connector.
 			 */
 			if (child->mii_phy > 1 || child->mii_inst > 1) {
 				aprint_error_dev(&sc->sc_dev, "cannot accommodate MII device %s"
 				       " at phy %d, instance %d\n",
 				       device_xname(child->mii_dev),
 				       child->mii_phy, child->mii_inst);
 				continue;
+			}
 			sc->sc_phys[child->mii_inst] = child->mii_phy;
+		}
 		/*
 		 * XXX - we can really do the following ONLY if the
 		 * phy indeed has the auto negotiation capability!!
 		 */
 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
+	}
 	/* claim 802.1q capability */
 	sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
 	/* Attach the interface. */
 	if_attach(ifp);
 	ether_ifattach(ifp, sc->sc_enaddr);
 	sc->sc_sh = shutdownhook_establish(hme_shutdown, sc);
 	if (sc->sc_sh == NULL)
 		panic("hme_config: can't establish shutdownhook");
 #if NRND > 0
 	rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev),
 			  RND_TYPE_NET, 0);
 #endif
 	callout_init(&sc->sc_tick_ch, 0);
+}
 void
 hme_tick(void *arg)
+{
 	struct hme_softc *sc = arg;
 	int s;
 	s = splnet();
 	mii_tick(&sc->sc_mii);
 	splx(s);
 	callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc);
+}
 void
 hme_reset(struct hme_softc *sc)
+{
 	int s;
 	s = splnet();
 	(void)hme_init(sc);
 	splx(s);
+}
 void
 hme_stop(struct hme_softc *sc, bool chip_only)
+{
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t seb = sc->sc_seb;
 	int n;
 	if (!chip_only) {
 		callout_stop(&sc->sc_tick_ch);
 		mii_down(&sc->sc_mii);
+	}
 	/* Mask all interrupts */
 	bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff);
 	/* Reset transmitter and receiver */
 	bus_space_write_4(t, seb, HME_SEBI_RESET,
 			  (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX));
 	for (n = 0; n < 20; n++) {
 		u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET);
 		if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0)
 			return;
 		DELAY(20);
+	}
 	printf("%s: hme_stop: reset failed\n", device_xname(&sc->sc_dev));
+}
 void
 hme_meminit(struct hme_softc *sc)
+{
 	bus_addr_t txbufdma, rxbufdma;
 	bus_addr_t dma;
 	char *p;
 	unsigned int ntbuf, nrbuf, i;
 	struct hme_ring *hr = &sc->sc_rb;
 	p = hr->rb_membase;
 	dma = hr->rb_dmabase;
 	ntbuf = hr->rb_ntbuf;
 	nrbuf = hr->rb_nrbuf;
 	/*
 	 * Allocate transmit descriptors
 	 */
 	hr->rb_txd = p;
 	hr->rb_txddma = dma;
 	p += ntbuf * HME_XD_SIZE;
 	dma += ntbuf * HME_XD_SIZE;
 	/* We have reserved descriptor space until the next 2048 byte boundary.*/
 	dma = (bus_addr_t)roundup((u_long)dma, 2048);
 	p = (void *)roundup((u_long)p, 2048);
 	/*
 	 * Allocate receive descriptors
 	 */
 	hr->rb_rxd = p;
 	hr->rb_rxddma = dma;
 	p += nrbuf * HME_XD_SIZE;
 	dma += nrbuf * HME_XD_SIZE;
 	/* Again move forward to the next 2048 byte boundary.*/
 	dma = (bus_addr_t)roundup((u_long)dma, 2048);
 	p = (void *)roundup((u_long)p, 2048);
 	/*
 	 * Allocate transmit buffers
 	 */
 	hr->rb_txbuf = p;
 	txbufdma = dma;
 	p += ntbuf * _HME_BUFSZ;
 	dma += ntbuf * _HME_BUFSZ;
 	/*
 	 * Allocate receive buffers
 	 */
 	hr->rb_rxbuf = p;
 	rxbufdma = dma;
 	p += nrbuf * _HME_BUFSZ;
 	dma += nrbuf * _HME_BUFSZ;
 	/*
 	 * Initialize transmit buffer descriptors
 	 */
 	for (i = 0; i < ntbuf; i++) {
 		HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ);
 		HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0);
+	}
 	/*
 	 * Initialize receive buffer descriptors
 	 */
 	for (i = 0; i < nrbuf; i++) {
 		HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ);
 		HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i,
 				HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ));
+	}
 	hr->rb_tdhead = hr->rb_tdtail = 0;
 	hr->rb_td_nbusy = 0;
 	hr->rb_rdtail = 0;
+}
 /*
  * Initialization of interface; set up initialization block
  * and transmit/receive descriptor rings.
  */
 int
 hme_init(struct hme_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t seb = sc->sc_seb;
 	bus_space_handle_t etx = sc->sc_etx;
 	bus_space_handle_t erx = sc->sc_erx;
 	bus_space_handle_t mac = sc->sc_mac;
 	u_int8_t *ea;
 	u_int32_t v;
 	int rc;
 	/*
 	 * Initialization sequence. The numbered steps below correspond
 	 * to the sequence outlined in section 6.3.5.1 in the Ethernet
 	 * Channel Engine manual (part of the PCIO manual).
 	 * See also the STP2002-STQ document from Sun Microsystems.
 	 */
 	/* step 1 & 2. Reset the Ethernet Channel */
 	hme_stop(sc, false);
 	/* Re-initialize the MIF */
 	hme_mifinit(sc);
 	/* Call MI reset function if any */
 	if (sc->sc_hwreset)
 		(*sc->sc_hwreset)(sc);
 #if 0
 	/* Mask all MIF interrupts, just in case */
 	bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff);
 #endif
 	/* step 3. Setup data structures in host memory */
 	hme_meminit(sc);
 	/* step 4. TX MAC registers & counters */
 	bus_space_write_4(t, mac, HME_MACI_NCCNT, 0);
 	bus_space_write_4(t, mac, HME_MACI_FCCNT, 0);
 	bus_space_write_4(t, mac, HME_MACI_EXCNT, 0);
 	bus_space_write_4(t, mac, HME_MACI_LTCNT, 0);
 	bus_space_write_4(t, mac, HME_MACI_TXSIZE,
 	    (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
 	    ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN);
 	sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable;
 	/* Load station MAC address */
 	ea = sc->sc_enaddr;
 	bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]);
 	bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]);
 	bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]);
 	/*
 	 * Init seed for backoff
 	 * (source suggested by manual: low 10 bits of MAC address)
 	 */
 	v = ((ea[4] << 8) | ea[5]) & 0x3fff;
 	bus_space_write_4(t, mac, HME_MACI_RANDSEED, v);
 	/* Note: Accepting power-on default for other MAC registers here.. */
 	/* step 5. RX MAC registers & counters */
 	hme_setladrf(sc);
 	/* step 6 & 7. Program Descriptor Ring Base Addresses */
 	bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma);
 	bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf);
 	bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma);
 	bus_space_write_4(t, mac, HME_MACI_RXSIZE,
 	    (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
 	    ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN);
 	/* step 8. Global Configuration & Interrupt Mask */
 	bus_space_write_4(t, seb, HME_SEBI_IMASK,
 			~(
 			  /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/
 			  HME_SEB_STAT_HOSTTOTX |
 			  HME_SEB_STAT_RXTOHOST |
 			  HME_SEB_STAT_TXALL |
 			  HME_SEB_STAT_TXPERR |
 			  HME_SEB_STAT_RCNTEXP |
 			  /*HME_SEB_STAT_MIFIRQ |*/
 			  HME_SEB_STAT_ALL_ERRORS ));
 	switch (sc->sc_burst) {
 	default:
 		v = 0;
 		break;
 	case 16:
 		v = HME_SEB_CFG_BURST16;
 		break;
 	case 32:
 		v = HME_SEB_CFG_BURST32;
 		break;
 	case 64:
 		v = HME_SEB_CFG_BURST64;
 		break;
+	}
 	bus_space_write_4(t, seb, HME_SEBI_CFG, v);
 	/* step 9. ETX Configuration: use mostly default values */
 	/* Enable DMA */
 	v = bus_space_read_4(t, etx, HME_ETXI_CFG);
 	v |= HME_ETX_CFG_DMAENABLE;
 	bus_space_write_4(t, etx, HME_ETXI_CFG, v);
 	/* Transmit Descriptor ring size: in increments of 16 */
 	bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1);
 	/* step 10. ERX Configuration */
 	v = bus_space_read_4(t, erx, HME_ERXI_CFG);
 	/* Encode Receive Descriptor ring size: four possible values */
 	switch (_HME_NDESC /*XXX*/) {
 	case 32:
 		v |= HME_ERX_CFG_RINGSIZE32;
 		break;
 	case 64:
 		v |= HME_ERX_CFG_RINGSIZE64;
 		break;
 	case 128:
 		v |= HME_ERX_CFG_RINGSIZE128;
 		break;
 	case 256:
 		v |= HME_ERX_CFG_RINGSIZE256;
 		break;
 	default:
 		printf("hme: invalid Receive Descriptor ring size\n");
 		break;
+	}
 	/* Enable DMA */
 	v |= HME_ERX_CFG_DMAENABLE;
 	/* set h/w rx checksum start offset (# of half-words) */
 #ifdef INET
 	v |= (((ETHER_HDR_LEN + sizeof(struct ip) +
 		((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
 		ETHER_VLAN_ENCAP_LEN : 0)) / 2) << HME_ERX_CFG_CSUMSHIFT) &
 		HME_ERX_CFG_CSUMSTART;
 #endif
 	bus_space_write_4(t, erx, HME_ERXI_CFG, v);
 	/* step 11. XIF Configuration */
 	v = bus_space_read_4(t, mac, HME_MACI_XIF);
 	v |= HME_MAC_XIF_OE;
 	bus_space_write_4(t, mac, HME_MACI_XIF, v);
 	/* step 12. RX_MAC Configuration Register */
 	v = bus_space_read_4(t, mac, HME_MACI_RXCFG);
 	v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP;
 	bus_space_write_4(t, mac, HME_MACI_RXCFG, v);
 	/* step 13. TX_MAC Configuration Register */
 	v = bus_space_read_4(t, mac, HME_MACI_TXCFG);
 	v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP);
 	bus_space_write_4(t, mac, HME_MACI_TXCFG, v);
 	/* step 14. Issue Transmit Pending command */
 	/* Call MI initialization function if any */
 	if (sc->sc_hwinit)
 		(*sc->sc_hwinit)(sc);
 	/* Set the current media. */
 	if ((rc = hme_mediachange(ifp)) != 0)
 		return rc;
 	/* Start the one second timer. */
 	callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc);
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	sc->sc_if_flags = ifp->if_flags;
 	ifp->if_timer = 0;
 	hme_start(ifp);
 	return 0;
+}
 /*
  * Routine to copy from mbuf chain to transmit buffer in
  * network buffer memory.
  * Returns the amount of data copied.
  */
 int
 hme_put(struct hme_softc *sc, int ri, struct mbuf *m)
 	/* ri:			 Ring index */
+{
 	struct mbuf *n;
 	int len, tlen = 0;
 	char *bp;
 	bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ;
 	for (; m; m = n) {
 		len = m->m_len;
 		if (len == 0) {
 			MFREE(m, n);
 			continue;
+		}
 		memcpy(bp, mtod(m, void *), len);
 		bp += len;
 		tlen += len;
 		MFREE(m, n);
+	}
 	return (tlen);
+}
 /*
  * Pull data off an interface.
  * Len is length of data, with local net header stripped.
  * We copy the data into mbufs.  When full cluster sized units are present
  * we copy into clusters.
  */
 struct mbuf *
 hme_get(struct hme_softc *sc, int ri, u_int32_t flags)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct mbuf *m, *m0, *newm;
 	char *bp;
 	int len, totlen;
 	totlen = HME_XD_DECODE_RSIZE(flags);
 	MGETHDR(m0, M_DONTWAIT, MT_DATA);
 	if (m0 == 0)
 		return (0);
 	m0->m_pkthdr.rcvif = ifp;
 	m0->m_pkthdr.len = totlen;
 	len = MHLEN;
 	m = m0;
 	bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ;
 	while (totlen > 0) {
 		if (totlen >= MINCLSIZE) {
 			MCLGET(m, M_DONTWAIT);
 			if ((m->m_flags & M_EXT) == 0)
 				goto bad;
 			len = MCLBYTES;
+		}
 		if (m == m0) {
 			char *newdata = (char *)
 			    ALIGN(m->m_data + sizeof(struct ether_header)) -
 			    sizeof(struct ether_header);
 			len -= newdata - m->m_data;
 			m->m_data = newdata;
+		}
 		m->m_len = len = min(totlen, len);
 		memcpy(mtod(m, void *), bp, len);
 		bp += len;
 		totlen -= len;
 		if (totlen > 0) {
 			MGET(newm, M_DONTWAIT, MT_DATA);
 			if (newm == 0)
 				goto bad;
 			len = MLEN;
 			m = m->m_next = newm;
+		}
+	}
 #ifdef INET
 	/* hardware checksum */
 	if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) {
 		struct ether_header *eh;
 		struct ip *ip;
 		struct udphdr *uh;
 		uint16_t *opts;
 		int32_t hlen, pktlen;
 		uint32_t temp;
 		if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) {
 			pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN -
 				ETHER_VLAN_ENCAP_LEN;
 			eh = (struct ether_header *) mtod(m0, void *) +
 				ETHER_VLAN_ENCAP_LEN;
 		} else {
 			pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN;
 			eh = mtod(m0, struct ether_header *);
+		}
 		if (ntohs(eh->ether_type) != ETHERTYPE_IP)
 			goto swcsum;
 		ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN);
 		/* IPv4 only */
 		if (ip->ip_v != IPVERSION)
 			goto swcsum;
 		hlen = ip->ip_hl << 2;
 		if (hlen < sizeof(struct ip))
 			goto swcsum;
 		/*
 		 * bail if too short, has random trailing garbage, truncated,
 		 * fragment, or has ethernet pad.
 		 */
 		if ((ntohs(ip->ip_len) < hlen) || (ntohs(ip->ip_len) != pktlen)
 		    || (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)))
 			goto swcsum;
 		switch (ip->ip_p) {
 		case IPPROTO_TCP:
 			if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4))
 				goto swcsum;
 			if (pktlen < (hlen + sizeof(struct tcphdr)))
 				goto swcsum;
 			m0->m_pkthdr.csum_flags = M_CSUM_TCPv4;
 			break;
 		case IPPROTO_UDP:
 			if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4))
 				goto swcsum;
 			if (pktlen < (hlen + sizeof(struct udphdr)))
 				goto swcsum;
 			uh = (struct udphdr *)((char *)ip + hlen);
 			/* no checksum */
 			if (uh->uh_sum == 0)
 				goto swcsum;
 			m0->m_pkthdr.csum_flags = M_CSUM_UDPv4;
 			break;
 		default:
 			goto swcsum;
+		}
 		/* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */
 		m0->m_pkthdr.csum_data = (~flags) & HME_XD_RXCKSUM;
 		/* if the pkt had ip options, we have to deduct them */
 		if (hlen > sizeof(struct ip)) {
 			uint32_t optsum;
 			optsum = 0;
 			temp = hlen - sizeof(struct ip);
 			opts = (uint16_t *)((char *)ip + sizeof(struct ip));
 			while (temp > 1) {
 				optsum += ntohs(*opts++);
 				temp -= 2;
+			}
 			while (optsum >> 16)
 				optsum = (optsum >> 16) + (optsum & 0xffff);
-			/* Deduct the ip opts sum from the hwsum (rfc 1624). */
+			/* Deduct the ip opts sum from the hwsum. */
-			m0->m_pkthdr.csum_data = ~((~m0->m_pkthdr.csum_data) -
+			m0->m_pkthdr.csum_data += (uint16_t)~optsum;
 						   ~optsum);
 			while (m0->m_pkthdr.csum_data >> 16)
 				m0->m_pkthdr.csum_data =
 					(m0->m_pkthdr.csum_data >> 16) +
 					(m0->m_pkthdr.csum_data & 0xffff);
+		}
 		m0->m_pkthdr.csum_flags |= M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR;
 	} else
 swcsum:
 		m0->m_pkthdr.csum_flags = 0;
 #endif
 	return (m0);
 bad:
 	m_freem(m0);
 	return (0);
+}
 /*
  * Pass a packet to the higher levels.
  */
 void
 hme_read(struct hme_softc *sc, int ix, u_int32_t flags)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct mbuf *m;
 	int len;
 	len = HME_XD_DECODE_RSIZE(flags);
 	if (len <= sizeof(struct ether_header) ||
 	    len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
 	    ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) :
 	    ETHERMTU + sizeof(struct ether_header))) {
 #ifdef HMEDEBUG
 		printf("%s: invalid packet size %d; dropping\n",
 		    device_xname(&sc->sc_dev), len);
 #endif
 		ifp->if_ierrors++;
 		return;
+	}
 	/* Pull packet off interface. */
 	m = hme_get(sc, ix, flags);
 	if (m == 0) {
 		ifp->if_ierrors++;
 		return;
+	}
 	ifp->if_ipackets++;
 #if NBPFILTER > 0
 	/*
 	 * Check if there's a BPF listener on this interface.
 	 * If so, hand off the raw packet to BPF.
 	 */
 	if (ifp->if_bpf)
 		bpf_mtap(ifp->if_bpf, m);
 #endif
 	/* Pass the packet up. */
 	(*ifp->if_input)(ifp, m);
+}
 void
 hme_start(struct ifnet *ifp)
+{
 	struct hme_softc *sc = (struct hme_softc *)ifp->if_softc;
 	void *txd = sc->sc_rb.rb_txd;
 	struct mbuf *m;
 	unsigned int txflags;
 	unsigned int ri, len;
 	unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
 		return;
 	ri = sc->sc_rb.rb_tdhead;
 	for (;;) {
 		IFQ_DEQUEUE(&ifp->if_snd, m);
 		if (m == 0)
 			break;
 #if NBPFILTER > 0
 		/*
 		 * If BPF is listening on this interface, let it see the
 		 * packet before we commit it to the wire.
 		 */
 		if (ifp->if_bpf)
 			bpf_mtap(ifp->if_bpf, m);
 #endif
 #ifdef INET
 		/* collect bits for h/w csum, before hme_put frees the mbuf */
 		if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) &&
 		    m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) {
 			struct ether_header *eh;
 			uint16_t offset, start;
 			eh = mtod(m, struct ether_header *);
 			switch (ntohs(eh->ether_type)) {
 			case ETHERTYPE_IP:
 				start = ETHER_HDR_LEN;
 				break;
 			case ETHERTYPE_VLAN:
 				start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 				break;
 			default:
 				/* unsupported, drop it */
 				m_free(m);
 				continue;
+			}
 			start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data);
 			offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data)
 			    + start;
 			txflags = HME_XD_TXCKSUM |
 				  (offset << HME_XD_TXCSSTUFFSHIFT) |
 		  		  (start << HME_XD_TXCSSTARTSHIFT);
 		} else
 #endif
 			txflags = 0;
 		/*
 		 * Copy the mbuf chain into the transmit buffer.
 		 */
 		len = hme_put(sc, ri, m);
 		/*
 		 * Initialize transmit registers and start transmission
 		 */
 		HME_XD_SETFLAGS(sc->sc_pci, txd, ri,
 			HME_XD_OWN | HME_XD_SOP | HME_XD_EOP |
 			HME_XD_ENCODE_TSIZE(len) | txflags);
 		/*if (sc->sc_rb.rb_td_nbusy <= 0)*/
 		bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING,
 				  HME_ETX_TP_DMAWAKEUP);
 		if (++ri == ntbuf)
 			ri = 0;
 		if (++sc->sc_rb.rb_td_nbusy == ntbuf) {
 			ifp->if_flags |= IFF_OACTIVE;
 			break;
+		}
+	}
 	sc->sc_rb.rb_tdhead = ri;
+}
 /*
  * Transmit interrupt.
  */
 int
 hme_tint(struct hme_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mac = sc->sc_mac;
 	unsigned int ri, txflags;
 	/*
 	 * Unload collision counters
 	 */
 	ifp->if_collisions +=
 		bus_space_read_4(t, mac, HME_MACI_NCCNT) +
 		bus_space_read_4(t, mac, HME_MACI_FCCNT) +
 		bus_space_read_4(t, mac, HME_MACI_EXCNT) +
 		bus_space_read_4(t, mac, HME_MACI_LTCNT);
 	/*
 	 * then clear the hardware counters.
 	 */
 	bus_space_write_4(t, mac, HME_MACI_NCCNT, 0);
 	bus_space_write_4(t, mac, HME_MACI_FCCNT, 0);
 	bus_space_write_4(t, mac, HME_MACI_EXCNT, 0);
 	bus_space_write_4(t, mac, HME_MACI_LTCNT, 0);
 	/* Fetch current position in the transmit ring */
 	ri = sc->sc_rb.rb_tdtail;
 	for (;;) {
 		if (sc->sc_rb.rb_td_nbusy <= 0)
 			break;
 		txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri);
 		if (txflags & HME_XD_OWN)
 			break;
 		ifp->if_flags &= ~IFF_OACTIVE;
 		ifp->if_opackets++;
 		if (++ri == sc->sc_rb.rb_ntbuf)
 			ri = 0;
 		--sc->sc_rb.rb_td_nbusy;
+	}
 	/* Update ring */
 	sc->sc_rb.rb_tdtail = ri;
 	hme_start(ifp);
 	if (sc->sc_rb.rb_td_nbusy == 0)
 		ifp->if_timer = 0;
 	return (1);
+}
 /*
  * Receive interrupt.
  */
 int
 hme_rint(struct hme_softc *sc)
+{
 	void *xdr = sc->sc_rb.rb_rxd;
 	unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
 	unsigned int ri;
 	u_int32_t flags;
 	ri = sc->sc_rb.rb_rdtail;
 	/*
 	 * Process all buffers with valid data.
 	 */
 	for (;;) {
 		flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri);
 		if (flags & HME_XD_OWN)
 			break;
 		if (flags & HME_XD_OFL) {
 			printf("%s: buffer overflow, ri=%d; flags=0x%x\n",
 					device_xname(&sc->sc_dev), ri, flags);
 		} else
 			hme_read(sc, ri, flags);
 		/* This buffer can be used by the hardware again */
 		HME_XD_SETFLAGS(sc->sc_pci, xdr, ri,
 				HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ));
 		if (++ri == nrbuf)
 			ri = 0;
+	}
 	sc->sc_rb.rb_rdtail = ri;
 	return (1);
+}
 int
 hme_eint(struct hme_softc *sc, u_int status)
+{
 	char bits[128];
 	if ((status & HME_SEB_STAT_MIFIRQ) != 0) {
 		bus_space_tag_t t = sc->sc_bustag;
 		bus_space_handle_t mif = sc->sc_mif;
 		u_int32_t cf, st, sm;
 		cf = bus_space_read_4(t, mif, HME_MIFI_CFG);
 		st = bus_space_read_4(t, mif, HME_MIFI_STAT);
 		sm = bus_space_read_4(t, mif, HME_MIFI_SM);
 		printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n",
 			device_xname(&sc->sc_dev), cf, st, sm);
 		return (1);
+	}
 	snprintb(bits, sizeof(bits), HME_SEB_STAT_BITS, status);
 	printf("%s: status=%s\n", device_xname(&sc->sc_dev), bits);
 	return (1);
+}
 int
 hme_intr(void *v)
+{
 	struct hme_softc *sc = (struct hme_softc *)v;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t seb = sc->sc_seb;
 	u_int32_t status;
 	int r = 0;
 	status = bus_space_read_4(t, seb, HME_SEBI_STAT);
 	if ((status & HME_SEB_STAT_ALL_ERRORS) != 0)
 		r |= hme_eint(sc, status);
 	if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0)
 		r |= hme_tint(sc);
 	if ((status & HME_SEB_STAT_RXTOHOST) != 0)
 		r |= hme_rint(sc);
 #if NRND > 0
 	rnd_add_uint32(&sc->rnd_source, status);
 #endif
 	return (r);
+}
 void
 hme_watchdog(struct ifnet *ifp)
+{
 	struct hme_softc *sc = ifp->if_softc;
 	log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev));
 	++ifp->if_oerrors;
 	hme_reset(sc);
+}
 /*
  * Initialize the MII Management Interface
  */
 void
 hme_mifinit(struct hme_softc *sc)
+{
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mif = sc->sc_mif;
 	bus_space_handle_t mac = sc->sc_mac;
 	int instance, phy;
 	u_int32_t v;
 	if (sc->sc_mii.mii_media.ifm_cur != NULL) {
 		instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
 		phy = sc->sc_phys[instance];
 	} else
 		/* No media set yet, pick phy arbitrarily.. */
 		phy = HME_PHYAD_EXTERNAL;
 	/* Configure the MIF in frame mode, no poll, current phy select */
 	v = 0;
 	if (phy == HME_PHYAD_EXTERNAL)
 		v |= HME_MIF_CFG_PHY;
 	bus_space_write_4(t, mif, HME_MIFI_CFG, v);
 	/* If an external transceiver is selected, enable its MII drivers */
 	v = bus_space_read_4(t, mac, HME_MACI_XIF);
 	v &= ~HME_MAC_XIF_MIIENABLE;
 	if (phy == HME_PHYAD_EXTERNAL)
 		v |= HME_MAC_XIF_MIIENABLE;
 	bus_space_write_4(t, mac, HME_MACI_XIF, v);
+}
 /*
  * MII interface
  */
 static int
 hme_mii_readreg(struct device *self, int phy, int reg)
+{
 	struct hme_softc *sc = (void *)self;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mif = sc->sc_mif;
 	bus_space_handle_t mac = sc->sc_mac;
 	u_int32_t v, xif_cfg, mifi_cfg;
 	int n;
 	/* We can at most have two PHYs */
 	if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)
 		return (0);
 	/* Select the desired PHY in the MIF configuration register */
 	v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG);
 	v &= ~HME_MIF_CFG_PHY;
 	if (phy == HME_PHYAD_EXTERNAL)
 		v |= HME_MIF_CFG_PHY;
 	bus_space_write_4(t, mif, HME_MIFI_CFG, v);
 	/* Enable MII drivers on external transceiver */
 	v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF);
 	if (phy == HME_PHYAD_EXTERNAL)
 		v |= HME_MAC_XIF_MIIENABLE;
 	else
 		v &= ~HME_MAC_XIF_MIIENABLE;
 	bus_space_write_4(t, mac, HME_MACI_XIF, v);
 #if 0
 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */
 	/*
 	 * Check whether a transceiver is connected by testing
 	 * the MIF configuration register's MDI_X bits. Note that
 	 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h
 	 */
 	mif_mdi_bit = 1 << (8 + (1 - phy));
 	delay(100);
 	v = bus_space_read_4(t, mif, HME_MIFI_CFG);
 	if ((v & mif_mdi_bit) == 0)
 		return (0);
 #endif
 	/* Construct the frame command */
 	v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) |
 	    HME_MIF_FO_TAMSB |
 	    (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) |
 	    (phy << HME_MIF_FO_PHYAD_SHIFT) |
 	    (reg << HME_MIF_FO_REGAD_SHIFT);
 	bus_space_write_4(t, mif, HME_MIFI_FO, v);
 	for (n = 0; n < 100; n++) {
 		DELAY(1);
 		v = bus_space_read_4(t, mif, HME_MIFI_FO);
 		if (v & HME_MIF_FO_TALSB) {
 			v &= HME_MIF_FO_DATA;
 			goto out;
+		}
+	}
 	v = 0;
 	printf("%s: mii_read timeout\n", device_xname(&sc->sc_dev));
 out:
 	/* Restore MIFI_CFG register */
 	bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg);
 	/* Restore XIF register */
 	bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg);
 	return (v);
+}
 static void
 hme_mii_writereg(struct device *self, int phy, int reg, int val)
+{
 	struct hme_softc *sc = (void *)self;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mif = sc->sc_mif;
 	bus_space_handle_t mac = sc->sc_mac;
 	u_int32_t v, xif_cfg, mifi_cfg;
 	int n;
 	/* We can at most have two PHYs */
 	if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)
 		return;
 	/* Select the desired PHY in the MIF configuration register */
 	v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG);
 	v &= ~HME_MIF_CFG_PHY;
 	if (phy == HME_PHYAD_EXTERNAL)
 		v |= HME_MIF_CFG_PHY;
 	bus_space_write_4(t, mif, HME_MIFI_CFG, v);
 	/* Enable MII drivers on external transceiver */
 	v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF);
 	if (phy == HME_PHYAD_EXTERNAL)
 		v |= HME_MAC_XIF_MIIENABLE;
 	else
 		v &= ~HME_MAC_XIF_MIIENABLE;
 	bus_space_write_4(t, mac, HME_MACI_XIF, v);
 #if 0
 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */
 	/*
 	 * Check whether a transceiver is connected by testing
 	 * the MIF configuration register's MDI_X bits. Note that
 	 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h
 	 */
 	mif_mdi_bit = 1 << (8 + (1 - phy));
 	delay(100);
 	v = bus_space_read_4(t, mif, HME_MIFI_CFG);
 	if ((v & mif_mdi_bit) == 0)
 		return;
 #endif
 	/* Construct the frame command */
 	v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT)	|
 	    HME_MIF_FO_TAMSB				|
 	    (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT)	|
 	    (phy << HME_MIF_FO_PHYAD_SHIFT)		|
 	    (reg << HME_MIF_FO_REGAD_SHIFT)		|
 	    (val & HME_MIF_FO_DATA);
 	bus_space_write_4(t, mif, HME_MIFI_FO, v);
 	for (n = 0; n < 100; n++) {
 		DELAY(1);
 		v = bus_space_read_4(t, mif, HME_MIFI_FO);
 		if (v & HME_MIF_FO_TALSB)
 			goto out;
+	}
 	printf("%s: mii_write timeout\n", device_xname(&sc->sc_dev));
 out:
 	/* Restore MIFI_CFG register */
 	bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg);
 	/* Restore XIF register */
 	bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg);
+}
 static void
 hme_mii_statchg(struct device *dev)
+{
 	struct hme_softc *sc = (void *)dev;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mac = sc->sc_mac;
 	u_int32_t v;
 #ifdef HMEDEBUG
 	if (sc->sc_debug)
 		printf("hme_mii_statchg: status change\n");
 #endif
 	/* Set the MAC Full Duplex bit appropriately */
 	/* Apparently the hme chip is SIMPLEX if working in full duplex mode,
 	   but not otherwise. */
 	v = bus_space_read_4(t, mac, HME_MACI_TXCFG);
 	if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) {
 		v |= HME_MAC_TXCFG_FULLDPLX;
 		sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX;
 	} else {
 		v &= ~HME_MAC_TXCFG_FULLDPLX;
 		sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX;
+	}
 	sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags;
 	bus_space_write_4(t, mac, HME_MACI_TXCFG, v);
+}
 int
 hme_mediachange(struct ifnet *ifp)
+{
 	struct hme_softc *sc = ifp->if_softc;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mif = sc->sc_mif;
 	bus_space_handle_t mac = sc->sc_mac;
 	int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
 	int phy = sc->sc_phys[instance];
 	int rc;
 	u_int32_t v;
 #ifdef HMEDEBUG
 	if (sc->sc_debug)
 		printf("hme_mediachange: phy = %d\n", phy);
 #endif
 	/* Select the current PHY in the MIF configuration register */
 	v = bus_space_read_4(t, mif, HME_MIFI_CFG);
 	v &= ~HME_MIF_CFG_PHY;
 	if (phy == HME_PHYAD_EXTERNAL)
 		v |= HME_MIF_CFG_PHY;
 	bus_space_write_4(t, mif, HME_MIFI_CFG, v);
 	/* If an external transceiver is selected, enable its MII drivers */
 	v = bus_space_read_4(t, mac, HME_MACI_XIF);
 	v &= ~HME_MAC_XIF_MIIENABLE;
 	if (phy == HME_PHYAD_EXTERNAL)
 		v |= HME_MAC_XIF_MIIENABLE;
 	bus_space_write_4(t, mac, HME_MACI_XIF, v);
 	if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
 		return 0;
 	return rc;
+}
 /*
  * Process an ioctl request.
  */
 int
 hme_ioctl(struct ifnet *ifp, unsigned long cmd, void *data)
+{
 	struct hme_softc *sc = ifp->if_softc;
 	struct ifaddr *ifa = (struct ifaddr *)data;
 	int s, error = 0;
 	s = splnet();
 	switch (cmd) {
 	case SIOCINITIFADDR:
 		switch (ifa->ifa_addr->sa_family) {
 #ifdef INET
 		case AF_INET:
 			if (ifp->if_flags & IFF_UP)
 				hme_setladrf(sc);
 			else {
 				ifp->if_flags |= IFF_UP;
 				error = hme_init(sc);
+			}
 			arp_ifinit(ifp, ifa);
 			break;
 #endif
 		default:
 			ifp->if_flags |= IFF_UP;
 			error = hme_init(sc);
 			break;
+		}
 		break;
 	case SIOCSIFFLAGS:
 #ifdef HMEDEBUG
+		{
 			struct ifreq *ifr = data;
 			sc->sc_debug =
 			    (ifr->ifr_flags & IFF_DEBUG) != 0 ? 1 : 0;
+		}
 #endif
 		if ((error = ifioctl_common(ifp, cmd, data)) != 0)
 			break;
 		switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) {
 		case IFF_RUNNING:
 			/*
 			 * If interface is marked down and it is running, then
 			 * stop it.
 			 */
 			hme_stop(sc, false);
 			ifp->if_flags &= ~IFF_RUNNING;
 			break;
 		case IFF_UP:
 			/*
 			 * If interface is marked up and it is stopped, then
 			 * start it.
 			 */
 			error = hme_init(sc);
 			break;
 		case IFF_UP|IFF_RUNNING:
 			/*
 			 * If setting debug or promiscuous mode, do not reset
 			 * the chip; for everything else, call hme_init()
 			 * which will trigger a reset.
 			 */
 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG)
 			if (ifp->if_flags != sc->sc_if_flags) {
 				if ((ifp->if_flags & (~RESETIGN))
 				    == (sc->sc_if_flags & (~RESETIGN)))
 					hme_setladrf(sc);
 				else
 					error = hme_init(sc);
+			}
 #undef RESETIGN
 			break;
 		case 0:
 			break;
+		}
 		if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable)
 			error = hme_init(sc);
 		break;
 	default:
 		if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
 			break;
 		error = 0;
 		if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
+			;
 		else if (ifp->if_flags & IFF_RUNNING) {
 			/*
 			 * Multicast list has changed; set the hardware filter
 			 * accordingly.
 			 */
 			hme_setladrf(sc);
+		}
 		break;
+	}
 	sc->sc_if_flags = ifp->if_flags;
 	splx(s);
 	return (error);
+}
 void
 hme_shutdown(void *arg)
+{
 	hme_stop((struct hme_softc *)arg, false);
+}
 /*
  * Set up the logical address filter.
  */
 void
 hme_setladrf(struct hme_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	struct ethercom *ec = &sc->sc_ethercom;
 	bus_space_tag_t t = sc->sc_bustag;
 	bus_space_handle_t mac = sc->sc_mac;
 	u_char *cp;
 	u_int32_t crc;
 	u_int32_t hash[4];
 	u_int32_t v;
 	int len;
 	/* Clear hash table */
 	hash[3] = hash[2] = hash[1] = hash[0] = 0;
 	/* Get current RX configuration */
 	v = bus_space_read_4(t, mac, HME_MACI_RXCFG);
 	if ((ifp->if_flags & IFF_PROMISC) != 0) {
 		/* Turn on promiscuous mode; turn off the hash filter */
 		v |= HME_MAC_RXCFG_PMISC;
 		v &= ~HME_MAC_RXCFG_HENABLE;
 		ifp->if_flags |= IFF_ALLMULTI;
 		goto chipit;
+	}
 	/* Turn off promiscuous mode; turn on the hash filter */
 	v &= ~HME_MAC_RXCFG_PMISC;
 	v |= HME_MAC_RXCFG_HENABLE;
 	/*
 	 * Set up multicast address filter by passing all multicast addresses
 	 * through a crc generator, and then using the high order 6 bits as an
 	 * index into the 64 bit logical address filter.  The high order bit
 	 * selects the word, while the rest of the bits select the bit within
 	 * the word.
 	 */
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 			/*
 			 * We must listen to a range of multicast addresses.
 			 * For now, just accept all multicasts, rather than
 			 * trying to set only those filter bits needed to match
 			 * the range.  (At this time, the only use of address
 			 * ranges is for IP multicast routing, for which the
 			 * range is big enough to require all bits set.)
 			 */
 			hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
 			ifp->if_flags |= IFF_ALLMULTI;
 			goto chipit;
+		}
 		cp = enm->enm_addrlo;
 		crc = 0xffffffff;
 		for (len = sizeof(enm->enm_addrlo); --len >= 0;) {
 			int octet = *cp++;
 			int i;
 #define MC_POLY_LE	0xedb88320UL	/* mcast crc, little endian */
 			for (i = 0; i < 8; i++) {
 				if ((crc & 1) ^ (octet & 1)) {
 					crc >>= 1;
 					crc ^= MC_POLY_LE;
 				} else {
 					crc >>= 1;
+				}
 				octet >>= 1;
+			}
+		}
 		/* Just want the 6 most significant bits. */
 		crc >>= 26;
 		/* Set the corresponding bit in the filter. */
 		hash[crc >> 4] |= 1 << (crc & 0xf);
 		ETHER_NEXT_MULTI(step, enm);
+	}
 	ifp->if_flags &= ~IFF_ALLMULTI;
 chipit:
 	/* Now load the hash table into the chip */
 	bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]);
 	bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]);
 	bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]);
 	bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]);
 	bus_space_write_4(t, mac, HME_MACI_RXCFG, v);
+}
 /*
  * Routines for accessing the transmit and receive buffers.
  * The various CPU and adapter configurations supported by this
  * driver require three different access methods for buffers
  * and descriptors:
  *	(1) contig (contiguous data; no padding),
  *	(2) gap2 (two bytes of data followed by two bytes of padding),
  *	(3) gap16 (16 bytes of data followed by 16 bytes of padding).
  */
 #if 0
 /*
  * contig: contiguous data with no padding.
+ *
  * Buffers may have any alignment.
  */
 void
 hme_copytobuf_contig(struct hme_softc *sc, void *from, int ri, int len)
+{
 	volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ);
 	/*
 	 * Just call memcpy() to do the work.
 	 */
 	memcpy(buf, from, len);
+}
 void
 hme_copyfrombuf_contig(struct hme_softc *sc, void *to, int boff, int len)
+{
 	volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ);
 	/*
 	 * Just call memcpy() to do the work.
 	 */
 	memcpy(to, buf, len);
+}
 #endif