 @@ -1,14 +1,14 @@
-/*	$NetBSD: ichlpcib.c,v 1.15 2009/03/03 06:05:28 mrg Exp $	*/
+/*	$NetBSD: ichlpcib.c,v 1.16 2009/04/04 23:13:18 joerg Exp $	*/
 /*-
  * Copyright (c) 2004 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Minoura Makoto and Matthew R. Green.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -29,27 +29,27 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver
+ *
  *  LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has
  *  some power management and monitoring functions.
  *  Currently we support the watchdog timer, SpeedStep (on some systems)
  *  and the power management timer.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.15 2009/03/03 06:05:28 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.16 2009/04/04 23:13:18 joerg Exp $");
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/sysctl.h>
 #include <sys/timetc.h>
 #include <machine/bus.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcidevs.h>
 @@ -76,36 +76,40 @@ struct lpcib_softc {
 	bus_space_handle_t	sc_rcbah;
 	pcireg_t		sc_rcba_reg;
 	/* Watchdog variables. */
 	struct sysmon_wdog	sc_smw;
 	bus_space_tag_t		sc_iot;
 	bus_space_handle_t	sc_ioh;
 #if NHPET > 0
 	/* HPET variables. */
 	uint32_t		sc_hpet_reg;
 #endif
 	/* Speedstep */
 	pcireg_t		sc_pmcon_orig;
 	/* Power management */
 	pcireg_t		sc_pirq[2];
 	pcireg_t		sc_pmcon;
 	pcireg_t		sc_fwhsel2;
 };
 static int lpcibmatch(device_t, cfdata_t, void *);
 static void lpcibattach(device_t, device_t, void *);
 static bool lpcib_suspend(device_t PMF_FN_PROTO);
 static bool lpcib_resume(device_t PMF_FN_PROTO);
 static bool lpcib_shutdown(device_t, int);
 static void pmtimer_configure(device_t);
 static void tcotimer_configure(device_t);
 static int tcotimer_setmode(struct sysmon_wdog *);
 static int tcotimer_tickle(struct sysmon_wdog *);
 static void tcotimer_stop(struct lpcib_softc *);
 static void tcotimer_start(struct lpcib_softc *);
 static void tcotimer_status_reset(struct lpcib_softc *);
 static int  tcotimer_disable_noreboot(device_t);
 static void speedstep_configure(device_t);
 static int speedstep_sysctl_helper(SYSCTLFN_ARGS);
 @@ -195,26 +199,29 @@ lpcibattach(device_t parent, device_t se
 	pcibattach(parent, self, aux);
 	/*
 	 * Part of our I/O registers are used as ACPI PM regs.
 	 * Since our ACPI subsystem accesses the I/O space directly so far,
 	 * we do not have to bother bus_space I/O map confliction.
 	 */
 	if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0,
 			   &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) {
 		aprint_error_dev(self, "can't map power management i/o space");
 		return;
+	}
 	sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag,
 	    LPCIB_PCI_GEN_PMCON_1);
 	/* For ICH6 and later, always enable RCBA */
 	if (sc->sc_has_rcba) {
 		pcireg_t rcba;
 		sc->sc_rcbat = sc->sc_pa.pa_memt;
 		rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag,
 		     LPCIB_RCBA);
 		if ((rcba & LPCIB_RCBA_EN) == 0) {
 			aprint_error_dev(self, "RCBA is not enabled");
 			return;
+		}
 		rcba &= ~LPCIB_RCBA_EN;
 @@ -231,31 +238,43 @@ lpcibattach(device_t parent, device_t se
 	/* Set up the TCO (watchdog). */
 	tcotimer_configure(self);
 	/* Set up SpeedStep. */
 	speedstep_configure(self);
 #if NHPET > 0
 	/* Set up HPET. */
 	lpcib_hpet_configure(self);
 #endif
 	/* Install power handler */
-	if (!pmf_device_register(self, lpcib_suspend, lpcib_resume))
+	if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume,
 	    lpcib_shutdown))
 		aprint_error_dev(self, "couldn't establish power handler\n");
+}
 static bool
 lpcib_shutdown(device_t dv, int howto)
+{
 	struct lpcib_softc *sc = device_private(dv);
 	pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag,
 	    LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig);
 	return true;
+}
 static bool
 lpcib_suspend(device_t dv PMF_FN_ARGS)
+{
 	struct lpcib_softc *sc = device_private(dv);
 	pci_chipset_tag_t pc = sc->sc_pcib.sc_pc;
 	pcitag_t tag = sc->sc_pcib.sc_tag;
 	/* capture PIRQ routing control registers */
 	sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT);
 	sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT);
 	sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1);
 	sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA);