 @@ -1,2548 +1,2548 @@
-/*	$NetBSD: if_wm.c,v 1.162.4.5 2009/05/03 17:54:07 snj Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.162.4.6 2009/05/03 17:56:05 snj Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed for the NetBSD Project by
  *	Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*******************************************************************************
   Copyright (c) 2001-2005, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 . Redistributions in binary form must reproduce the above copyright
       notice, this list of conditions and the following disclaimer in the
       documentation and/or other materials provided with the distribution.
 . Neither the name of the Intel Corporation nor the names of its
       contributors may be used to endorse or promote products derived from
       this software without specific prior written permission.
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/
 /*
  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
+ *
  * TODO (in order of importance):
+ *
  *	- Rework how parameters are loaded from the EEPROM.
  *	- Figure out what to do with the i82545GM and i82546GB
  *	  SERDES controllers.
  *	- Fix hw VLAN assist.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.162.4.5 2009/05/03 17:54:07 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.162.4.6 2009/05/03 17:56:05 snj Exp $");
 #include "bpfilter.h"
 #include "rnd.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/queue.h>
 #include <sys/syslog.h>
 #include <uvm/uvm_extern.h>		/* for PAGE_SIZE */
 #if NRND > 0
 #include <sys/rnd.h>
 #endif
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #if NBPFILTER > 0
 #include <net/bpf.h>
 #endif
 #include <netinet/in.h>			/* XXX for struct ip */
 #include <netinet/in_systm.h>		/* XXX for struct ip */
 #include <netinet/ip.h>			/* XXX for struct ip */
 #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
 #include <netinet/tcp.h>		/* XXX for struct tcphdr */
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <machine/endian.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/mii_bitbang.h>
 #include <dev/mii/ikphyreg.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/if_wmreg.h>
 #ifdef WM_DEBUG
 #define	WM_DEBUG_LINK		0x01
 #define	WM_DEBUG_TX		0x02
 #define	WM_DEBUG_RX		0x04
 #define	WM_DEBUG_GMII		0x08
 int	wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK|WM_DEBUG_GMII;
 #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
 #else
 #define	DPRINTF(x, y)	/* nothing */
 #endif /* WM_DEBUG */
 /*
  * Transmit descriptor list size.  Due to errata, we can only have
  * 256 hardware descriptors in the ring on < 82544, but we use 4096
  * on >= 82544.  We tell the upper layers that they can queue a lot
  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
  * of them at a time.
+ *
  * We allow up to 256 (!) DMA segments per packet.  Pathological packet
  * chains containing many small mbufs have been observed in zero-copy
  * situations with jumbo frames.
  */
 #define	WM_NTXSEGS		256
 #define	WM_IFQUEUELEN		256
 #define	WM_TXQUEUELEN_MAX	64
 #define	WM_TXQUEUELEN_MAX_82547	16
 #define	WM_TXQUEUELEN(sc)	((sc)->sc_txnum)
 #define	WM_TXQUEUELEN_MASK(sc)	(WM_TXQUEUELEN(sc) - 1)
 #define	WM_TXQUEUE_GC(sc)	(WM_TXQUEUELEN(sc) / 8)
 #define	WM_NTXDESC_82542	256
 #define	WM_NTXDESC_82544	4096
 #define	WM_NTXDESC(sc)		((sc)->sc_ntxdesc)
 #define	WM_NTXDESC_MASK(sc)	(WM_NTXDESC(sc) - 1)
 #define	WM_TXDESCSIZE(sc)	(WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t))
 #define	WM_NEXTTX(sc, x)	(((x) + 1) & WM_NTXDESC_MASK(sc))
 #define	WM_NEXTTXS(sc, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(sc))
 #define	WM_MAXTXDMA		round_page(IP_MAXPACKET) /* for TSO */
 /*
  * Receive descriptor list size.  We have one Rx buffer for normal
  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
  * packet.  We allocate 256 receive descriptors, each with a 2k
  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
  */
 #define	WM_NRXDESC		256
 #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
 #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
 #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
 /*
  * Control structures are DMA'd to the i82542 chip.  We allocate them in
  * a single clump that maps to a single DMA segment to make several things
  * easier.
  */
 struct wm_control_data_82544 {
 	/*
 	 * The receive descriptors.
 	 */
 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
 	/*
 	 * The transmit descriptors.  Put these at the end, because
 	 * we might use a smaller number of them.
 	 */
 	wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544];
 };
 struct wm_control_data_82542 {
 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
 	wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542];
 };
 #define	WM_CDOFF(x)	offsetof(struct wm_control_data_82544, x)
 #define	WM_CDTXOFF(x)	WM_CDOFF(wcd_txdescs[(x)])
 #define	WM_CDRXOFF(x)	WM_CDOFF(wcd_rxdescs[(x)])
 /*
  * Software state for transmit jobs.
  */
 struct wm_txsoft {
 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t txs_dmamap;	/* our DMA map */
 	int txs_firstdesc;		/* first descriptor in packet */
 	int txs_lastdesc;		/* last descriptor in packet */
 	int txs_ndesc;			/* # of descriptors used */
 };
 /*
  * Software state for receive buffers.  Each descriptor gets a
  * 2k (MCLBYTES) buffer and a DMA map.  For packets which fill
  * more than one buffer, we chain them together.
  */
 struct wm_rxsoft {
 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
 };
 typedef enum {
 	WM_T_unknown		= 0,
 	WM_T_82542_2_0,			/* i82542 2.0 (really old) */
 	WM_T_82542_2_1,			/* i82542 2.1+ (old) */
 	WM_T_82543,			/* i82543 */
 	WM_T_82544,			/* i82544 */
 	WM_T_82540,			/* i82540 */
 	WM_T_82545,			/* i82545 */
 	WM_T_82545_3,			/* i82545 3.0+ */
 	WM_T_82546,			/* i82546 */
 	WM_T_82546_3,			/* i82546 3.0+ */
 	WM_T_82541,			/* i82541 */
 	WM_T_82541_2,			/* i82541 2.0+ */
 	WM_T_82547,			/* i82547 */
 	WM_T_82547_2,			/* i82547 2.0+ */
 	WM_T_82571,			/* i82571 */
 	WM_T_82572,			/* i82572 */
 	WM_T_82573,			/* i82573 */
 	WM_T_82574,			/* i82574 */
 	WM_T_80003,			/* i80003 */
 	WM_T_ICH8,			/* ICH8 LAN */
 	WM_T_ICH9,			/* ICH9 LAN */
 } wm_chip_type;
 /*
  * Software state per device.
  */
 struct wm_softc {
 	device_t sc_dev;		/* generic device information */
 	bus_space_tag_t sc_st;		/* bus space tag */
 	bus_space_handle_t sc_sh;	/* bus space handle */
 	bus_space_tag_t sc_iot;		/* I/O space tag */
 	bus_space_handle_t sc_ioh;	/* I/O space handle */
 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
 	struct ethercom sc_ethercom;	/* ethernet common data */
 	pci_chipset_tag_t sc_pc;
 	pcitag_t sc_pcitag;
 	wm_chip_type sc_type;		/* chip type */
 	int sc_flags;			/* flags; see below */
 	int sc_bus_speed;		/* PCI/PCIX bus speed */
 	int sc_pcix_offset;		/* PCIX capability register offset */
 	int sc_flowflags;		/* 802.3x flow control flags */
 	void *sc_ih;			/* interrupt cookie */
 	int sc_ee_addrbits;		/* EEPROM address bits */
 	struct mii_data sc_mii;		/* MII/media information */
 	callout_t sc_tick_ch;		/* tick callout */
 	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
 #define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
 	int		sc_align_tweak;
 	/*
 	 * Software state for the transmit and receive descriptors.
 	 */
 	int			sc_txnum;	/* must be a power of two */
 	struct wm_txsoft	sc_txsoft[WM_TXQUEUELEN_MAX];
 	struct wm_rxsoft	sc_rxsoft[WM_NRXDESC];
 	/*
 	 * Control data structures.
 	 */
 	int			sc_ntxdesc;	/* must be a power of two */
 	struct wm_control_data_82544 *sc_control_data;
 #define	sc_txdescs	sc_control_data->wcd_txdescs
 #define	sc_rxdescs	sc_control_data->wcd_rxdescs
 #ifdef WM_EVENT_COUNTERS
 	/* Event counters. */
 	struct evcnt sc_ev_txsstall;	/* Tx stalled due to no txs */
 	struct evcnt sc_ev_txdstall;	/* Tx stalled due to no txd */
 	struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */
 	struct evcnt sc_ev_txdw;	/* Tx descriptor interrupts */
 	struct evcnt sc_ev_txqe;	/* Tx queue empty interrupts */
 	struct evcnt sc_ev_rxintr;	/* Rx interrupts */
 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
 	struct evcnt sc_ev_rxipsum;	/* IP checksums checked in-bound */
 	struct evcnt sc_ev_rxtusum;	/* TCP/UDP cksums checked in-bound */
 	struct evcnt sc_ev_txipsum;	/* IP checksums comp. out-bound */
 	struct evcnt sc_ev_txtusum;	/* TCP/UDP cksums comp. out-bound */
 	struct evcnt sc_ev_txtusum6;	/* TCP/UDP v6 cksums comp. out-bound */
 	struct evcnt sc_ev_txtso;	/* TCP seg offload out-bound (IPv4) */
 	struct evcnt sc_ev_txtso6;	/* TCP seg offload out-bound (IPv6) */
 	struct evcnt sc_ev_txtsopain;	/* painful header manip. for TSO */
 	struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
 	struct evcnt sc_ev_txdrop;	/* Tx packets dropped (too many segs) */
 	struct evcnt sc_ev_tu;		/* Tx underrun */
 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
 #endif /* WM_EVENT_COUNTERS */
 	bus_addr_t sc_tdt_reg;		/* offset of TDT register */
 	int	sc_txfree;		/* number of free Tx descriptors */
 	int	sc_txnext;		/* next ready Tx descriptor */
 	int	sc_txsfree;		/* number of free Tx jobs */
 	int	sc_txsnext;		/* next free Tx job */
 	int	sc_txsdirty;		/* dirty Tx jobs */
 	/* These 5 variables are used only on the 82547. */
 	int	sc_txfifo_size;		/* Tx FIFO size */
 	int	sc_txfifo_head;		/* current head of FIFO */
 	uint32_t sc_txfifo_addr;	/* internal address of start of FIFO */
 	int	sc_txfifo_stall;	/* Tx FIFO is stalled */
 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
 	bus_addr_t sc_rdt_reg;		/* offset of RDT register */
 	int	sc_rxptr;		/* next ready Rx descriptor/queue ent */
 	int	sc_rxdiscard;
 	int	sc_rxlen;
 	struct mbuf *sc_rxhead;
 	struct mbuf *sc_rxtail;
 	struct mbuf **sc_rxtailp;
 	uint32_t sc_ctrl;		/* prototype CTRL register */
 #if 0
 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
 #endif
 	uint32_t sc_icr;		/* prototype interrupt bits */
 	uint32_t sc_itr;		/* prototype intr throttling reg */
 	uint32_t sc_tctl;		/* prototype TCTL register */
 	uint32_t sc_rctl;		/* prototype RCTL register */
 	uint32_t sc_txcw;		/* prototype TXCW register */
 	uint32_t sc_tipg;		/* prototype TIPG register */
 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
 	uint32_t sc_pba;		/* prototype PBA register */
 	int sc_tbi_linkup;		/* TBI link status */
 	int sc_tbi_anstate;		/* autonegotiation state */
 	int sc_mchash_type;		/* multicast filter offset */
 #if NRND > 0
 	rndsource_element_t rnd_source;	/* random source */
 #endif
 	int sc_ich8_flash_base;
 	int sc_ich8_flash_bank_size;
 };
 #define	WM_RXCHAIN_RESET(sc)						\
 do {									\
 	(sc)->sc_rxtailp = &(sc)->sc_rxhead;				\
 	*(sc)->sc_rxtailp = NULL;					\
 	(sc)->sc_rxlen = 0;						\
 } while (/*CONSTCOND*/0)
 #define	WM_RXCHAIN_LINK(sc, m)						\
 do {									\
 	*(sc)->sc_rxtailp = (sc)->sc_rxtail = (m);			\
 	(sc)->sc_rxtailp = &(m)->m_next;				\
 } while (/*CONSTCOND*/0)
 /* sc_flags */
 #define	WM_F_HAS_MII		0x0001	/* has MII */
 #define	WM_F_EEPROM_HANDSHAKE	0x0002	/* requires EEPROM handshake */
 #define	WM_F_EEPROM_SEMAPHORE	0x0004	/* EEPROM with semaphore */
 #define	WM_F_EEPROM_EERDEEWR	0x0008	/* EEPROM access via EERD/EEWR */
 #define	WM_F_EEPROM_SPI		0x0010	/* EEPROM is SPI */
 #define	WM_F_EEPROM_FLASH	0x0020	/* EEPROM is FLASH */
 #define	WM_F_EEPROM_INVALID	0x0040	/* EEPROM not present (bad checksum) */
 #define	WM_F_IOH_VALID		0x0080	/* I/O handle is valid */
 #define	WM_F_BUS64		0x0100	/* bus is 64-bit */
 #define	WM_F_PCIX		0x0200	/* bus is PCI-X */
 #define	WM_F_CSA		0x0400	/* bus is CSA */
 #define	WM_F_PCIE		0x0800	/* bus is PCI-Express */
 #define WM_F_SWFW_SYNC		0x1000  /* Software-Firmware synchronisation */
 #define WM_F_SWFWHW_SYNC	0x2000  /* Software-Firmware synchronisation */
 #ifdef WM_EVENT_COUNTERS
 #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
 #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
 #else
 #define	WM_EVCNT_INCR(ev)	/* nothing */
 #define	WM_EVCNT_ADD(ev, val)	/* nothing */
 #endif
 #define	CSR_READ(sc, reg)						\
 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
 #define	CSR_WRITE(sc, reg, val)						\
 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
 #define	CSR_WRITE_FLUSH(sc)						\
 	(void) CSR_READ((sc), WMREG_STATUS)
 #define ICH8_FLASH_READ32(sc, reg) \
 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg))
 #define ICH8_FLASH_WRITE32(sc, reg, data) \
 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
 #define ICH8_FLASH_READ16(sc, reg) \
 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg))
 #define ICH8_FLASH_WRITE16(sc, reg, data) \
 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
 #define	WM_CDTXADDR(sc, x)	((sc)->sc_cddma + WM_CDTXOFF((x)))
 #define	WM_CDRXADDR(sc, x)	((sc)->sc_cddma + WM_CDRXOFF((x)))
 #define	WM_CDTXADDR_LO(sc, x)	(WM_CDTXADDR((sc), (x)) & 0xffffffffU)
 #define	WM_CDTXADDR_HI(sc, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0)
 #define	WM_CDRXADDR_LO(sc, x)	(WM_CDRXADDR((sc), (x)) & 0xffffffffU)
 #define	WM_CDRXADDR_HI(sc, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0)
 #define	WM_CDTXSYNC(sc, x, n, ops)					\
 do {									\
 	int __x, __n;							\
+									\
 	__x = (x);							\
 	__n = (n);							\
+									\
 	/* If it will wrap around, sync to the end of the ring. */	\
 	if ((__x + __n) > WM_NTXDESC(sc)) {				\
 		bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,	\
 		    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) *		\
 		    (WM_NTXDESC(sc) - __x), (ops));			\
 		__n -= (WM_NTXDESC(sc) - __x);				\
 		__x = 0;						\
 	}								\
+									\
 	/* Now sync whatever is left. */				\
 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
 	    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops));	\
 } while (/*CONSTCOND*/0)
 #define	WM_CDRXSYNC(sc, x, ops)						\
 do {									\
 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
 	   WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops));		\
 } while (/*CONSTCOND*/0)
 #define	WM_INIT_RXDESC(sc, x)						\
 do {									\
 	struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)];		\
 	wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)];		\
 	struct mbuf *__m = __rxs->rxs_mbuf;				\
+									\
 	/*								\
 	 * Note: We scoot the packet forward 2 bytes in the buffer	\
 	 * so that the payload after the Ethernet header is aligned	\
 	 * to a 4-byte boundary.					\
 	 *								\
 	 * XXX BRAINDAMAGE ALERT!					\
 	 * The stupid chip uses the same size for every buffer, which	\
 	 * is set in the Receive Control register.  We are using the 2K	\
 	 * size option, but what we REALLY want is (2K - 2)!  For this	\
 	 * reason, we can't "scoot" packets longer than the standard	\
 	 * Ethernet MTU.  On strict-alignment platforms, if the total	\
 	 * size exceeds (2K - 2) we set align_tweak to 0 and let	\
 	 * the upper layer copy the headers.				\
 	 */								\
 	__m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak;	\
+									\
 	wm_set_dma_addr(&__rxd->wrx_addr,				\
 	    __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \
 	__rxd->wrx_len = 0;						\
 	__rxd->wrx_cksum = 0;						\
 	__rxd->wrx_status = 0;						\
 	__rxd->wrx_errors = 0;						\
 	__rxd->wrx_special = 0;						\
 	WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
+									\
 	CSR_WRITE((sc), (sc)->sc_rdt_reg, (x));				\
 } while (/*CONSTCOND*/0)
 static void	wm_start(struct ifnet *);
 static void	wm_watchdog(struct ifnet *);
 static int	wm_ioctl(struct ifnet *, u_long, void *);
 static int	wm_init(struct ifnet *);
 static void	wm_stop(struct ifnet *, int);
 static void	wm_reset(struct wm_softc *);
 static void	wm_rxdrain(struct wm_softc *);
 static int	wm_add_rxbuf(struct wm_softc *, int);
 static int	wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *);
 static int	wm_read_eeprom_eerd(struct wm_softc *, int, int, u_int16_t *);
 static int	wm_validate_eeprom_checksum(struct wm_softc *);
 static void	wm_tick(void *);
 static void	wm_set_filter(struct wm_softc *);
 static int	wm_intr(void *);
 static void	wm_txintr(struct wm_softc *);
 static void	wm_rxintr(struct wm_softc *);
 static void	wm_linkintr(struct wm_softc *, uint32_t);
 static void	wm_tbi_mediainit(struct wm_softc *);
 static int	wm_tbi_mediachange(struct ifnet *);
 static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_tbi_set_linkled(struct wm_softc *);
 static void	wm_tbi_check_link(struct wm_softc *);
 static void	wm_gmii_reset(struct wm_softc *);
 static int	wm_gmii_i82543_readreg(device_t, int, int);
 static void	wm_gmii_i82543_writereg(device_t, int, int, int);
 static int	wm_gmii_i82544_readreg(device_t, int, int);
 static void	wm_gmii_i82544_writereg(device_t, int, int, int);
 static int	wm_gmii_i80003_readreg(device_t, int, int);
 static void	wm_gmii_i80003_writereg(device_t, int, int, int);
 static void	wm_gmii_statchg(device_t);
 static void	wm_gmii_mediainit(struct wm_softc *);
 static int	wm_gmii_mediachange(struct ifnet *);
 static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
 static int	wm_kmrn_i80003_readreg(struct wm_softc *, int);
 static void	wm_kmrn_i80003_writereg(struct wm_softc *, int, int);
 static int	wm_match(device_t, cfdata_t, void *);
 static void	wm_attach(device_t, device_t, void *);
 static int	wm_is_onboard_nvm_eeprom(struct wm_softc *);
 static void	wm_get_auto_rd_done(struct wm_softc *);
 static int	wm_get_swsm_semaphore(struct wm_softc *);
 static void	wm_put_swsm_semaphore(struct wm_softc *);
 static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
 static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
 static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
 static int	wm_get_swfwhw_semaphore(struct wm_softc *);
 static void	wm_put_swfwhw_semaphore(struct wm_softc *);
 static int	wm_read_eeprom_ich8(struct wm_softc *, int, int, uint16_t *);
 static int32_t	wm_ich8_cycle_init(struct wm_softc *);
 static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
 static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t,
 		     uint32_t, uint16_t *);
 static int32_t	wm_read_ich8_word(struct wm_softc *sc, uint32_t, uint16_t *);
 static void	wm_82547_txfifo_stall(void *);
 static int	wm_check_mng_mode(struct wm_softc *);
 static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
 static int	wm_check_mng_mode_82574(struct wm_softc *);
 static int	wm_check_mng_mode_generic(struct wm_softc *);
 static void	wm_get_hw_control(struct wm_softc *);
 CFATTACH_DECL_NEW(wm, sizeof(struct wm_softc),
     wm_match, wm_attach, NULL, NULL);
 /*
  * Devices supported by this driver.
  */
 static const struct wm_product {
 	pci_vendor_id_t		wmp_vendor;
 	pci_product_id_t	wmp_product;
 	const char		*wmp_name;
 	wm_chip_type		wmp_type;
 	int			wmp_flags;
 #define	WMP_F_1000X		0x01
 #define	WMP_F_1000T		0x02
 } wm_products[] = {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
 	  "Intel i82542 1000BASE-X Ethernet",
 	  WM_T_82542_2_1,	WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
 	  "Intel i82543GC 1000BASE-X Ethernet",
 	  WM_T_82543,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
 	  "Intel i82543GC 1000BASE-T Ethernet",
 	  WM_T_82543,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
 	  "Intel i82544EI 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
 	  "Intel i82544EI 1000BASE-X Ethernet",
 	  WM_T_82544,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
 	  "Intel i82544GC 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
 	  "Intel i82540EM 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
 	  "Intel i82545EM 1000BASE-T Ethernet",
 	  WM_T_82545,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_COPPER,
 	  "Intel i82545GM 1000BASE-T Ethernet",
 	  WM_T_82545_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_FIBER,
 	  "Intel i82545GM 1000BASE-X Ethernet",
 	  WM_T_82545_3,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_SERDES,
 	  "Intel i82545GM Gigabit Ethernet (SERDES)",
 	  WM_T_82545_3,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82546EB_QUAD,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
 	  "Intel i82545EM 1000BASE-X Ethernet",
 	  WM_T_82545,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
 	  "Intel i82546EB 1000BASE-X Ethernet",
 	  WM_T_82546,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_COPPER,
 	  "Intel i82546GB 1000BASE-T Ethernet",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_FIBER,
 	  "Intel i82546GB 1000BASE-X Ethernet",
 	  WM_T_82546_3,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_SERDES,
 	  "Intel i82546GB Gigabit Ethernet (SERDES)",
 	  WM_T_82546_3,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,
 	  "i82546GB quad-port Gigabit Ethernet",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,
 	  "i82546GB quad-port Gigabit Ethernet (KSP3)",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_PCIE,
 	  "Intel PRO/1000MT (82546GB)",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI,
 	  "Intel i82541EI 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER_LOM,
 	  "Intel i82541ER (LOM) 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI_MOBILE,
 	  "Intel i82541EI Mobile 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER,
 	  "Intel i82541ER 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI,
 	  "Intel i82541GI 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI_MOBILE,
 	  "Intel i82541GI Mobile 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541PI,
 	  "Intel i82541PI 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI,
 	  "Intel i82547EI 1000BASE-T Ethernet",
 	  WM_T_82547,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI_MOBILE,
 	  "Intel i82547EI Mobile 1000BASE-T Ethernet",
 	  WM_T_82547,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547GI,
 	  "Intel i82547GI 1000BASE-T Ethernet",
 	  WM_T_82547_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_COPPER,
 	  "Intel PRO/1000 PT (82571EB)",
 	  WM_T_82571,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_FIBER,
 	  "Intel PRO/1000 PF (82571EB)",
 	  WM_T_82571,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_SERDES,
 	  "Intel PRO/1000 PB (82571EB)",
 	  WM_T_82571,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER,
 	  "Intel PRO/1000 QT (82571EB)",
 	  WM_T_82571,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_COPPER,
 	  "Intel i82572EI 1000baseT Ethernet",
 	  WM_T_82572,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER,
 	  "Intel� PRO/1000 PT Quad Port Server Adapter",
 	  WM_T_82571,		WMP_F_1000T, },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_FIBER,
 	  "Intel i82572EI 1000baseX Ethernet",
 	  WM_T_82572,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_SERDES,
 	  "Intel i82572EI Gigabit Ethernet (SERDES)",
 	  WM_T_82572,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI,
 	  "Intel i82572EI 1000baseT Ethernet",
 	  WM_T_82572,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E,
 	  "Intel i82573E",
 	  WM_T_82573,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E_IAMT,
 	  "Intel i82573E IAMT",
 	  WM_T_82573,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573L,
 	  "Intel i82573L Gigabit Ethernet",
 	  WM_T_82573,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574L,
 	  "Intel i82574L",
 	  WM_T_82574,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT,
 	  "i80003 dual 1000baseT Ethernet",
 	  WM_T_80003,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT,
 	  "i80003 dual 1000baseX Ethernet",
 	  WM_T_80003,		WMP_F_1000T },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT,
 	  "Intel i80003ES2 dual Gigabit Ethernet (SERDES)",
 	  WM_T_80003,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT,
 	  "Intel i80003 1000baseT Ethernet",
 	  WM_T_80003,		WMP_F_1000T },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT,
 	  "Intel i80003 Gigabit Ethernet (SERDES)",
 	  WM_T_80003,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_AMT,
 	  "Intel i82801H (M_AMT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_AMT,
 	  "Intel i82801H (AMT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_LAN,
 	  "Intel i82801H LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_LAN,
 	  "Intel i82801H (IFE) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_LAN,
 	  "Intel i82801H (M) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_GT,
 	  "Intel i82801H IFE (GT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_G,
 	  "Intel i82801H IFE (G) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_AMT,
 	  "82801I (AMT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE,
 	  "82801I LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_G,
 	  "82801I (G) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_GT,
 	  "82801I (GT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_C,
 	  "82801I (C) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M,
 	  "82801I mobile LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IGP_M_V,
 	  "82801I mobile (V) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_AMT,
 	  "82801I mobile (AMT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ 0,			0,
 	  NULL,
 ,			0 },
 };
 #ifdef WM_EVENT_COUNTERS
 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")];
 #endif /* WM_EVENT_COUNTERS */
 #if 0 /* Not currently used */
 static inline uint32_t
 wm_io_read(struct wm_softc *sc, int reg)
+{
 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
 	return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4));
+}
 #endif
 static inline void
 wm_io_write(struct wm_softc *sc, int reg, uint32_t val)
+{
 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val);
+}
 static inline void
 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v)
+{
 	wa->wa_low = htole32(v & 0xffffffffU);
 	if (sizeof(bus_addr_t) == 8)
 		wa->wa_high = htole32((uint64_t) v >> 32);
 	else
 		wa->wa_high = 0;
+}
 static const struct wm_product *
 wm_lookup(const struct pci_attach_args *pa)
+{
 	const struct wm_product *wmp;
 	for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) {
 		if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor &&
 		    PCI_PRODUCT(pa->pa_id) == wmp->wmp_product)
 			return (wmp);
+	}
 	return (NULL);
+}
 static int
 wm_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct pci_attach_args *pa = aux;
 	if (wm_lookup(pa) != NULL)
 		return (1);
 	return (0);
+}
 static void
 wm_attach(device_t parent, device_t self, void *aux)
+{
 	struct wm_softc *sc = device_private(self);
 	struct pci_attach_args *pa = aux;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	pci_chipset_tag_t pc = pa->pa_pc;
 	pci_intr_handle_t ih;
 	size_t cdata_size;
 	const char *intrstr = NULL;
 	const char *eetype, *xname;
 	bus_space_tag_t memt;
 	bus_space_handle_t memh;
 	bus_dma_segment_t seg;
 	int memh_valid;
 	int i, rseg, error;
 	const struct wm_product *wmp;
 	prop_data_t ea;
 	prop_number_t pn;
 	uint8_t enaddr[ETHER_ADDR_LEN];
 	uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin;
 	pcireg_t preg, memtype;
 	uint32_t reg;
 	sc->sc_dev = self;
 	callout_init(&sc->sc_tick_ch, 0);
 	wmp = wm_lookup(pa);
 	if (wmp == NULL) {
 		printf("\n");
 		panic("wm_attach: impossible");
+	}
 	sc->sc_pc = pa->pa_pc;
 	sc->sc_pcitag = pa->pa_tag;
 	if (pci_dma64_available(pa))
 		sc->sc_dmat = pa->pa_dmat64;
 	else
 		sc->sc_dmat = pa->pa_dmat;
 	preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG));
 	aprint_naive(": Ethernet controller\n");
 	aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg);
 	sc->sc_type = wmp->wmp_type;
 	if (sc->sc_type < WM_T_82543) {
 		if (preg < 2) {
 			aprint_error_dev(sc->sc_dev,
 			    "i82542 must be at least rev. 2\n");
 			return;
+		}
 		if (preg < 3)
 			sc->sc_type = WM_T_82542_2_0;
+	}
 	/*
 	 * Map the device.  All devices support memory-mapped acccess,
 	 * and it is really required for normal operation.
 	 */
 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA);
 	switch (memtype) {
 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
 		memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
 		    memtype, 0, &memt, &memh, NULL, NULL) == 0);
 		break;
 	default:
 		memh_valid = 0;
+	}
 	if (memh_valid) {
 		sc->sc_st = memt;
 		sc->sc_sh = memh;
 	} else {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to map device registers\n");
 		return;
+	}
 	/*
 	 * In addition, i82544 and later support I/O mapped indirect
 	 * register access.  It is not desirable (nor supported in
 	 * this driver) to use it for normal operation, though it is
 	 * required to work around bugs in some chip versions.
 	 */
 	if (sc->sc_type >= WM_T_82544) {
 		/* First we have to find the I/O BAR. */
 		for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
 			if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) ==
 			    PCI_MAPREG_TYPE_IO)
 				break;
+		}
 		if (i == PCI_MAPREG_END)
 			aprint_error_dev(sc->sc_dev,
 			    "WARNING: unable to find I/O BAR\n");
 		else {
 			/*
 			 * The i8254x doesn't apparently respond when the
 			 * I/O BAR is 0, which looks somewhat like it's not
 			 * been configured.
 			 */
 			preg = pci_conf_read(pc, pa->pa_tag, i);
 			if (PCI_MAPREG_MEM_ADDR(preg) == 0) {
 				aprint_error_dev(sc->sc_dev,
 				    "WARNING: I/O BAR at zero.\n");
 			} else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO,
 , &sc->sc_iot, &sc->sc_ioh,
 					NULL, NULL) == 0) {
 				sc->sc_flags |= WM_F_IOH_VALID;
 			} else {
 				aprint_error_dev(sc->sc_dev,
 				    "WARNING: unable to map I/O space\n");
+			}
+		}
+	}
 	/* Enable bus mastering.  Disable MWI on the i82542 2.0. */
 	preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
 	preg |= PCI_COMMAND_MASTER_ENABLE;
 	if (sc->sc_type < WM_T_82542_2_1)
 		preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
 	/* power up chip */
 	if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
 	    NULL)) && error != EOPNOTSUPP) {
 		aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
 		return;
+	}
 	/*
 	 * Map and establish our interrupt.
 	 */
 	if (pci_intr_map(pa, &ih)) {
 		aprint_error_dev(sc->sc_dev, "unable to map interrupt\n");
 		return;
+	}
 	intrstr = pci_intr_string(pc, ih);
 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc);
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(sc->sc_dev, "unable to establish interrupt");
 		if (intrstr != NULL)
 			aprint_normal(" at %s", intrstr);
 		aprint_normal("\n");
 		return;
+	}
 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
 	/*
 	 * Determine a few things about the bus we're connected to.
 	 */
 	if (sc->sc_type < WM_T_82543) {
 		/* We don't really know the bus characteristics here. */
 		sc->sc_bus_speed = 33;
 	} else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) {
 		/*
 		 * CSA (Communication Streaming Architecture) is about as fast
 		 * a 32-bit 66MHz PCI Bus.
 		 */
 		sc->sc_flags |= WM_F_CSA;
 		sc->sc_bus_speed = 66;
 		aprint_verbose_dev(sc->sc_dev,
 		    "Communication Streaming Architecture\n");
 		if (sc->sc_type == WM_T_82547) {
 			callout_init(&sc->sc_txfifo_ch, 0);
 			callout_setfunc(&sc->sc_txfifo_ch,
 					wm_82547_txfifo_stall, sc);
 			aprint_verbose_dev(sc->sc_dev,
 			    "using 82547 Tx FIFO stall work-around\n");
+		}
 	} else if (sc->sc_type >= WM_T_82571) {
 		sc->sc_flags |= WM_F_PCIE;
 		if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9))
 			sc->sc_flags |= WM_F_EEPROM_SEMAPHORE;
 		aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n");
 	} else {
 		reg = CSR_READ(sc, WMREG_STATUS);
 		if (reg & STATUS_BUS64)
 			sc->sc_flags |= WM_F_BUS64;
 		if (sc->sc_type >= WM_T_82544 &&
 		    (reg & STATUS_PCIX_MODE) != 0) {
 			pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb;
 			sc->sc_flags |= WM_F_PCIX;
 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
 					       PCI_CAP_PCIX,
 					       &sc->sc_pcix_offset, NULL) == 0)
 				aprint_error_dev(sc->sc_dev,
 				    "unable to find PCIX capability\n");
 			else if (sc->sc_type != WM_T_82545_3 &&
 				 sc->sc_type != WM_T_82546_3) {
 				/*
 				 * Work around a problem caused by the BIOS
 				 * setting the max memory read byte count
 				 * incorrectly.
 				 */
 				pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag,
 				    sc->sc_pcix_offset + PCI_PCIX_CMD);
 				pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag,
 				    sc->sc_pcix_offset + PCI_PCIX_STATUS);
 				bytecnt =
 				    (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >>
 				    PCI_PCIX_CMD_BYTECNT_SHIFT;
 				maxb =
 				    (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >>
 				    PCI_PCIX_STATUS_MAXB_SHIFT;
 				if (bytecnt > maxb) {
 					aprint_verbose_dev(sc->sc_dev,
 					    "resetting PCI-X MMRBC: %d -> %d\n",
 << bytecnt, 512 << maxb);
 					pcix_cmd = (pcix_cmd &
 					    ~PCI_PCIX_CMD_BYTECNT_MASK) |
 					   (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT);
 					pci_conf_write(pa->pa_pc, pa->pa_tag,
 					    sc->sc_pcix_offset + PCI_PCIX_CMD,
 					    pcix_cmd);
+				}
+			}
+		}
 		/*
 		 * The quad port adapter is special; it has a PCIX-PCIX
 		 * bridge on the board, and can run the secondary bus at
 		 * a higher speed.
 		 */
 		if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) {
 			sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120
 								      : 66;
 		} else if (sc->sc_flags & WM_F_PCIX) {
 			switch (reg & STATUS_PCIXSPD_MASK) {
 			case STATUS_PCIXSPD_50_66:
 				sc->sc_bus_speed = 66;
 				break;
 			case STATUS_PCIXSPD_66_100:
 				sc->sc_bus_speed = 100;
 				break;
 			case STATUS_PCIXSPD_100_133:
 				sc->sc_bus_speed = 133;
 				break;
 			default:
 				aprint_error_dev(sc->sc_dev,
 				    "unknown PCIXSPD %d; assuming 66MHz\n",
 				    reg & STATUS_PCIXSPD_MASK);
 				sc->sc_bus_speed = 66;
+			}
 		} else
 			sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
 		aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n",
 		    (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed,
 		    (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI");
+	}
 	/*
 	 * Allocate the control data structures, and create and load the
 	 * DMA map for it.
+	 *
 	 * NOTE: All Tx descriptors must be in the same 4G segment of
 	 * memory.  So must Rx descriptors.  We simplify by allocating
 	 * both sets within the same 4G segment.
 	 */
 	WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ?
 	    WM_NTXDESC_82542 : WM_NTXDESC_82544;
 	cdata_size = sc->sc_type < WM_T_82544 ?
 	    sizeof(struct wm_control_data_82542) :
 	    sizeof(struct wm_control_data_82544);
 	if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE,
 				      (bus_size_t) 0x100000000ULL,
 				      &seg, 1, &rseg, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to allocate control data, error = %d\n",
 		    error);
 		goto fail_0;
+	}
 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size,
 				    (void **)&sc->sc_control_data,
 				    BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to map control data, error = %d\n", error);
 		goto fail_1;
+	}
 	if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size,
 , 0, &sc->sc_cddmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to create control data DMA map, error = %d\n",
 		    error);
 		goto fail_2;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
 				     sc->sc_control_data, cdata_size, NULL,
 )) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load control data DMA map, error = %d\n",
 		    error);
 		goto fail_3;
+	}
 	/*
 	 * Create the transmit buffer DMA maps.
 	 */
 	WM_TXQUEUELEN(sc) =
 	    (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
 	    WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
 	for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA,
 					       WM_NTXSEGS, WTX_MAX_LEN, 0, 0,
 					  &sc->sc_txsoft[i].txs_dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to create Tx DMA map %d, error = %d\n",
 			    i, error);
 			goto fail_4;
+		}
+	}
 	/*
 	 * Create the receive buffer DMA maps.
 	 */
 	for (i = 0; i < WM_NRXDESC; i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
 					       MCLBYTES, 0, 0,
 					  &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to create Rx DMA map %d error = %d\n",
 			    i, error);
 			goto fail_5;
+		}
 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
+	}
 	/* clear interesting stat counters */
 	CSR_READ(sc, WMREG_COLC);
 	CSR_READ(sc, WMREG_RXERRC);
 	/*
 	 * Reset the chip to a known state.
 	 */
 	wm_reset(sc);
 	switch (sc->sc_type) {
 	case WM_T_82573:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 		if (wm_check_mng_mode(sc) != 0)
 			wm_get_hw_control(sc);
 		break;
 	default:
 		break;
+	}
 	/*
 	 * Get some information about the EEPROM.
 	 */
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)) {
 		uint32_t flash_size;
 		sc->sc_flags |= WM_F_SWFWHW_SYNC | WM_F_EEPROM_FLASH;
 		memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH);
 		if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0,
 		    &sc->sc_flasht, &sc->sc_flashh, NULL, NULL)) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't map FLASH registers\n");
 			return;
+		}
 		flash_size = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);
 		sc->sc_ich8_flash_base = (flash_size & ICH_GFPREG_BASE_MASK) *
 						ICH_FLASH_SECTOR_SIZE;
 		sc->sc_ich8_flash_bank_size =
 			((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
 		sc->sc_ich8_flash_bank_size -=
 			(flash_size & ICH_GFPREG_BASE_MASK);
 		sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 		sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t);
 	} else if (sc->sc_type == WM_T_80003)
 		sc->sc_flags |= WM_F_EEPROM_EERDEEWR |  WM_F_SWFW_SYNC;
 	else if (sc->sc_type == WM_T_82573)
 		sc->sc_flags |= WM_F_EEPROM_EERDEEWR;
 	else if (sc->sc_type == WM_T_82574)
 		sc->sc_flags |= WM_F_EEPROM_EERDEEWR;
 	else if (sc->sc_type > WM_T_82544)
 		sc->sc_flags |= WM_F_EEPROM_HANDSHAKE;
 	if (sc->sc_type <= WM_T_82544)
 		sc->sc_ee_addrbits = 6;
 	else if (sc->sc_type <= WM_T_82546_3) {
 		reg = CSR_READ(sc, WMREG_EECD);
 		if (reg & EECD_EE_SIZE)
 			sc->sc_ee_addrbits = 8;
 		else
 			sc->sc_ee_addrbits = 6;
 	} else if (sc->sc_type <= WM_T_82547_2) {
 		reg = CSR_READ(sc, WMREG_EECD);
 		if (reg & EECD_EE_TYPE) {
 			sc->sc_flags |= WM_F_EEPROM_SPI;
 			sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
 		} else
 			sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6;
 	} else if ((sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574) &&
 	    (wm_is_onboard_nvm_eeprom(sc) == 0)) {
 		sc->sc_flags |= WM_F_EEPROM_FLASH;
 	} else {
 		/* Assume everything else is SPI. */
 		reg = CSR_READ(sc, WMREG_EECD);
 		sc->sc_flags |= WM_F_EEPROM_SPI;
 		sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
+	}
 	/*
 	 * Defer printing the EEPROM type until after verifying the checksum
 	 * This allows the EEPROM type to be printed correctly in the case
 	 * that no EEPROM is attached.
 	 */
 	/*
 	 * Validate the EEPROM checksum. If the checksum fails, flag this for
 	 * later, so we can fail future reads from the EEPROM.
 	 */
 	if (wm_validate_eeprom_checksum(sc)) {
 		/*
 		 * Read twice again because some PCI-e parts fail the first
 		 * check due to the link being in sleep state.
 		 */
 		if (wm_validate_eeprom_checksum(sc))
 			sc->sc_flags |= WM_F_EEPROM_INVALID;
+	}
 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
 		aprint_verbose_dev(sc->sc_dev, "No EEPROM\n");
 	else if (sc->sc_flags & WM_F_EEPROM_FLASH) {
 		aprint_verbose_dev(sc->sc_dev, "FLASH\n");
 	} else {
 		if (sc->sc_flags & WM_F_EEPROM_SPI)
 			eetype = "SPI";
 		else
 			eetype = "MicroWire";
 		aprint_verbose_dev(sc->sc_dev,
 		    "%u word (%d address bits) %s EEPROM\n",
 U << sc->sc_ee_addrbits,
 		    sc->sc_ee_addrbits, eetype);
+	}
 	/*
 	 * Read the Ethernet address from the EEPROM, if not first found
 	 * in device properties.
 	 */
 	ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-addr");
 	if (ea != NULL) {
 		KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
 		KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
 		memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
 	} else {
 		if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR,
 		    sizeof(myea) / sizeof(myea[0]), myea)) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to read Ethernet address\n");
 			return;
+		}
 		enaddr[0] = myea[0] & 0xff;
 		enaddr[1] = myea[0] >> 8;
 		enaddr[2] = myea[1] & 0xff;
 		enaddr[3] = myea[1] >> 8;
 		enaddr[4] = myea[2] & 0xff;
 		enaddr[5] = myea[2] >> 8;
+	}
 	/*
 	 * Toggle the LSB of the MAC address on the second port
 	 * of the dual port controller.
 	 */
 	if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3
 	    || sc->sc_type ==  WM_T_82571 || sc->sc_type == WM_T_80003) {
 		if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1)
 			enaddr[5] ^= 1;
+	}
 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
 	    ether_sprintf(enaddr));
 	/*
 	 * Read the config info from the EEPROM, and set up various
 	 * bits in the control registers based on their contents.
 	 */
 	pn = prop_dictionary_get(device_properties(sc->sc_dev),
 				 "i82543-cfg1");
 	if (pn != NULL) {
 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
 		cfg1 = (uint16_t) prop_number_integer_value(pn);
 	} else {
 		if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) {
 			aprint_error_dev(sc->sc_dev, "unable to read CFG1\n");
 			return;
+		}
+	}
 	pn = prop_dictionary_get(device_properties(sc->sc_dev),
 				 "i82543-cfg2");
 	if (pn != NULL) {
 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
 		cfg2 = (uint16_t) prop_number_integer_value(pn);
 	} else {
 		if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) {
 			aprint_error_dev(sc->sc_dev, "unable to read CFG2\n");
 			return;
+		}
+	}
 	if (sc->sc_type >= WM_T_82544) {
 		pn = prop_dictionary_get(device_properties(sc->sc_dev),
 					 "i82543-swdpin");
 		if (pn != NULL) {
 			KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
 			swdpin = (uint16_t) prop_number_integer_value(pn);
 		} else {
 			if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) {
 				aprint_error_dev(sc->sc_dev,
 				    "unable to read SWDPIN\n");
 				return;
+			}
+		}
+	}
 	if (cfg1 & EEPROM_CFG1_ILOS)
 		sc->sc_ctrl |= CTRL_ILOS;
 	if (sc->sc_type >= WM_T_82544) {
 		sc->sc_ctrl |=
 		    ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
 		    CTRL_SWDPIO_SHIFT;
 		sc->sc_ctrl |=
 		    ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
 		    CTRL_SWDPINS_SHIFT;
 	} else {
 		sc->sc_ctrl |=
 		    ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) <<
 		    CTRL_SWDPIO_SHIFT;
+	}
 #if 0
 	if (sc->sc_type >= WM_T_82544) {
 		if (cfg1 & EEPROM_CFG1_IPS0)
 			sc->sc_ctrl_ext |= CTRL_EXT_IPS;
 		if (cfg1 & EEPROM_CFG1_IPS1)
 			sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
 		sc->sc_ctrl_ext |=
 		    ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
 		    CTRL_EXT_SWDPIO_SHIFT;
 		sc->sc_ctrl_ext |=
 		    ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
 		    CTRL_EXT_SWDPINS_SHIFT;
 	} else {
 		sc->sc_ctrl_ext |=
 		    ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) <<
 		    CTRL_EXT_SWDPIO_SHIFT;
+	}
 #endif
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 #if 0
 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
 #endif
 	/*
 	 * Set up some register offsets that are different between
 	 * the i82542 and the i82543 and later chips.
 	 */
 	if (sc->sc_type < WM_T_82543) {
 		sc->sc_rdt_reg = WMREG_OLD_RDT0;
 		sc->sc_tdt_reg = WMREG_OLD_TDT;
 	} else {
 		sc->sc_rdt_reg = WMREG_RDT;
 		sc->sc_tdt_reg = WMREG_TDT;
+	}
 	/*
 	 * Determine if we're TBI or GMII mode, and initialize the
 	 * media structures accordingly.
 	 */
 	if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
 	    || sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574) {
 		/* STATUS_TBIMODE reserved/reused, can't rely on it */
 		wm_gmii_mediainit(sc);
 	} else if (sc->sc_type < WM_T_82543 ||
 	    (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
 		if (wmp->wmp_flags & WMP_F_1000T)
 			aprint_error_dev(sc->sc_dev,
 			    "WARNING: TBIMODE set on 1000BASE-T product!\n");
 		wm_tbi_mediainit(sc);
 	} else {
 		if (wmp->wmp_flags & WMP_F_1000X)
 			aprint_error_dev(sc->sc_dev,
 			    "WARNING: TBIMODE clear on 1000BASE-X product!\n");
 		wm_gmii_mediainit(sc);
+	}
 	ifp = &sc->sc_ethercom.ec_if;
 	xname = device_xname(sc->sc_dev);
 	strlcpy(ifp->if_xname, xname, IFNAMSIZ);
 	ifp->if_softc = sc;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_ioctl = wm_ioctl;
 	ifp->if_start = wm_start;
 	ifp->if_watchdog = wm_watchdog;
 	ifp->if_init = wm_init;
 	ifp->if_stop = wm_stop;
 	IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN));
 	IFQ_SET_READY(&ifp->if_snd);
 	if (sc->sc_type != WM_T_82573 && sc->sc_type != WM_T_82574 &&
 	    sc->sc_type != WM_T_ICH8)
 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 	/*
 	 * If we're a i82543 or greater, we can support VLANs.
 	 */
 	if (sc->sc_type >= WM_T_82543)
 		sc->sc_ethercom.ec_capabilities |=
-		    ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */;
+		    ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
 	/*
 	 * We can perform TCPv4 and UDPv4 checkums in-bound.  Only
 	 * on i82543 and later.
 	 */
 	if (sc->sc_type >= WM_T_82543) {
 		ifp->if_capabilities |=
 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
 		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
 		    IFCAP_CSUM_TCPv6_Tx |
 		    IFCAP_CSUM_UDPv6_Tx;
+	}
 	/*
 	 * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL.
+	 *
 	 *	82541GI (8086:1076) ... no
 	 *	82572EI (8086:10b9) ... yes
 	 */
 	if (sc->sc_type >= WM_T_82571) {
 		ifp->if_capabilities |=
 		    IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx;
+	}
 	/*
 	 * If we're a i82544 or greater (except i82547), we can do
 	 * TCP segmentation offload.
 	 */
 	if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) {
 		ifp->if_capabilities |= IFCAP_TSOv4;
+	}
 	if (sc->sc_type >= WM_T_82571) {
 		ifp->if_capabilities |= IFCAP_TSOv6;
+	}
 	/*
 	 * Attach the interface.
 	 */
 	if_attach(ifp);
 	ether_ifattach(ifp, enaddr);
 #if NRND > 0
 	rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, 0);
 #endif
 #ifdef WM_EVENT_COUNTERS
 	/* Attach event counters. */
 	evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC,
 	    NULL, xname, "txsstall");
 	evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC,
 	    NULL, xname, "txdstall");
 	evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC,
 	    NULL, xname, "txfifo_stall");
 	evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR,
 	    NULL, xname, "txdw");
 	evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR,
 	    NULL, xname, "txqe");
 	evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
 	    NULL, xname, "rxintr");
 	evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR,
 	    NULL, xname, "linkintr");
 	evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,
 	    NULL, xname, "rxipsum");
 	evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC,
 	    NULL, xname, "rxtusum");
 	evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
 	    NULL, xname, "txipsum");
 	evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC,
 	    NULL, xname, "txtusum");
 	evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC,
 	    NULL, xname, "txtusum6");
 	evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC,
 	    NULL, xname, "txtso");
 	evcnt_attach_dynamic(&sc->sc_ev_txtso6, EVCNT_TYPE_MISC,
 	    NULL, xname, "txtso6");
 	evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC,
 	    NULL, xname, "txtsopain");
 	for (i = 0; i < WM_NTXSEGS; i++) {
 		sprintf(wm_txseg_evcnt_names[i], "txseg%d", i);
 		evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC,
 		    NULL, xname, wm_txseg_evcnt_names[i]);
+	}
 	evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC,
 	    NULL, xname, "txdrop");
 	evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC,
 	    NULL, xname, "tu");
 	evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC,
 	    NULL, xname, "tx_xoff");
 	evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC,
 	    NULL, xname, "tx_xon");
 	evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC,
 	    NULL, xname, "rx_xoff");
 	evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC,
 	    NULL, xname, "rx_xon");
 	evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC,
 	    NULL, xname, "rx_macctl");
 #endif /* WM_EVENT_COUNTERS */
 	if (!pmf_device_register(self, NULL, NULL))
 		aprint_error_dev(self, "couldn't establish power handler\n");
 	else
 		pmf_class_network_register(self, ifp);
 	return;
 	/*
 	 * Free any resources we've allocated during the failed attach
 	 * attempt.  Do this in reverse order and fall through.
 	 */
  fail_5:
 	for (i = 0; i < WM_NRXDESC; i++) {
 		if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    sc->sc_rxsoft[i].rxs_dmamap);
+	}
  fail_4:
 	for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
 		if (sc->sc_txsoft[i].txs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    sc->sc_txsoft[i].txs_dmamap);
+	}
 	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
  fail_3:
 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
  fail_2:
 	bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
 	    cdata_size);
  fail_1:
 	bus_dmamem_free(sc->sc_dmat, &seg, rseg);
  fail_0:
 	return;
+}
 /*
  * wm_tx_offload:
+ *
  *	Set up TCP/IP checksumming parameters for the
  *	specified packet.
  */
 static int
 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp,
     uint8_t *fieldsp)
+{
 	struct mbuf *m0 = txs->txs_mbuf;
 	struct livengood_tcpip_ctxdesc *t;
 	uint32_t ipcs, tucs, cmd, cmdlen, seg;
 	uint32_t ipcse;
 	struct ether_header *eh;
 	int offset, iphl;
 	uint8_t fields;
 	/*
 	 * XXX It would be nice if the mbuf pkthdr had offset
 	 * fields for the protocol headers.
 	 */
 	eh = mtod(m0, struct ether_header *);
 	switch (htons(eh->ether_type)) {
 	case ETHERTYPE_IP:
 	case ETHERTYPE_IPV6:
 		offset = ETHER_HDR_LEN;
 		break;
 	case ETHERTYPE_VLAN:
 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 		break;
 	default:
 		/*
 		 * Don't support this protocol or encapsulation.
 		 */
 		*fieldsp = 0;
 		*cmdp = 0;
 		return (0);
+	}
 	if ((m0->m_pkthdr.csum_flags &
 	    (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) {
 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
 	} else {
 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
+	}
 	ipcse = offset + iphl - 1;
 	cmd = WTX_CMD_DEXT | WTX_DTYP_D;
 	cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE;
 	seg = 0;
 	fields = 0;
 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
 		int hlen = offset + iphl;
 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
 		if (__predict_false(m0->m_len <
 				    (hlen + sizeof(struct tcphdr)))) {
 			/*
 			 * TCP/IP headers are not in the first mbuf; we need
 			 * to do this the slow and painful way.  Let's just
 			 * hope this doesn't happen very often.
 			 */
 			struct tcphdr th;
 			WM_EVCNT_INCR(&sc->sc_ev_txtsopain);
 			m_copydata(m0, hlen, sizeof(th), &th);
 			if (v4) {
 				struct ip ip;
 				m_copydata(m0, offset, sizeof(ip), &ip);
 				ip.ip_len = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip, ip_len),
 				    sizeof(ip.ip_len), &ip.ip_len);
 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr ip6;
 				m_copydata(m0, offset, sizeof(ip6), &ip6);
 				ip6.ip6_plen = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip6_hdr, ip6_plen),
 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
 			    sizeof(th.th_sum), &th.th_sum);
 			hlen += th.th_off << 2;
 		} else {
 			/*
 			 * TCP/IP headers are in the first mbuf; we can do
 			 * this the easy way.
 			 */
 			struct tcphdr *th;
 			if (v4) {
 				struct ip *ip =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip->ip_len = 0;
 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr *ip6 =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip6->ip6_plen = 0;
 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			hlen += th->th_off << 2;
+		}
 		if (v4) {
 			WM_EVCNT_INCR(&sc->sc_ev_txtso);
 			cmdlen |= WTX_TCPIP_CMD_IP;
 		} else {
 			WM_EVCNT_INCR(&sc->sc_ev_txtso6);
 			ipcse = 0;
+		}
 		cmd |= WTX_TCPIP_CMD_TSE;
 		cmdlen |= WTX_TCPIP_CMD_TSE |
 		    WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen);
 		seg = WTX_TCPIP_SEG_HDRLEN(hlen) |
 		    WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz);
+	}
 	/*
 	 * NOTE: Even if we're not using the IP or TCP/UDP checksum
 	 * offload feature, if we load the context descriptor, we
 	 * MUST provide valid values for IPCSS and TUCSS fields.
 	 */
 	ipcs = WTX_TCPIP_IPCSS(offset) |
 	    WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
 	    WTX_TCPIP_IPCSE(ipcse);
 	if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) {
 		WM_EVCNT_INCR(&sc->sc_ev_txipsum);
 		fields |= WTX_IXSM;
+	}
 	offset += iphl;
 	if (m0->m_pkthdr.csum_flags &
 	    (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) {
 		WM_EVCNT_INCR(&sc->sc_ev_txtusum);
 		fields |= WTX_TXSM;
 		tucs = WTX_TCPIP_TUCSS(offset) |
 		    WTX_TCPIP_TUCSO(offset +
 		    M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
 	} else if ((m0->m_pkthdr.csum_flags &
 	    (M_CSUM_TCPv6|M_CSUM_UDPv6|M_CSUM_TSOv6)) != 0) {
 		WM_EVCNT_INCR(&sc->sc_ev_txtusum6);
 		fields |= WTX_TXSM;
 		tucs = WTX_TCPIP_TUCSS(offset) |
 		    WTX_TCPIP_TUCSO(offset +
 		    M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
 	} else {
 		/* Just initialize it to a valid TCP context. */
 		tucs = WTX_TCPIP_TUCSS(offset) |
 		    WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) |
 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
+	}
 	/* Fill in the context descriptor. */
 	t = (struct livengood_tcpip_ctxdesc *)
 	    &sc->sc_txdescs[sc->sc_txnext];
 	t->tcpip_ipcs = htole32(ipcs);
 	t->tcpip_tucs = htole32(tucs);
 	t->tcpip_cmdlen = htole32(cmdlen);
 	t->tcpip_seg = htole32(seg);
 	WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE);
 	sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext);
 	txs->txs_ndesc++;
 	*cmdp = cmd;
 	*fieldsp = fields;
 	return (0);
+}
 static void
 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0)
+{
 	struct mbuf *m;
 	int i;
 	log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev));
 	for (m = m0, i = 0; m != NULL; m = m->m_next, i++)
 		log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, "
 		    "m_flags = 0x%08x\n", device_xname(sc->sc_dev),
 		    m->m_data, m->m_len, m->m_flags);
 	log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev),
 	    i, i == 1 ? "" : "s");
+}
 /*
  * wm_82547_txfifo_stall:
+ *
  *	Callout used to wait for the 82547 Tx FIFO to drain,
  *	reset the FIFO pointers, and restart packet transmission.
  */
 static void
 wm_82547_txfifo_stall(void *arg)
+{
 	struct wm_softc *sc = arg;
 	int s;
 	s = splnet();
 	if (sc->sc_txfifo_stall) {
 		if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) &&
 		    CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
 		    CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
 			/*
 			 * Packets have drained.  Stop transmitter, reset
 			 * FIFO pointers, restart transmitter, and kick
 			 * the packet queue.
 			 */
 			uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
 			CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN);
 			CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr);
 			CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr);
 			CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr);
 			CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr);
 			CSR_WRITE(sc, WMREG_TCTL, tctl);
 			CSR_WRITE_FLUSH(sc);
 			sc->sc_txfifo_head = 0;
 			sc->sc_txfifo_stall = 0;
 			wm_start(&sc->sc_ethercom.ec_if);
 		} else {
 			/*
 			 * Still waiting for packets to drain; try again in
 			 * another tick.
 			 */
 			callout_schedule(&sc->sc_txfifo_ch, 1);
+		}
+	}
 	splx(s);
+}
 /*
  * wm_82547_txfifo_bugchk:
+ *
  *	Check for bug condition in the 82547 Tx FIFO.  We need to
  *	prevent enqueueing a packet that would wrap around the end
  *	if the Tx FIFO ring buffer, otherwise the chip will croak.
+ *
  *	We do this by checking the amount of space before the end
  *	of the Tx FIFO buffer.  If the packet will not fit, we "stall"
  *	the Tx FIFO, wait for all remaining packets to drain, reset
  *	the internal FIFO pointers to the beginning, and restart
  *	transmission on the interface.
  */
 #define	WM_FIFO_HDR		0x10
 #define	WM_82547_PAD_LEN	0x3e0
 static int
 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0)
+{
 	int space = sc->sc_txfifo_size - sc->sc_txfifo_head;
 	int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR);
 	/* Just return if already stalled. */
 	if (sc->sc_txfifo_stall)
 		return (1);
 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
 		/* Stall only occurs in half-duplex mode. */
 		goto send_packet;
+	}
 	if (len >= WM_82547_PAD_LEN + space) {
 		sc->sc_txfifo_stall = 1;
 		callout_schedule(&sc->sc_txfifo_ch, 1);
 		return (1);
+	}
  send_packet:
 	sc->sc_txfifo_head += len;
 	if (sc->sc_txfifo_head >= sc->sc_txfifo_size)
 		sc->sc_txfifo_head -= sc->sc_txfifo_size;
 	return (0);
+}
 /*
  * wm_start:		[ifnet interface function]
+ *
  *	Start packet transmission on the interface.
  */
 static void
 wm_start(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct mbuf *m0;
 	struct m_tag *mtag;
 	struct wm_txsoft *txs;
 	bus_dmamap_t dmamap;
 	int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso;
 	bus_addr_t curaddr;
 	bus_size_t seglen, curlen;
 	uint32_t cksumcmd;
 	uint8_t cksumfields;
 	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
 		return;
 	/*
 	 * Remember the previous number of free descriptors.
 	 */
 	ofree = sc->sc_txfree;
 	/*
 	 * Loop through the send queue, setting up transmit descriptors
 	 * until we drain the queue, or use up all available transmit
 	 * descriptors.
 	 */
 	for (;;) {
 		/* Grab a packet off the queue. */
 		IFQ_POLL(&ifp->if_snd, m0);
 		if (m0 == NULL)
 			break;
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: have packet to transmit: %p\n",
 		    device_xname(sc->sc_dev), m0));
 		/* Get a work queue entry. */
 		if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) {
 			wm_txintr(sc);
 			if (sc->sc_txsfree == 0) {
 				DPRINTF(WM_DEBUG_TX,
 				    ("%s: TX: no free job descriptors\n",
 					device_xname(sc->sc_dev)));
 				WM_EVCNT_INCR(&sc->sc_ev_txsstall);
 				break;
+			}
+		}
 		txs = &sc->sc_txsoft[sc->sc_txsnext];
 		dmamap = txs->txs_dmamap;
 		use_tso = (m0->m_pkthdr.csum_flags &
 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0;
 		/*
 		 * So says the Linux driver:
 		 * The controller does a simple calculation to make sure
 		 * there is enough room in the FIFO before initiating the
 		 * DMA for each buffer.  The calc is:
 		 *	4 = ceil(buffer len / MSS)
 		 * To make sure we don't overrun the FIFO, adjust the max
 		 * buffer len if the MSS drops.
 		 */
 		dmamap->dm_maxsegsz =
 		    (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN)
 		    ? m0->m_pkthdr.segsz << 2
 		    : WTX_MAX_LEN;
 		/*
 		 * Load the DMA map.  If this fails, the packet either
 		 * didn't fit in the allotted number of segments, or we
 		 * were short on resources.  For the too-many-segments
 		 * case, we simply report an error and drop the packet,
 		 * since we can't sanely copy a jumbo packet to a single
 		 * buffer.
 		 */
 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
 		    BUS_DMA_WRITE|BUS_DMA_NOWAIT);
 		if (error) {
 			if (error == EFBIG) {
 				WM_EVCNT_INCR(&sc->sc_ev_txdrop);
 				log(LOG_ERR, "%s: Tx packet consumes too many "
 				    "DMA segments, dropping...\n",
 				    device_xname(sc->sc_dev));
 				IFQ_DEQUEUE(&ifp->if_snd, m0);
 				wm_dump_mbuf_chain(sc, m0);
 				m_freem(m0);
 				continue;
+			}
 			/*
 			 * Short on resources, just stop for now.
 			 */
 			DPRINTF(WM_DEBUG_TX,
 			    ("%s: TX: dmamap load failed: %d\n",
 			    device_xname(sc->sc_dev), error));
 			break;
+		}
 		segs_needed = dmamap->dm_nsegs;
 		if (use_tso) {
 			/* For sentinel descriptor; see below. */
 			segs_needed++;
+		}
 		/*
 		 * Ensure we have enough descriptors free to describe
 		 * the packet.  Note, we always reserve one descriptor
 		 * at the end of the ring due to the semantics of the
 		 * TDT register, plus one more in the event we need
 		 * to load offload context.
 		 */
 		if (segs_needed > sc->sc_txfree - 2) {
 			/*
 			 * Not enough free descriptors to transmit this
 			 * packet.  We haven't committed anything yet,
 			 * so just unload the DMA map, put the packet
 			 * pack on the queue, and punt.  Notify the upper
 			 * layer that there are no more slots left.
 			 */
 			DPRINTF(WM_DEBUG_TX,
 			    ("%s: TX: need %d (%d) descriptors, have %d\n",
 			    device_xname(sc->sc_dev), dmamap->dm_nsegs,
 			    segs_needed, sc->sc_txfree - 1));
 			ifp->if_flags |= IFF_OACTIVE;
 			bus_dmamap_unload(sc->sc_dmat, dmamap);
 			WM_EVCNT_INCR(&sc->sc_ev_txdstall);
 			break;
+		}
 		/*
 		 * Check for 82547 Tx FIFO bug.  We need to do this
 		 * once we know we can transmit the packet, since we
 		 * do some internal FIFO space accounting here.
 		 */
 		if (sc->sc_type == WM_T_82547 &&
 		    wm_82547_txfifo_bugchk(sc, m0)) {
 			DPRINTF(WM_DEBUG_TX,
 			    ("%s: TX: 82547 Tx FIFO bug detected\n",
 			    device_xname(sc->sc_dev)));
 			ifp->if_flags |= IFF_OACTIVE;
 			bus_dmamap_unload(sc->sc_dmat, dmamap);
 			WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall);
 			break;
+		}
 		IFQ_DEQUEUE(&ifp->if_snd, m0);
 		/*
 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
 		 */
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: packet has %d (%d) DMA segments\n",
 		    device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
 		WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]);
 		/*
 		 * Store a pointer to the packet so that we can free it
 		 * later.
+		 *
 		 * Initially, we consider the number of descriptors the
 		 * packet uses the number of DMA segments.  This may be
 		 * incremented by 1 if we do checksum offload (a descriptor
 		 * is used to set the checksum context).
 		 */
 		txs->txs_mbuf = m0;
 		txs->txs_firstdesc = sc->sc_txnext;
 		txs->txs_ndesc = segs_needed;
 		/* Set up offload parameters for this packet. */
 		if (m0->m_pkthdr.csum_flags &
 		    (M_CSUM_TSOv4|M_CSUM_TSOv6|
 		    M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
 		    M_CSUM_TCPv6|M_CSUM_UDPv6)) {
 			if (wm_tx_offload(sc, txs, &cksumcmd,
 					  &cksumfields) != 0) {
 				/* Error message already displayed. */
 				bus_dmamap_unload(sc->sc_dmat, dmamap);
 				continue;
+			}
 		} else {
 			cksumcmd = 0;
 			cksumfields = 0;
+		}
 		cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS;
 		/* Sync the DMA map. */
 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
 		    BUS_DMASYNC_PREWRITE);
 		/*
 		 * Initialize the transmit descriptor.
 		 */
 		for (nexttx = sc->sc_txnext, seg = 0;
 		     seg < dmamap->dm_nsegs; seg++) {
 			for (seglen = dmamap->dm_segs[seg].ds_len,
 			     curaddr = dmamap->dm_segs[seg].ds_addr;
 			     seglen != 0;
 			     curaddr += curlen, seglen -= curlen,
 			     nexttx = WM_NEXTTX(sc, nexttx)) {
 				curlen = seglen;
 				/*
 				 * So says the Linux driver:
 				 * Work around for premature descriptor
 				 * write-backs in TSO mode.  Append a
 				 * 4-byte sentinel descriptor.
 				 */
 				if (use_tso &&
 				    seg == dmamap->dm_nsegs - 1 &&
 				    curlen > 8)
 					curlen -= 4;
 				wm_set_dma_addr(
 				    &sc->sc_txdescs[nexttx].wtx_addr,
 				    curaddr);
 				sc->sc_txdescs[nexttx].wtx_cmdlen =
 				    htole32(cksumcmd | curlen);
 				sc->sc_txdescs[nexttx].wtx_fields.wtxu_status =
 ;
 				sc->sc_txdescs[nexttx].wtx_fields.wtxu_options =
 				    cksumfields;
 				sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0;
 				lasttx = nexttx;
 				DPRINTF(WM_DEBUG_TX,
 				    ("%s: TX: desc %d: low 0x%08lx, "
 				     "len 0x%04x\n",
 				    device_xname(sc->sc_dev), nexttx,
 				    curaddr & 0xffffffffUL, (unsigned)curlen));
+			}
+		}
 		KASSERT(lasttx != -1);
 		/*
 		 * Set up the command byte on the last descriptor of
 		 * the packet.  If we're in the interrupt delay window,
 		 * delay the interrupt.
 		 */
 		sc->sc_txdescs[lasttx].wtx_cmdlen |=
 		    htole32(WTX_CMD_EOP | WTX_CMD_RS);
 		/*
 		 * If VLANs are enabled and the packet has a VLAN tag, set
 		 * up the descriptor to encapsulate the packet for us.
+		 *
 		 * This is only valid on the last descriptor of the packet.
 		 */
 		if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
 			sc->sc_txdescs[lasttx].wtx_cmdlen |=
 			    htole32(WTX_CMD_VLE);
 			sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan
 			    = htole16(VLAN_TAG_VALUE(mtag) & 0xffff);
+		}
 		txs->txs_lastdesc = lasttx;
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: desc %d: cmdlen 0x%08x\n",
 		    device_xname(sc->sc_dev),
 		    lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen)));
 		/* Sync the descriptors we're using. */
 		WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc,
 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 		/* Give the packet to the chip. */
 		CSR_WRITE(sc, sc->sc_tdt_reg, nexttx);
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: finished transmitting packet, job %d\n",
 		    device_xname(sc->sc_dev), sc->sc_txsnext));
 		/* Advance the tx pointer. */
 		sc->sc_txfree -= txs->txs_ndesc;
 		sc->sc_txnext = nexttx;
 		sc->sc_txsfree--;
 		sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext);
 #if NBPFILTER > 0
 		/* Pass the packet to any BPF listeners. */
 		if (ifp->if_bpf)
 			bpf_mtap(ifp->if_bpf, m0);
 #endif /* NBPFILTER > 0 */
+	}
 	if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) {
 		/* No more slots; notify upper layer. */
 		ifp->if_flags |= IFF_OACTIVE;
+	}
 	if (sc->sc_txfree != ofree) {
 		/* Set a watchdog timer in case the chip flakes out. */
 		ifp->if_timer = 5;
+	}
+}
 /*
  * wm_watchdog:		[ifnet interface function]
+ *
  *	Watchdog timer handler.
  */
 static void
 wm_watchdog(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	/*
 	 * Since we're using delayed interrupts, sweep up
 	 * before we report an error.
 	 */
 	wm_txintr(sc);
 	if (sc->sc_txfree != WM_NTXDESC(sc)) {
 		log(LOG_ERR,
 		    "%s: device timeout (txfree %d txsfree %d txnext %d)\n",
 		    device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree,
 		    sc->sc_txnext);
 		ifp->if_oerrors++;
 		/* Reset the interface. */
 		(void) wm_init(ifp);
+	}
 	/* Try to get more packets going. */
 	wm_start(ifp);
+}
 /*
  * wm_ioctl:		[ifnet interface function]
+ *
  *	Handle control requests from the operator.
  */
 static int
 wm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct ifreq *ifr = (struct ifreq *) data;
 	int s, error;
 	s = splnet();
 	switch (cmd) {
 	case SIOCSIFMEDIA:
 	case SIOCGIFMEDIA:
 		/* Flow control requires full-duplex mode. */
 		if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
 		    (ifr->ifr_media & IFM_FDX) == 0)
 			ifr->ifr_media &= ~IFM_ETH_FMASK;
 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
 			if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
 				/* We can do both TXPAUSE and RXPAUSE. */
 				ifr->ifr_media |=
 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
+			}
 			sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
+		}
 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
 		break;
 	default:
 		if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
 			break;
 		error = 0;
 		if (cmd == SIOCSIFCAP)
 			error = (*ifp->if_init)(ifp);
 		else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
+			;
 		else if (ifp->if_flags & IFF_RUNNING) {
 			/*
 			 * Multicast list has changed; set the hardware filter
 			 * accordingly.
 			 */
 			wm_set_filter(sc);
+		}
 		break;
+	}
 	/* Try to get more packets going. */
 	wm_start(ifp);
 	splx(s);
 	return (error);
+}
 /*
  * wm_intr:
+ *
  *	Interrupt service routine.
  */
 static int
 wm_intr(void *arg)
+{
 	struct wm_softc *sc = arg;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	uint32_t icr;
 	int handled = 0;
 	while (1 /* CONSTCOND */) {
 		icr = CSR_READ(sc, WMREG_ICR);
 		if ((icr & sc->sc_icr) == 0)
 			break;
 #if 0 /*NRND > 0*/
 		if (RND_ENABLED(&sc->rnd_source))
 			rnd_add_uint32(&sc->rnd_source, icr);
 #endif
 		handled = 1;
 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
 		if (icr & (ICR_RXDMT0|ICR_RXT0)) {
 			DPRINTF(WM_DEBUG_RX,
 			    ("%s: RX: got Rx intr 0x%08x\n",
 			    device_xname(sc->sc_dev),
 			    icr & (ICR_RXDMT0|ICR_RXT0)));
 			WM_EVCNT_INCR(&sc->sc_ev_rxintr);
+		}
 #endif
 		wm_rxintr(sc);
 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
 		if (icr & ICR_TXDW) {
 			DPRINTF(WM_DEBUG_TX,
 			    ("%s: TX: got TXDW interrupt\n",
 			    device_xname(sc->sc_dev)));
 			WM_EVCNT_INCR(&sc->sc_ev_txdw);
+		}
 #endif
 		wm_txintr(sc);
 		if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) {
 			WM_EVCNT_INCR(&sc->sc_ev_linkintr);
 			wm_linkintr(sc, icr);
+		}
 		if (icr & ICR_RXO) {
 			ifp->if_ierrors++;
 #if defined(WM_DEBUG)
 			log(LOG_WARNING, "%s: Receive overrun\n",
 			    device_xname(sc->sc_dev));
 #endif /* defined(WM_DEBUG) */
+		}
+	}
 	if (handled) {
 		/* Try to get more packets going. */
 		wm_start(ifp);
+	}
 	return (handled);
+}
 /*
  * wm_txintr:
+ *
  *	Helper; handle transmit interrupts.
  */
 static void
 wm_txintr(struct wm_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct wm_txsoft *txs;
 	uint8_t status;
 	int i;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	/*
 	 * Go through the Tx list and free mbufs for those
 	 * frames which have been transmitted.
 	 */
 	for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc);
 	     i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) {
 		txs = &sc->sc_txsoft[i];
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: checking job %d\n", device_xname(sc->sc_dev), i));
 		WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc,
 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 		status =
 		    sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status;
 		if ((status & WTX_ST_DD) == 0) {
 			WM_CDTXSYNC(sc, txs->txs_lastdesc, 1,
 			    BUS_DMASYNC_PREREAD);
 			break;
+		}
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: job %d done: descs %d..%d\n",
 		    device_xname(sc->sc_dev), i, txs->txs_firstdesc,
 		    txs->txs_lastdesc));
 		/*
 		 * XXX We should probably be using the statistics
 		 * XXX registers, but I don't know if they exist
 		 * XXX on chips before the i82544.
 		 */
 #ifdef WM_EVENT_COUNTERS
 		if (status & WTX_ST_TU)
 			WM_EVCNT_INCR(&sc->sc_ev_tu);
 #endif /* WM_EVENT_COUNTERS */
 		if (status & (WTX_ST_EC|WTX_ST_LC)) {
 			ifp->if_oerrors++;
 			if (status & WTX_ST_LC)
 				log(LOG_WARNING, "%s: late collision\n",
 				    device_xname(sc->sc_dev));
 			else if (status & WTX_ST_EC) {
 				ifp->if_collisions += 16;
 				log(LOG_WARNING, "%s: excessive collisions\n",
 				    device_xname(sc->sc_dev));
+			}
 		} else
 			ifp->if_opackets++;
 		sc->sc_txfree += txs->txs_ndesc;
 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
 , txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
 		m_freem(txs->txs_mbuf);
 		txs->txs_mbuf = NULL;
+	}
 	/* Update the dirty transmit buffer pointer. */
 	sc->sc_txsdirty = i;
 	DPRINTF(WM_DEBUG_TX,
 	    ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i));
 	/*
 	 * If there are no more pending transmissions, cancel the watchdog
 	 * timer.
 	 */
 	if (sc->sc_txsfree == WM_TXQUEUELEN(sc))
 		ifp->if_timer = 0;
+}
 /*
  * wm_rxintr:
+ *
  *	Helper; handle receive interrupts.
  */