 @@ -1,14 +1,14 @@
-/* $NetBSD: i82596.c,v 1.19 2008/04/04 17:03:42 tsutsui Exp $ */
+/* $NetBSD: i82596.c,v 1.20 2009/05/05 15:47:35 tsutsui Exp $ */
 /*
  * Copyright (c) 2003 Jochen Kunz.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -33,27 +33,27 @@
  * Driver for the Intel i82596CA and i82596DX/SX 10MBit/s Ethernet chips.
+ *
  * It operates the i82596 in 32-Bit Linear Mode, opposed to the old i82586
  * ie(4) driver (src/sys/dev/ic/i82586.c), that degrades the i82596 to
  * i82586 compatibility mode.
+ *
  * Documentation about these chips can be found at
+ *
  *	http://developer.intel.com/design/network/datashts/290218.htm
  *	http://developer.intel.com/design/network/datashts/290219.htm
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i82596.c,v 1.19 2008/04/04 17:03:42 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i82596.c,v 1.20 2009/05/05 15:47:35 tsutsui Exp $");
 /* autoconfig and device stuff */
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/conf.h>
 #include "locators.h"
 #include "ioconf.h"
 /* bus_space / bus_dma etc. */
 #include <sys/bus.h>
 #include <sys/intr.h>
 /* general system data and functions */
 @@ -113,30 +113,48 @@ static void iee_cb_setup(struct iee_soft
  *	chip, wait for the chip to initialize and ACK interrupts that
  *	this may have caused by calling (sc->sc_iee_cmd)(sc, IEE_SCB_ACK);
  * This functions must carefully bus_dmamap_sync() all data they have touched!
+ *
  * sc_mediastatus() and sc_mediachange() are just MD hooks to the according
  * MI functions. The MD frontend may set this pointers to NULL when they
  * are not needed.
+ *
  * sc->sc_type has to be set to I82596_UNKNOWN or I82596_DX or I82596_CA.
  * This is for printing out the correct chip type at attach time only. The
  * MI backend doesn't distinguish different chip types when programming
  * the chip.
+ *
- * sc->sc_flags has to be set to 0 on little endian hardware and to
+ * IEE_NEED_SWAP in sc->sc_flags has to be cleared on little endian hardware
- * IEE_NEED_SWAP on big endian hardware, when endianess conversion is not
+ * and set on big endian hardware, when endianess conversion is not done
- * done by the bus attachment. Usually you need to set IEE_NEED_SWAP
+ * by the bus attachment but done by i82596 chip itself.
- * when IEE_SYSBUS_BE is set in the sysbus byte.
+ * Usually you need to set IEE_NEED_SWAP on big endian machines
  * where the hardware (the LE/~BE pin) is configured as BE mode.
+ *
  * If the chip is configured as BE mode, all 8 bit (byte) and 16 bit (word)
  * entities can be written in big endian. But Rev A chip doesn't support
  * 32 bit (dword) entities with big endian byte ordering, so we have to
  * treat all 32 bit (dword) entities as two 16 bit big endian entities.
  * Rev B and C chips support big endian byte ordering for 32 bit entities,
  * and this new feature is enabled by IEE_SYSBUS_BE in the sysbus byte.
+ *
  * With the IEE_SYSBUS_BE feature, all 32 bit address ponters are
  * treated as true 32 bit entities but the SCB absolute address and
  * statistical counters are still treated as two 16 bit big endian entities,
  * so we have to always swap high and low words for these entities.
  * IEE_SWAP32() should be used for the SCB address and statistical counters,
  * and IEE_SWAPA32() should be used for other 32 bit pointers in the shmem.
+ *
  * IEE_REV_A flag must be set in sc->sc_flags if the IEE_SYSBUS_BE feature
  * is disabled even on big endian machines for the old Rev A chip in backend.
+ *
  * sc->sc_cl_align must be set to 1 or to the cache line size. When set to
  * 1 no special alignment of DMA descriptors is done. If sc->sc_cl_align != 1
  * it forces alignment of the data structures in the shared memory to a multiple
  * of sc->sc_cl_align. This is needed on archs like hp700 that have non DMA
  * I/O coherent caches and are unable to map the shared memory uncachable.
  * (At least pre PA7100LC CPUs are unable to map memory uncachable.)
+ *
  * sc->sc_cl_align MUST BE INITIALIZED BEFORE THE FOLLOWING MACROS ARE USED:
  * SC_* IEE_*_SZ IEE_*_OFF IEE_SHMEM_MAX (shell style glob(3) pattern)
+ *
  * The MD frontend has to allocate a piece of DMA memory at least of
  * IEE_SHMEM_MAX bytes size. All communication with the chip is done via
 @@ -246,46 +264,49 @@ iee_intr(void *intarg)
 			panic("%s: iee_intr: can't load RX DMA map\n",
 			    device_xname(sc->sc_dev));
 		bus_dmamap_sync(sc->sc_dmat, rx_map, 0,
 		    new_mbuf->m_ext.ext_size, BUS_DMASYNC_PREREAD);
 #if NBPFILTER > 0
 		if (ifp->if_bpf != 0)
 			bpf_mtap(ifp->if_bpf, rx_mbuf);
 #endif /* NBPFILTER > 0 */
 		(*ifp->if_input)(ifp, rx_mbuf);
 		ifp->if_ipackets++;
 		sc->sc_rx_mbuf[sc->sc_rx_done] = new_mbuf;
 		rbd->rbd_count = 0;
 		rbd->rbd_size = IEE_RBD_EL | rx_map->dm_segs[0].ds_len;
-		rbd->rbd_rb_addr = rx_map->dm_segs[0].ds_addr;
+		rbd->rbd_rb_addr = IEE_SWAPA32(rx_map->dm_segs[0].ds_addr);
 		sc->sc_rx_done = (sc->sc_rx_done + 1) % IEE_NRFD;
 		rfd = SC_RFD(sc->sc_rx_done);
+	}
 	if ((scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR1
 	    || (scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR2
 	    || (scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR3) {
 		/* Receive Overrun, reinit receive ring buffer. */
 		for (n = 0 ; n < IEE_NRFD ; n++) {
 			SC_RFD(n)->rfd_cmd = IEE_RFD_SF;
-			SC_RFD(n)->rfd_link_addr = IEE_PHYS_SHMEM(IEE_RFD_OFF
+			SC_RFD(n)->rfd_link_addr =
-			    + IEE_RFD_SZ * ((n + 1) % IEE_NRFD));
+			    IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_RFD_OFF
-			SC_RBD(n)->rbd_next_rbd = IEE_PHYS_SHMEM(IEE_RBD_OFF
+			    + IEE_RFD_SZ * ((n + 1) % IEE_NRFD)));
-			    + IEE_RBD_SZ * ((n + 1) % IEE_NRFD));
+			SC_RBD(n)->rbd_next_rbd =
 			    IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_RBD_OFF
 			    + IEE_RBD_SZ * ((n + 1) % IEE_NRFD)));
 			SC_RBD(n)->rbd_size = IEE_RBD_EL |
 			    sc->sc_rx_map[n]->dm_segs[0].ds_len;
 			SC_RBD(n)->rbd_rb_addr =
-			    sc->sc_rx_map[n]->dm_segs[0].ds_addr;
+			    IEE_SWAPA32(sc->sc_rx_map[n]->dm_segs[0].ds_addr);
+		}
-		SC_RFD(0)->rfd_rbd_addr = IEE_PHYS_SHMEM(IEE_RBD_OFF);
+		SC_RFD(0)->rfd_rbd_addr =
 		    IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_RBD_OFF));
 		sc->sc_rx_done = 0;
 		bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, IEE_RFD_OFF,
 		    IEE_RFD_LIST_SZ + IEE_RBD_LIST_SZ, BUS_DMASYNC_PREWRITE);
 		(sc->sc_iee_cmd)(sc, IEE_SCB_RUC_ST);
 		printf("%s: iee_intr: receive ring buffer overrun\n",
 		    device_xname(sc->sc_dev));
+	}
 	if (sc->sc_next_cb != 0
 	    && (SC_CB(sc->sc_next_cb - 1)->cb_status & IEE_CB_C) != 0) {
 		/* CMD list finished */
 		ifp->if_timer = 0;
 		if (sc->sc_next_tbd != 0) {
 @@ -320,53 +341,53 @@ iee_intr(void *intarg)
 				    scb_status, scb_cmd,
 				    ++sc->sc_cmd_err, n, SC_CB(n)->cb_status,
 				    n, SC_CB(n)->cb_cmd);
+		}
 		sc->sc_next_cb = 0;
 		if ((sc->sc_flags & IEE_WANT_MCAST) != 0) {
 			iee_cb_setup(sc, IEE_CB_CMD_MCS | IEE_CB_S | IEE_CB_EL
 			    | IEE_CB_I);
 			(sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE);
 		} else
 			/* Try to get deferred packets going. */
 			iee_start(ifp);
+	}
-	if (IEE_SWAP(SC_SCB->scb_crc_err) != sc->sc_crc_err) {
+	if (IEE_SWAP32(SC_SCB->scb_crc_err) != sc->sc_crc_err) {
-		sc->sc_crc_err = IEE_SWAP(SC_SCB->scb_crc_err);
+		sc->sc_crc_err = IEE_SWAP32(SC_SCB->scb_crc_err);
 		printf("%s: iee_intr: crc_err=%d\n", device_xname(sc->sc_dev),
 		    sc->sc_crc_err);
+	}
-	if (IEE_SWAP(SC_SCB->scb_align_err) != sc->sc_align_err) {
+	if (IEE_SWAP32(SC_SCB->scb_align_err) != sc->sc_align_err) {
-		sc->sc_align_err = IEE_SWAP(SC_SCB->scb_align_err);
+		sc->sc_align_err = IEE_SWAP32(SC_SCB->scb_align_err);
 		printf("%s: iee_intr: align_err=%d\n", device_xname(sc->sc_dev),
 		    sc->sc_align_err);
+	}
-	if (IEE_SWAP(SC_SCB->scb_resource_err) != sc->sc_resource_err) {
+	if (IEE_SWAP32(SC_SCB->scb_resource_err) != sc->sc_resource_err) {
-		sc->sc_resource_err = IEE_SWAP(SC_SCB->scb_resource_err);
+		sc->sc_resource_err = IEE_SWAP32(SC_SCB->scb_resource_err);
 		printf("%s: iee_intr: resource_err=%d\n",
 		    device_xname(sc->sc_dev), sc->sc_resource_err);
+	}
-	if (IEE_SWAP(SC_SCB->scb_overrun_err) != sc->sc_overrun_err) {
+	if (IEE_SWAP32(SC_SCB->scb_overrun_err) != sc->sc_overrun_err) {
-		sc->sc_overrun_err = IEE_SWAP(SC_SCB->scb_overrun_err);
+		sc->sc_overrun_err = IEE_SWAP32(SC_SCB->scb_overrun_err);
 		printf("%s: iee_intr: overrun_err=%d\n",
 		    device_xname(sc->sc_dev), sc->sc_overrun_err);
+	}
-	if (IEE_SWAP(SC_SCB->scb_rcvcdt_err) != sc->sc_rcvcdt_err) {
+	if (IEE_SWAP32(SC_SCB->scb_rcvcdt_err) != sc->sc_rcvcdt_err) {
-		sc->sc_rcvcdt_err = IEE_SWAP(SC_SCB->scb_rcvcdt_err);
+		sc->sc_rcvcdt_err = IEE_SWAP32(SC_SCB->scb_rcvcdt_err);
 		printf("%s: iee_intr: rcvcdt_err=%d\n",
 		    device_xname(sc->sc_dev), sc->sc_rcvcdt_err);
+	}
-	if (IEE_SWAP(SC_SCB->scb_short_fr_err) != sc->sc_short_fr_err) {
+	if (IEE_SWAP32(SC_SCB->scb_short_fr_err) != sc->sc_short_fr_err) {
-		sc->sc_short_fr_err = IEE_SWAP(SC_SCB->scb_short_fr_err);
+		sc->sc_short_fr_err = IEE_SWAP32(SC_SCB->scb_short_fr_err);
 		printf("%s: iee_intr: short_fr_err=%d\n",
 		    device_xname(sc->sc_dev), sc->sc_short_fr_err);
+	}
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 0, IEE_SHMEM_MAX,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	(sc->sc_iee_cmd)(sc, IEE_SCB_ACK);
 	return 1;
+}
 /*
  * How Command Block List Processing is done.
 @@ -466,68 +487,69 @@ iee_cb_setup(struct iee_softc *sc, uint3
 			sc->sc_cf[11] &= ~IEE_CF_11_MCALL;
 		} else {
 			/* disable ALLMULTI and load mcast list */
 			ifp->if_flags &= ~IFF_ALLMULTI;
 			sc->sc_cf[11] |= IEE_CF_11_MCALL;
 			/* Mcast setup may need more then IEE_CB_SZ bytes. */
 			bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map,
 			    IEE_CB_OFF, IEE_CB_LIST_SZ + IEE_TBD_LIST_SZ,
 			    BUS_DMASYNC_PREWRITE);
+		}
 		iee_cb_setup(sc, IEE_CB_CMD_CONF);
 		break;
 	case IEE_CB_CMD_TR:	/* Transmit */
-		cb->cb_transmit.tx_tbd_addr = IEE_PHYS_SHMEM(IEE_TBD_OFF
+		cb->cb_transmit.tx_tbd_addr =
-		    + IEE_TBD_SZ * sc->sc_next_tbd);
+		    IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_TBD_OFF
 		    + IEE_TBD_SZ * sc->sc_next_tbd));
 		cb->cb_cmd |= IEE_CB_SF; /* Always use Flexible Mode. */
 		break;
 	case IEE_CB_CMD_TDR:	/* Time Domain Reflectometry */
 		break;
 	case IEE_CB_CMD_DUMP:	/* Dump */
 		break;
 	case IEE_CB_CMD_DIAG:	/* Diagnose */
 		break;
 	default:
 		/* can't happen */
 		break;
+	}
-	cb->cb_link_addr = IEE_PHYS_SHMEM(IEE_CB_OFF + IEE_CB_SZ *
+	cb->cb_link_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_CB_OFF + IEE_CB_SZ *
-	    (sc->sc_next_cb + 1));
+	    (sc->sc_next_cb + 1)));
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, IEE_CB_OFF
 	    + IEE_CB_SZ * sc->sc_next_cb, IEE_CB_SZ, BUS_DMASYNC_PREWRITE);
 	sc->sc_next_cb++;
 	ifp->if_timer = 5;
 	return;
+}
 void
 iee_attach(struct iee_softc *sc, uint8_t *eth_addr, int *media, int nmedia,
     int defmedia)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	int n;
 	/* Set pointer to Intermediate System Configuration Pointer. */
 	/* Phys. addr. in big endian order. (Big endian as defined by Intel.) */
-	SC_SCP->scp_iscp_addr = IEE_SWAP(IEE_PHYS_SHMEM(IEE_ISCP_OFF));
+	SC_SCP->scp_iscp_addr = IEE_SWAP32(IEE_PHYS_SHMEM(IEE_ISCP_OFF));
 	/* Set pointer to System Control Block. */
 	/* Phys. addr. in big endian order. (Big endian as defined by Intel.) */
-	SC_ISCP->iscp_scb_addr = IEE_SWAP(IEE_PHYS_SHMEM(IEE_SCB_OFF));
+	SC_ISCP->iscp_scb_addr = IEE_SWAP32(IEE_PHYS_SHMEM(IEE_SCB_OFF));
 	/* Set pointer to Receive Frame Area. (physical address) */
-	SC_SCB->scb_rfa_addr = IEE_PHYS_SHMEM(IEE_RFD_OFF);
+	SC_SCB->scb_rfa_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_RFD_OFF));
 	/* Set pointer to Command Block. (physical address) */
-	SC_SCB->scb_cmd_blk_addr = IEE_PHYS_SHMEM(IEE_CB_OFF);
+	SC_SCB->scb_cmd_blk_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_CB_OFF));
 	ifmedia_init(&sc->sc_ifmedia, 0, iee_mediachange, iee_mediastatus);
 	if (media != NULL) {
 		for (n = 0 ; n < nmedia ; n++)
 			ifmedia_add(&sc->sc_ifmedia, media[n], 0, NULL);
 		ifmedia_set(&sc->sc_ifmedia, defmedia);
 	} else {
 		ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_NONE, 0, NULL);
 		ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_NONE);
+	}
 	ifp->if_softc = sc;
 	strcpy(ifp->if_xname, device_xname(sc->sc_dev));
 @@ -646,32 +668,32 @@ iee_start(struct ifnet *ifp)
 			m_freem(sc->sc_tx_mbuf[t]);
 			sc->sc_tx_mbuf[t] = m;
 			if(bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_tx_map[t],
 		    	    m, BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) {
 				printf("%s: iee_start: can't load TX DMA map\n",
 				    device_xname(sc->sc_dev));
 				m_freem(sc->sc_tx_mbuf[t]);
 				t--;
 				continue;
+			}
+		}
 		for (n = 0 ; n < sc->sc_tx_map[t]->dm_nsegs ; n++) {
 			SC_TBD(sc->sc_next_tbd + n)->tbd_tb_addr =
-			    sc->sc_tx_map[t]->dm_segs[n].ds_addr;
+			    IEE_SWAPA32(sc->sc_tx_map[t]->dm_segs[n].ds_addr);
 			SC_TBD(sc->sc_next_tbd + n)->tbd_size =
 			    sc->sc_tx_map[t]->dm_segs[n].ds_len;
 			SC_TBD(sc->sc_next_tbd + n)->tbd_link_addr =
-			    IEE_PHYS_SHMEM(IEE_TBD_OFF + IEE_TBD_SZ
+			    IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_TBD_OFF + IEE_TBD_SZ
-			    * (sc->sc_next_tbd + n + 1));
+			    * (sc->sc_next_tbd + n + 1)));
+		}
 		SC_TBD(sc->sc_next_tbd + n - 1)->tbd_size |= IEE_CB_EL;
 		bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_map[t], 0,
 		    sc->sc_tx_map[t]->dm_mapsize, BUS_DMASYNC_PREWRITE);
 		IFQ_POLL(&ifp->if_snd, m);
 		if (m == NULL)
 			iee_cb_setup(sc, IEE_CB_CMD_TR | IEE_CB_S | IEE_CB_EL
 			    | IEE_CB_I);
 		else
 			iee_cb_setup(sc, IEE_CB_CMD_TR);
 		sc->sc_next_tbd += n;
 #if NBPFILTER > 0
 		/* Pass packet to bpf if someone listens. */
 @@ -768,31 +790,33 @@ iee_init(struct ifnet *ifp)
 			    device_xname(sc->sc_dev));
 			for (n = 0 ; n < t ; n++)
 				bus_dmamap_destroy(sc->sc_dmat,
 				    sc->sc_tx_map[n]);
 			return ENOBUFS;
+		}
+	}
 	/* Initialize Receive Frame and Receive Buffer Descriptors */
 	err = 0;
 	memset(SC_RFD(0), 0, IEE_RFD_LIST_SZ);
 	memset(SC_RBD(0), 0, IEE_RBD_LIST_SZ);
 	for (r = 0 ; r < IEE_NRFD ; r++) {
 		SC_RFD(r)->rfd_cmd = IEE_RFD_SF;
-		SC_RFD(r)->rfd_link_addr = IEE_PHYS_SHMEM(IEE_RFD_OFF
+		SC_RFD(r)->rfd_link_addr =
-		    + IEE_RFD_SZ * ((r + 1) % IEE_NRFD));
+		    IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_RFD_OFF
 		    + IEE_RFD_SZ * ((r + 1) % IEE_NRFD)));
 		SC_RBD(r)->rbd_next_rbd = IEE_PHYS_SHMEM(IEE_RBD_OFF
-		    + IEE_RBD_SZ * ((r + 1) % IEE_NRFD));
+		SC_RBD(r)->rbd_next_rbd =
 		    IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_RBD_OFF
 		    + IEE_RBD_SZ * ((r + 1) % IEE_NRFD)));
 		if (sc->sc_rx_mbuf[r] == NULL) {
 			MGETHDR(sc->sc_rx_mbuf[r], M_DONTWAIT, MT_DATA);
 			if (sc->sc_rx_mbuf[r] == NULL) {
 				printf("%s: iee_init: can't allocate mbuf\n",
 				    device_xname(sc->sc_dev));
 				err = 1;
 				break;
+			}
 			MCLAIM(sc->sc_rx_mbuf[r],&sc->sc_ethercom.ec_rx_mowner);
 			MCLGET(sc->sc_rx_mbuf[r], M_DONTWAIT);
 			if ((sc->sc_rx_mbuf[r]->m_flags & M_EXT) == 0) {
 				printf("%s: iee_init: can't allocate mbuf"
 				    " cluster\n", device_xname(sc->sc_dev));
 @@ -814,29 +838,30 @@ iee_init(struct ifnet *ifp)
 		    sc->sc_rx_mbuf[r]->m_ext.ext_buf,
 		    sc->sc_rx_mbuf[r]->m_ext.ext_size, NULL,
 		    BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) {
 			printf("%s: iee_init: can't load RX DMA map\n",
 			    device_xname(sc->sc_dev));
 			bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[r]);
 			m_freem(sc->sc_rx_mbuf[r]);
 			err = 1;
 			break;
+		}
 		bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_map[r], 0,
 		    sc->sc_rx_mbuf[r]->m_ext.ext_size, BUS_DMASYNC_PREREAD);
 		SC_RBD(r)->rbd_size = sc->sc_rx_map[r]->dm_segs[0].ds_len;
-		SC_RBD(r)->rbd_rb_addr= sc->sc_rx_map[r]->dm_segs[0].ds_addr;
+		SC_RBD(r)->rbd_rb_addr =
 		    IEE_SWAPA32(sc->sc_rx_map[r]->dm_segs[0].ds_addr);
+	}
-	SC_RFD(0)->rfd_rbd_addr = IEE_PHYS_SHMEM(IEE_RBD_OFF);
+	SC_RFD(0)->rfd_rbd_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_RBD_OFF));
 	if (err != 0) {
 		for (n = 0 ; n < r; n++) {
 			m_freem(sc->sc_rx_mbuf[n]);
 			sc->sc_rx_mbuf[n] = NULL;
 			bus_dmamap_unload(sc->sc_dmat, sc->sc_rx_map[n]);
 			bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[n]);
 			sc->sc_rx_map[n] = NULL;
+		}
 		for (n = 0 ; n < t ; n++) {
 			bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_map[n]);
 			sc->sc_tx_map[n] = NULL;
+		}
 		return ENOBUFS;
 @@ -850,27 +875,27 @@ iee_init(struct ifnet *ifp)
 	sc->sc_cf[3] = IEE_CF_3_ADDRLEN_DEF | IEE_CF_3_NSAI
 	    | IEE_CF_3_PREAMLEN_DEF;
 	sc->sc_cf[4] = IEE_CF_4_DEF;
 	sc->sc_cf[5] = IEE_CF_5_DEF;
 	sc->sc_cf[6] = IEE_CF_6_DEF;
 	sc->sc_cf[7] = IEE_CF_7_DEF;
 	sc->sc_cf[8] = IEE_CF_8_DEF;
 	sc->sc_cf[9] = IEE_CF_9_DEF;
 	sc->sc_cf[10] = IEE_CF_10_DEF;
 	sc->sc_cf[11] = IEE_CF_11_DEF & ~IEE_CF_11_LNGFLD;
 	sc->sc_cf[12] = IEE_CF_12_DEF;
 	sc->sc_cf[13] = IEE_CF_13_DEF;
 	iee_cb_setup(sc, IEE_CB_CMD_CONF | IEE_CB_S | IEE_CB_EL);
-	SC_SCB->scb_rfa_addr = IEE_PHYS_SHMEM(IEE_RFD_OFF);
+	SC_SCB->scb_rfa_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(IEE_RFD_OFF));
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 0, IEE_SHMEM_MAX,
 	    BUS_DMASYNC_PREWRITE);
 	(sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE | IEE_SCB_RUC_ST);
 	/* Issue a Channel Attention to ACK interrupts we may have caused. */
 	(sc->sc_iee_cmd)(sc, IEE_SCB_ACK);
 	/* Mark the interface as running and ready to RX/TX packets. */
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	return 0;
+}

 @@ -1,14 +1,14 @@
-/* $NetBSD: i82596var.h,v 1.10 2008/04/04 17:03:42 tsutsui Exp $ */
+/* $NetBSD: i82596var.h,v 1.11 2009/05/05 15:47:35 tsutsui Exp $ */
 /*
  * Copyright (c) 2003 Jochen Kunz.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -179,30 +179,43 @@ struct iee_softc {
 	uint32_t sc_cmd_err;
 	uint32_t sc_tx_timeout;
 	uint32_t sc_setup_timeout;
 	int (*sc_iee_cmd)(struct iee_softc *, uint32_t);
 	int (*sc_iee_reset)(struct iee_softc *);
 	void (*sc_mediastatus)(struct ifnet *, struct ifmediareq *);
 	int (*sc_mediachange)(struct ifnet *);
 };
 /* Flags */
 #define IEE_NEED_SWAP	0x01
-#define	IEE_WANT_MCAST	0x02
+#define IEE_WANT_MCAST	0x02
 #define IEE_REV_A	0x04
-#define IEE_SWAP(x)	((sc->sc_flags & IEE_NEED_SWAP) == 0 ? x : 	\
+/*
-			(((x) << 16) | ((x) >> 16)))
+ * Rev A1 chip doesn't have 32-bit BE mode and all 32 bit pointers are
  * treated as two 16-bit big endian entities.
  */
 #define IEE_SWAPA32(x)	((sc->sc_flags & (IEE_NEED_SWAP|IEE_REV_A)) ==	\
 			    (IEE_NEED_SWAP|IEE_REV_A) ?			\
 			    (((x) << 16) | ((x) >> 16)) : (x))
 /*
  * The SCB absolute address and statistical counters are
  * always treated as two 16-bit big endian entities
  * even in 32-bit BE mode supported by Rev B and C chips.
  */
 #define IEE_SWAP32(x)	((sc->sc_flags & IEE_NEED_SWAP) != 0 ? 		\
 			    (((x) << 16) | ((x) >> 16)) : (x))
 #define IEE_PHYS_SHMEM(x) ((uint32_t) (sc->sc_shmem_map->dm_segs[0].ds_addr \
 			+ (x)))
 /* Offsets in shared memory */
 #define IEE_SCP_SZ	(((sizeof(struct iee_scp) - 1) / (sc)->sc_cl_align + 1)\
 			* (sc)->sc_cl_align)
 #define IEE_SCP_OFF	0
 #define IEE_ISCP_SZ	(((sizeof(struct iee_iscp) - 1) / (sc)->sc_cl_align + 1)\
 			* (sc)->sc_cl_align)
 #define IEE_ISCP_OFF	IEE_SCP_SZ