Tue May 5 18:17:57 2009 UTC ()
Pull up following revision(s) (requested by snj in ticket #737):
	sys/arch/x86/pci/pchb.c: revisions 1.15 - 1.17
	sys/dev/pci/agp.c: revisions 1.63 - 1.65
	sys/dev/pci/agp_i810.c: revisions 1.57 - 1.64
	sys/dev/pci/pcidevs: revisions 1.965, 1.967 via patch
	sys/dev/pci/agpreg.h: revision 1.20
Add AGP support for Intel G35, G45, and Q45.


(bouyer)
diff -r1.14 -r1.14.4.1 src/sys/arch/x86/pci/pchb.c
diff -r1.62 -r1.62.4.1 src/sys/dev/pci/agp.c
diff -r1.56 -r1.56.4.1 src/sys/dev/pci/agp_i810.c
diff -r1.19 -r1.19.14.1 src/sys/dev/pci/agpreg.h
diff -r1.962.4.2 -r1.962.4.3 src/sys/dev/pci/pcidevs
cvs diff -r1.14 -r1.14.4.1 src/sys/arch/x86/pci/pchb.c (expand / switch to unified diff)

--- src/sys/arch/x86/pci/pchb.c 2008/08/22 18:05:44 1.14
+++ src/sys/arch/x86/pci/pchb.c 2009/05/05 18:17:57 1.14.4.1
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: pchb.c,v 1.14 2008/08/22 18:05:44 tnn Exp $ */ 1/* $NetBSD: pchb.c,v 1.14.4.1 2009/05/05 18:17:57 bouyer Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1996, 1998, 2000 The NetBSD Foundation, Inc. 4 * Copyright (c) 1996, 1998, 2000 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe. 8 * by Jason R. Thorpe.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -20,27 +20,27 @@ @@ -20,27 +20,27 @@
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.14 2008/08/22 18:05:44 tnn Exp $"); 33__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.14.4.1 2009/05/05 18:17:57 bouyer Exp $");
34 34
35#include <sys/types.h> 35#include <sys/types.h>
36#include <sys/param.h> 36#include <sys/param.h>
37#include <sys/systm.h> 37#include <sys/systm.h>
38#include <sys/device.h> 38#include <sys/device.h>
39 39
40#include <machine/bus.h> 40#include <machine/bus.h>
41 41
42#include <dev/pci/pcivar.h> 42#include <dev/pci/pcivar.h>
43#include <dev/pci/pcireg.h> 43#include <dev/pci/pcireg.h>
44 44
45#include <dev/pci/pcidevs.h> 45#include <dev/pci/pcidevs.h>
46 46
@@ -372,26 +372,31 @@ pchbattach(device_t parent, device_t sel @@ -372,26 +372,31 @@ pchbattach(device_t parent, device_t sel
372 case PCI_PRODUCT_INTEL_82865_HB: 372 case PCI_PRODUCT_INTEL_82865_HB:
373 case PCI_PRODUCT_INTEL_82915G_HB: 373 case PCI_PRODUCT_INTEL_82915G_HB:
374 case PCI_PRODUCT_INTEL_82915GM_HB: 374 case PCI_PRODUCT_INTEL_82915GM_HB:
375 case PCI_PRODUCT_INTEL_82945P_MCH: 375 case PCI_PRODUCT_INTEL_82945P_MCH:
376 case PCI_PRODUCT_INTEL_82945GM_HB: 376 case PCI_PRODUCT_INTEL_82945GM_HB:
377 case PCI_PRODUCT_INTEL_82945GME_HB: 377 case PCI_PRODUCT_INTEL_82945GME_HB:
378 case PCI_PRODUCT_INTEL_82946GZ_HB: 378 case PCI_PRODUCT_INTEL_82946GZ_HB:
379 case PCI_PRODUCT_INTEL_82965Q_HB: 379 case PCI_PRODUCT_INTEL_82965Q_HB:
380 case PCI_PRODUCT_INTEL_82965G_HB: 380 case PCI_PRODUCT_INTEL_82965G_HB:
381 case PCI_PRODUCT_INTEL_82965PM_HB: 381 case PCI_PRODUCT_INTEL_82965PM_HB:
382 case PCI_PRODUCT_INTEL_82Q35_HB: 382 case PCI_PRODUCT_INTEL_82Q35_HB:
383 case PCI_PRODUCT_INTEL_82G33_HB: 383 case PCI_PRODUCT_INTEL_82G33_HB:
384 case PCI_PRODUCT_INTEL_82Q33_HB: 384 case PCI_PRODUCT_INTEL_82Q33_HB:
 385 case PCI_PRODUCT_INTEL_82G35_HB:
 386 case PCI_PRODUCT_INTEL_82GM45_HB:
 387 case PCI_PRODUCT_INTEL_82IGD_E_HB:
 388 case PCI_PRODUCT_INTEL_82Q45_HB:
 389 case PCI_PRODUCT_INTEL_82G45_HB:
385 /* 390 /*
386 * The host bridge is either in GFX mode (internal 391 * The host bridge is either in GFX mode (internal
387 * graphics) or in AGP mode. In GFX mode, we pretend 392 * graphics) or in AGP mode. In GFX mode, we pretend
388 * to have AGP because the graphics memory access 393 * to have AGP because the graphics memory access
389 * is very similar and the AGP GATT code will 394 * is very similar and the AGP GATT code will
390 * deal with this. In the latter case, the 395 * deal with this. In the latter case, the
391 * pci_get_capability(PCI_CAP_AGP) test below will 396 * pci_get_capability(PCI_CAP_AGP) test below will
392 * fire, so we do no harm by already setting the flag. 397 * fire, so we do no harm by already setting the flag.
393 */ 398 */
394 has_agp = 1; 399 has_agp = 1;
395 break; 400 break;
396 } 401 }
397 break; 402 break;
cvs diff -r1.62 -r1.62.4.1 src/sys/dev/pci/agp.c (expand / switch to unified diff)

--- src/sys/dev/pci/agp.c 2008/10/17 17:15:09 1.62
+++ src/sys/dev/pci/agp.c 2009/05/05 18:17:57 1.62.4.1
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: agp.c,v 1.62 2008/10/17 17:15:09 christos Exp $ */ 1/* $NetBSD: agp.c,v 1.62.4.1 2009/05/05 18:17:57 bouyer Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2000 Doug Rabson 4 * Copyright (c) 2000 Doug Rabson
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -55,27 +55,27 @@ @@ -55,27 +55,27 @@
55 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
56 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 56 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
57 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
58 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
59 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
60 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
61 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
62 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
63 * POSSIBILITY OF SUCH DAMAGE. 63 * POSSIBILITY OF SUCH DAMAGE.
64 */ 64 */
65 65
66 66
67#include <sys/cdefs.h> 67#include <sys/cdefs.h>
68__KERNEL_RCSID(0, "$NetBSD: agp.c,v 1.62 2008/10/17 17:15:09 christos Exp $"); 68__KERNEL_RCSID(0, "$NetBSD: agp.c,v 1.62.4.1 2009/05/05 18:17:57 bouyer Exp $");
69 69
70#include <sys/param.h> 70#include <sys/param.h>
71#include <sys/systm.h> 71#include <sys/systm.h>
72#include <sys/malloc.h> 72#include <sys/malloc.h>
73#include <sys/kernel.h> 73#include <sys/kernel.h>
74#include <sys/device.h> 74#include <sys/device.h>
75#include <sys/conf.h> 75#include <sys/conf.h>
76#include <sys/ioctl.h> 76#include <sys/ioctl.h>
77#include <sys/fcntl.h> 77#include <sys/fcntl.h>
78#include <sys/agpio.h> 78#include <sys/agpio.h>
79#include <sys/proc.h> 79#include <sys/proc.h>
80#include <sys/mutex.h> 80#include <sys/mutex.h>
81 81
@@ -170,28 +170,38 @@ const struct agp_product { @@ -170,28 +170,38 @@ const struct agp_product {
170 NULL, agp_i810_attach }, 170 NULL, agp_i810_attach },
171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82965Q_HB, 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82965Q_HB,
172 NULL, agp_i810_attach }, 172 NULL, agp_i810_attach },
173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82965PM_HB, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82965PM_HB,
174 NULL, agp_i810_attach }, 174 NULL, agp_i810_attach },
175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82965G_HB, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82965G_HB,
176 NULL, agp_i810_attach }, 176 NULL, agp_i810_attach },
177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82Q35_HB, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82Q35_HB,
178 NULL, agp_i810_attach }, 178 NULL, agp_i810_attach },
179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82G33_HB, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82G33_HB,
180 NULL, agp_i810_attach }, 180 NULL, agp_i810_attach },
181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82Q33_HB, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82Q33_HB,
182 NULL, agp_i810_attach }, 182 NULL, agp_i810_attach },
 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82G35_HB,
 184 NULL, agp_i810_attach },
183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82946GZ_HB, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82946GZ_HB,
184 NULL, agp_i810_attach }, 186 NULL, agp_i810_attach },
 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82GM45_HB,
 188 NULL, agp_i810_attach },
 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82IGD_E_HB,
 190 NULL, agp_i810_attach },
 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82Q45_HB,
 192 NULL, agp_i810_attach },
 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82G45_HB,
 194 NULL, agp_i810_attach },
185#endif 195#endif
186 196
187#if NAGP_INTEL > 0 197#if NAGP_INTEL > 0
188 { PCI_VENDOR_INTEL, -1, 198 { PCI_VENDOR_INTEL, -1,
189 NULL, agp_intel_attach }, 199 NULL, agp_intel_attach },
190#endif 200#endif
191 201
192#if NAGP_AMD64 > 0 202#if NAGP_AMD64 > 0
193 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_PCHB, 203 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_PCHB,
194 agp_amd64_match, agp_amd64_attach }, 204 agp_amd64_match, agp_amd64_attach },
195 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_PCHB, 205 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_PCHB,
196 agp_amd64_match, agp_amd64_attach }, 206 agp_amd64_match, agp_amd64_attach },
197#endif 207#endif
cvs diff -r1.56 -r1.56.4.1 src/sys/dev/pci/agp_i810.c (expand / switch to unified diff)

--- src/sys/dev/pci/agp_i810.c 2008/08/22 18:05:44 1.56
+++ src/sys/dev/pci/agp_i810.c 2009/05/05 18:17:57 1.56.4.1
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: agp_i810.c,v 1.56 2008/08/22 18:05:44 tnn Exp $ */ 1/* $NetBSD: agp_i810.c,v 1.56.4.1 2009/05/05 18:17:57 bouyer Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2000 Doug Rabson 4 * Copyright (c) 2000 Doug Rabson
5 * Copyright (c) 2000 Ruslan Ermilov 5 * Copyright (c) 2000 Ruslan Ermilov
6 * All rights reserved. 6 * All rights reserved.
7 * 7 *
8 * Redistribution and use in source and binary forms, with or without 8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions 9 * modification, are permitted provided that the following conditions
10 * are met: 10 * are met:
11 * 1. Redistributions of source code must retain the above copyright 11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer. 12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright 13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the 14 * notice, this list of conditions and the following disclaimer in the
@@ -20,76 +20,61 @@ @@ -20,76 +20,61 @@
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE. 27 * SUCH DAMAGE.
28 * 28 *
29 * $FreeBSD: src/sys/pci/agp_i810.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 * $FreeBSD: src/sys/pci/agp_i810.c,v 1.4 2001/07/05 21:28:47 jhb Exp $
30 */ 30 */
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.56 2008/08/22 18:05:44 tnn Exp $"); 33__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.56.4.1 2009/05/05 18:17:57 bouyer Exp $");
34 34
35#include <sys/param.h> 35#include <sys/param.h>
36#include <sys/systm.h> 36#include <sys/systm.h>
37#include <sys/malloc.h> 37#include <sys/malloc.h>
38#include <sys/kernel.h> 38#include <sys/kernel.h>
39#include <sys/proc.h> 39#include <sys/proc.h>
40#include <sys/device.h> 40#include <sys/device.h>
41#include <sys/conf.h> 41#include <sys/conf.h>
42 42
43#include <uvm/uvm_extern.h> 43#include <uvm/uvm_extern.h>
44 44
45#include <dev/pci/pcivar.h> 45#include <dev/pci/pcivar.h>
46#include <dev/pci/pcireg.h> 46#include <dev/pci/pcireg.h>
47#include <dev/pci/pcidevs.h> 47#include <dev/pci/pcidevs.h>
48#include <dev/pci/agpvar.h> 48#include <dev/pci/agpvar.h>
49#include <dev/pci/agpreg.h> 49#include <dev/pci/agpreg.h>
50 50
51#include <sys/agpio.h> 51#include <sys/agpio.h>
52 52
53#include <sys/bus.h> 53#include <sys/bus.h>
54 54
55#include "agp_intel.h" 55#include "agp_intel.h"
56 56
57#define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 57#define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off)
58#define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 58#define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off)
59#define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 59#define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v)
60#define WRITEGTT(off, v) \ 
61 do { \ 
62 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { \ 
63 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, \ 
64 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 
65 (v)); \ 
66 } else if (isc->chiptype == CHIP_I965) { \ 
67 WRITE4(AGP_I965_GTT + \ 
68 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 
69 (v)); \ 
70 } else { \ 
71 WRITE4(AGP_I810_GTT + \ 
72 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 
73 (v)); \ 
74 } \ 
75 } while (0) 
76 60
77#define CHIP_I810 0 /* i810/i815 */ 61#define CHIP_I810 0 /* i810/i815 */
78#define CHIP_I830 1 /* 830M/845G */ 62#define CHIP_I830 1 /* 830M/845G */
79#define CHIP_I855 2 /* 852GM/855GM/865G */ 63#define CHIP_I855 2 /* 852GM/855GM/865G */
80#define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 64#define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */
81#define CHIP_I965 4 /* 965Q/965PM */ 65#define CHIP_I965 4 /* 965Q/965PM */
82#define CHIP_G33 5 /* G33/Q33/Q35 */ 66#define CHIP_G33 5 /* G33/Q33/Q35 */
 67#define CHIP_G4X 6 /* G45/Q45 */
83 68
84struct agp_i810_softc { 69struct agp_i810_softc {
85 u_int32_t initial_aperture; /* aperture size at startup */ 70 u_int32_t initial_aperture; /* aperture size at startup */
86 struct agp_gatt *gatt; 71 struct agp_gatt *gatt;
87 int chiptype; /* i810-like or i830 */ 72 int chiptype; /* i810-like or i830 */
88 u_int32_t dcache_size; /* i810 only */ 73 u_int32_t dcache_size; /* i810 only */
89 u_int32_t stolen; /* number of i830/845 gtt entries 74 u_int32_t stolen; /* number of i830/845 gtt entries
90 for stolen memory */ 75 for stolen memory */
91 bus_space_tag_t bst; /* register bus_space tag */ 76 bus_space_tag_t bst; /* register bus_space tag */
92 bus_space_handle_t bsh; /* register bus_space handle */ 77 bus_space_handle_t bsh; /* register bus_space handle */
93 bus_space_tag_t gtt_bst; /* GTT bus_space tag */ 78 bus_space_tag_t gtt_bst; /* GTT bus_space tag */
94 bus_space_handle_t gtt_bsh; /* GTT bus_space handle */ 79 bus_space_handle_t gtt_bsh; /* GTT bus_space handle */
95 struct pci_attach_args vga_pa; 80 struct pci_attach_args vga_pa;
@@ -107,40 +92,71 @@ static int agp_i810_bind_page(struct agp @@ -107,40 +92,71 @@ static int agp_i810_bind_page(struct agp
107static int agp_i810_unbind_page(struct agp_softc *, off_t); 92static int agp_i810_unbind_page(struct agp_softc *, off_t);
108static void agp_i810_flush_tlb(struct agp_softc *); 93static void agp_i810_flush_tlb(struct agp_softc *);
109static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 94static int agp_i810_enable(struct agp_softc *, u_int32_t mode);
110static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 95static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int,
111 vsize_t); 96 vsize_t);
112static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 97static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *);
113static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 98static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t);
114static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 99static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *);
115 100
116static bool agp_i810_resume(device_t PMF_FN_PROTO); 101static bool agp_i810_resume(device_t PMF_FN_PROTO);
117static int agp_i810_init(struct agp_softc *); 102static int agp_i810_init(struct agp_softc *);
118 103
119static int agp_i810_init(struct agp_softc *); 104static int agp_i810_init(struct agp_softc *);
 105static void agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t,
 106 u_int32_t);
120 107
121static struct agp_methods agp_i810_methods = { 108static struct agp_methods agp_i810_methods = {
122 agp_i810_get_aperture, 109 agp_i810_get_aperture,
123 agp_i810_set_aperture, 110 agp_i810_set_aperture,
124 agp_i810_bind_page, 111 agp_i810_bind_page,
125 agp_i810_unbind_page, 112 agp_i810_unbind_page,
126 agp_i810_flush_tlb, 113 agp_i810_flush_tlb,
127 agp_i810_enable, 114 agp_i810_enable,
128 agp_i810_alloc_memory, 115 agp_i810_alloc_memory,
129 agp_i810_free_memory, 116 agp_i810_free_memory,
130 agp_i810_bind_memory, 117 agp_i810_bind_memory,
131 agp_i810_unbind_memory, 118 agp_i810_unbind_memory,
132}; 119};
133 120
 121static void
 122agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, u_int32_t v)
 123{
 124 u_int32_t base_off;
 125
 126 base_off = 0;
 127
 128 switch (isc->chiptype) {
 129 case CHIP_I810:
 130 case CHIP_I830:
 131 case CHIP_I855:
 132 base_off = AGP_I810_GTT;
 133 break;
 134 case CHIP_I965:
 135 base_off = AGP_I965_GTT;
 136 break;
 137 case CHIP_G4X:
 138 base_off = AGP_G4X_GTT;
 139 break;
 140 case CHIP_I915:
 141 case CHIP_G33:
 142 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh,
 143 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, (v));
 144 return;
 145 }
 146
 147 WRITE4(base_off + (u_int32_t)(off >> AGP_PAGE_SHIFT) * 4, v);
 148}
 149
134/* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 150/* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */
135static int 151static int
136agp_i810_vgamatch(struct pci_attach_args *pa) 152agp_i810_vgamatch(struct pci_attach_args *pa)
137{ 153{
138 154
139 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 155 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY ||
140 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 156 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA)
141 return (0); 157 return (0);
142 158
143 switch (PCI_PRODUCT(pa->pa_id)) { 159 switch (PCI_PRODUCT(pa->pa_id)) {
144 case PCI_PRODUCT_INTEL_82810_GC: 160 case PCI_PRODUCT_INTEL_82810_GC:
145 case PCI_PRODUCT_INTEL_82810_DC100_GC: 161 case PCI_PRODUCT_INTEL_82810_DC100_GC:
146 case PCI_PRODUCT_INTEL_82810E_GC: 162 case PCI_PRODUCT_INTEL_82810E_GC:
@@ -157,27 +173,34 @@ agp_i810_vgamatch(struct pci_attach_args @@ -157,27 +173,34 @@ agp_i810_vgamatch(struct pci_attach_args
157 case PCI_PRODUCT_INTEL_82945GME_IGD: 173 case PCI_PRODUCT_INTEL_82945GME_IGD:
158 case PCI_PRODUCT_INTEL_82965Q_IGD: 174 case PCI_PRODUCT_INTEL_82965Q_IGD:
159 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 175 case PCI_PRODUCT_INTEL_82965Q_IGD_1:
160 case PCI_PRODUCT_INTEL_82965PM_IGD: 176 case PCI_PRODUCT_INTEL_82965PM_IGD:
161 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 177 case PCI_PRODUCT_INTEL_82965PM_IGD_1:
162 case PCI_PRODUCT_INTEL_82G33_IGD: 178 case PCI_PRODUCT_INTEL_82G33_IGD:
163 case PCI_PRODUCT_INTEL_82G33_IGD_1: 179 case PCI_PRODUCT_INTEL_82G33_IGD_1:
164 case PCI_PRODUCT_INTEL_82965G_IGD: 180 case PCI_PRODUCT_INTEL_82965G_IGD:
165 case PCI_PRODUCT_INTEL_82965G_IGD_1: 181 case PCI_PRODUCT_INTEL_82965G_IGD_1:
166 case PCI_PRODUCT_INTEL_82Q35_IGD: 182 case PCI_PRODUCT_INTEL_82Q35_IGD:
167 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 183 case PCI_PRODUCT_INTEL_82Q35_IGD_1:
168 case PCI_PRODUCT_INTEL_82Q33_IGD: 184 case PCI_PRODUCT_INTEL_82Q33_IGD:
169 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 185 case PCI_PRODUCT_INTEL_82Q33_IGD_1:
 186 case PCI_PRODUCT_INTEL_82G35_IGD:
 187 case PCI_PRODUCT_INTEL_82G35_IGD_1:
170 case PCI_PRODUCT_INTEL_82946GZ_IGD: 188 case PCI_PRODUCT_INTEL_82946GZ_IGD:
 189 case PCI_PRODUCT_INTEL_82GM45_IGD:
 190 case PCI_PRODUCT_INTEL_82GM45_IGD_1:
 191 case PCI_PRODUCT_INTEL_82IGD_E_IGD:
 192 case PCI_PRODUCT_INTEL_82Q45_IGD:
 193 case PCI_PRODUCT_INTEL_82G45_IGD:
171 return (1); 194 return (1);
172 } 195 }
173 196
174 return (0); 197 return (0);
175} 198}
176 199
177static int 200static int
178agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 201agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg)
179{ 202{
180 /* 203 /*
181 * Find the aperture. Don't map it (yet), this would 204 * Find the aperture. Don't map it (yet), this would
182 * eat KVA. 205 * eat KVA.
183 */ 206 */
@@ -249,49 +272,63 @@ agp_i810_attach(device_t parent, device_ @@ -249,49 +272,63 @@ agp_i810_attach(device_t parent, device_
249 case PCI_PRODUCT_INTEL_82945P_IGD: 272 case PCI_PRODUCT_INTEL_82945P_IGD:
250 case PCI_PRODUCT_INTEL_82945GM_IGD: 273 case PCI_PRODUCT_INTEL_82945GM_IGD:
251 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 274 case PCI_PRODUCT_INTEL_82945GM_IGD_1:
252 case PCI_PRODUCT_INTEL_82945GME_IGD: 275 case PCI_PRODUCT_INTEL_82945GME_IGD:
253 isc->chiptype = CHIP_I915; 276 isc->chiptype = CHIP_I915;
254 break; 277 break;
255 case PCI_PRODUCT_INTEL_82965Q_IGD: 278 case PCI_PRODUCT_INTEL_82965Q_IGD:
256 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 279 case PCI_PRODUCT_INTEL_82965Q_IGD_1:
257 case PCI_PRODUCT_INTEL_82965PM_IGD: 280 case PCI_PRODUCT_INTEL_82965PM_IGD:
258 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 281 case PCI_PRODUCT_INTEL_82965PM_IGD_1:
259 case PCI_PRODUCT_INTEL_82965G_IGD: 282 case PCI_PRODUCT_INTEL_82965G_IGD:
260 case PCI_PRODUCT_INTEL_82965G_IGD_1: 283 case PCI_PRODUCT_INTEL_82965G_IGD_1:
261 case PCI_PRODUCT_INTEL_82946GZ_IGD: 284 case PCI_PRODUCT_INTEL_82946GZ_IGD:
 285 case PCI_PRODUCT_INTEL_82G35_IGD:
 286 case PCI_PRODUCT_INTEL_82G35_IGD_1:
262 isc->chiptype = CHIP_I965; 287 isc->chiptype = CHIP_I965;
263 break; 288 break;
264 case PCI_PRODUCT_INTEL_82Q35_IGD: 289 case PCI_PRODUCT_INTEL_82Q35_IGD:
265 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 290 case PCI_PRODUCT_INTEL_82Q35_IGD_1:
266 case PCI_PRODUCT_INTEL_82G33_IGD: 291 case PCI_PRODUCT_INTEL_82G33_IGD:
267 case PCI_PRODUCT_INTEL_82G33_IGD_1: 292 case PCI_PRODUCT_INTEL_82G33_IGD_1:
268 case PCI_PRODUCT_INTEL_82Q33_IGD: 293 case PCI_PRODUCT_INTEL_82Q33_IGD:
269 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 294 case PCI_PRODUCT_INTEL_82Q33_IGD_1:
270 isc->chiptype = CHIP_G33; 295 isc->chiptype = CHIP_G33;
271 break; 296 break;
 297 case PCI_PRODUCT_INTEL_82GM45_IGD:
 298 case PCI_PRODUCT_INTEL_82GM45_IGD_1:
 299 case PCI_PRODUCT_INTEL_82IGD_E_IGD:
 300 case PCI_PRODUCT_INTEL_82Q45_IGD:
 301 case PCI_PRODUCT_INTEL_82G45_IGD:
 302 isc->chiptype = CHIP_G4X;
 303 break;
272 } 304 }
273 305
274 switch (isc->chiptype) { 306 switch (isc->chiptype) {
275 case CHIP_I915: 307 case CHIP_I915:
276 case CHIP_G33: 308 case CHIP_G33:
277 apbase = AGP_I915_GMADR; 309 apbase = AGP_I915_GMADR;
278 break; 310 break;
 311 case CHIP_I965:
 312 case CHIP_G4X:
 313 apbase = AGP_I965_GMADR;
 314 break;
279 default: 315 default:
280 apbase = AGP_I810_GMADR; 316 apbase = AGP_I810_GMADR;
281 break; 317 break;
282 } 318 }
283 if (isc->chiptype == CHIP_I965) { 319
284 error = agp_i965_map_aperture(&isc->vga_pa, sc, AGP_I965_GMADR); 320 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) {
 321 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase);
285 } else { 322 } else {
286 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 323 error = agp_map_aperture(&isc->vga_pa, sc, apbase);
287 } 324 }
288 if (error != 0) { 325 if (error != 0) {
289 aprint_error(": can't map aperture\n"); 326 aprint_error(": can't map aperture\n");
290 free(isc, M_AGP); 327 free(isc, M_AGP);
291 return error; 328 return error;
292 } 329 }
293 330
294 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 331 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) {
295 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 332 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR,
296 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 333 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh,
297 &mmadr, &mmadrsize); 334 &mmadr, &mmadrsize);
@@ -299,27 +336,27 @@ agp_i810_attach(device_t parent, device_ @@ -299,27 +336,27 @@ agp_i810_attach(device_t parent, device_
299 aprint_error(": can't map mmadr registers\n"); 336 aprint_error(": can't map mmadr registers\n");
300 agp_generic_detach(sc); 337 agp_generic_detach(sc);
301 return error; 338 return error;
302 } 339 }
303 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 340 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR,
304 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 341 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh,
305 NULL, NULL); 342 NULL, NULL);
306 if (error != 0) { 343 if (error != 0) {
307 aprint_error(": can't map gttadr registers\n"); 344 aprint_error(": can't map gttadr registers\n");
308 /* XXX we should release mmadr here */ 345 /* XXX we should release mmadr here */
309 agp_generic_detach(sc); 346 agp_generic_detach(sc);
310 return error; 347 return error;
311 } 348 }
312 } else if (isc->chiptype == CHIP_I965) { 349 } else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) {
313 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 350 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR,
314 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 351 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh,
315 &mmadr, &mmadrsize); 352 &mmadr, &mmadrsize);
316 if (error != 0) { 353 if (error != 0) {
317 aprint_error(": can't map mmadr registers\n"); 354 aprint_error(": can't map mmadr registers\n");
318 agp_generic_detach(sc); 355 agp_generic_detach(sc);
319 return error; 356 return error;
320 } 357 }
321 } else { 358 } else {
322 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 359 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR,
323 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 360 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh,
324 &mmadr, &mmadrsize); 361 &mmadr, &mmadrsize);
325 if (error != 0) { 362 if (error != 0) {
@@ -428,110 +465,176 @@ static int agp_i810_init(struct agp_soft @@ -428,110 +465,176 @@ static int agp_i810_init(struct agp_soft
428 465
429 if (isc->stolen > 0) { 466 if (isc->stolen > 0) {
430 aprint_normal(": detected %dk stolen memory\n%s", 467 aprint_normal(": detected %dk stolen memory\n%s",
431 isc->stolen * 4, device_xname(sc->as_dev)); 468 isc->stolen * 4, device_xname(sc->as_dev));
432 } 469 }
433 470
434 /* GATT address is already in there, make sure it's enabled */ 471 /* GATT address is already in there, make sure it's enabled */
435 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 472 pgtblctl = READ4(AGP_I810_PGTBL_CTL);
436 pgtblctl |= 1; 473 pgtblctl |= 1;
437 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 474 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
438 475
439 gatt->ag_physical = pgtblctl & ~1; 476 gatt->ag_physical = pgtblctl & ~1;
440 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 477 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 ||
441 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33) { 478 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 ||
 479 isc->chiptype == CHIP_G4X) {
442 pcireg_t reg; 480 pcireg_t reg;
443 u_int32_t pgtblctl, stolen; 481 u_int32_t pgtblctl, gtt_size, stolen;
444 u_int16_t gcc1; 482 u_int16_t gcc1;
445 483
446 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 484 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1);
447 gcc1 = (u_int16_t)(reg >> 16); 485 gcc1 = (u_int16_t)(reg >> 16);
448 486
 487 pgtblctl = READ4(AGP_I810_PGTBL_CTL);
 488
449 /* Stolen memory is set up at the beginning of the aperture by 489 /* Stolen memory is set up at the beginning of the aperture by
450 * the BIOS, consisting of the GATT followed by 4kb for the 490 * the BIOS, consisting of the GATT followed by 4kb for the
451 * BIOS display. 491 * BIOS display.
452 */ 492 */
453 switch (isc->chiptype) { 493 switch (isc->chiptype) {
454 case CHIP_I855: 494 case CHIP_I855:
455 stolen = 128 + 4; 495 gtt_size = 128;
456 break; 496 break;
457 case CHIP_I915: 497 case CHIP_I915:
458 stolen = 256 + 4; 498 gtt_size = 256;
459 break; 499 break;
460 case CHIP_I965: 500 case CHIP_I965:
461 stolen = 512 + 4; 501 switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) {
 502 case AGP_I810_PGTBL_SIZE_128KB:
 503 case AGP_I810_PGTBL_SIZE_512KB:
 504 gtt_size = 512;
 505 break;
 506 case AGP_I965_PGTBL_SIZE_1MB:
 507 gtt_size = 1024;
 508 break;
 509 case AGP_I965_PGTBL_SIZE_2MB:
 510 gtt_size = 2048;
 511 break;
 512 case AGP_I965_PGTBL_SIZE_1_5MB:
 513 gtt_size = 1024 + 512;
 514 break;
 515 default:
 516 aprint_error("Bad PGTBL size\n");
 517 agp_generic_detach(sc);
 518 return EINVAL;
 519 }
462 break; 520 break;
463 case CHIP_G33: 521 case CHIP_G33:
464 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 522 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) {
465 case AGP_G33_PGTBL_SIZE_1M: 523 case AGP_G33_PGTBL_SIZE_1M:
466 stolen = 1024 + 4; 524 gtt_size = 1024;
467 break; 525 break;
468 case AGP_G33_PGTBL_SIZE_2M: 526 case AGP_G33_PGTBL_SIZE_2M:
469 stolen = 2048 + 4; 527 gtt_size = 2048;
470 break; 528 break;
471 default: 529 default:
472 aprint_error(": bad gtt size\n"); 530 aprint_error(": Bad PGTBL size\n");
473 agp_generic_detach(sc); 531 agp_generic_detach(sc);
474 return EINVAL; 532 return EINVAL;
475 } 533 }
476 break; 534 break;
 535 case CHIP_G4X:
 536 gtt_size = 0;
 537 break;
477 default: 538 default:
478 aprint_error(": bad chiptype\n"); 539 aprint_error(": bad chiptype\n");
479 agp_generic_detach(sc); 540 agp_generic_detach(sc);
480 return EINVAL; 541 return EINVAL;
481 } 542 }
482 543
483 switch (gcc1 & AGP_I855_GCC1_GMS) { 544 switch (gcc1 & AGP_I855_GCC1_GMS) {
484 case AGP_I855_GCC1_GMS_STOLEN_1M: 545 case AGP_I855_GCC1_GMS_STOLEN_1M:
485 isc->stolen = (1024 - stolen) * 1024 / 4096; 546 stolen = 1024;
486 break; 547 break;
487 case AGP_I855_GCC1_GMS_STOLEN_4M: 548 case AGP_I855_GCC1_GMS_STOLEN_4M:
488 isc->stolen = (4096 - stolen) * 1024 / 4096; 549 stolen = 4 * 1024;
489 break; 550 break;
490 case AGP_I855_GCC1_GMS_STOLEN_8M: 551 case AGP_I855_GCC1_GMS_STOLEN_8M:
491 isc->stolen = (8192 - stolen) * 1024 / 4096; 552 stolen = 8 * 1024;
492 break; 553 break;
493 case AGP_I855_GCC1_GMS_STOLEN_16M: 554 case AGP_I855_GCC1_GMS_STOLEN_16M:
494 isc->stolen = (16384 - stolen) * 1024 / 4096; 555 stolen = 16 * 1024;
495 break; 556 break;
496 case AGP_I855_GCC1_GMS_STOLEN_32M: 557 case AGP_I855_GCC1_GMS_STOLEN_32M:
497 isc->stolen = (32768 - stolen) * 1024 / 4096; 558 stolen = 32 * 1024;
498 break; 559 break;
499 case AGP_I915_GCC1_GMS_STOLEN_48M: 560 case AGP_I915_GCC1_GMS_STOLEN_48M:
500 isc->stolen = (49152 - stolen) * 1024 / 4096; 561 stolen = 48 * 1024;
501 break; 562 break;
502 case AGP_I915_GCC1_GMS_STOLEN_64M: 563 case AGP_I915_GCC1_GMS_STOLEN_64M:
503 isc->stolen = (65536 - stolen) * 1024 / 4096; 564 stolen = 64 * 1024;
504 break; 565 break;
505 case AGP_G33_GCC1_GMS_STOLEN_128M: 566 case AGP_G33_GCC1_GMS_STOLEN_128M:
506 isc->stolen = ((128 * 1024) - stolen) * 1024 / 4096; 567 stolen = 128 * 1024;
507 break; 568 break;
508 case AGP_G33_GCC1_GMS_STOLEN_256M: 569 case AGP_G33_GCC1_GMS_STOLEN_256M:
509 isc->stolen = ((256 * 1024) - stolen) * 1024 / 4096; 570 stolen = 256 * 1024;
 571 break;
 572 case AGP_G4X_GCC1_GMS_STOLEN_96M:
 573 stolen = 96 * 1024;
 574 break;
 575 case AGP_G4X_GCC1_GMS_STOLEN_160M:
 576 stolen = 160 * 1024;
 577 break;
 578 case AGP_G4X_GCC1_GMS_STOLEN_224M:
 579 stolen = 224 * 1024;
 580 break;
 581 case AGP_G4X_GCC1_GMS_STOLEN_352M:
 582 stolen = 352 * 1024;
510 break; 583 break;
511 default: 584 default:
512 isc->stolen = 0; 
513 aprint_error( 585 aprint_error(
514 ": unknown memory configuration, disabling\n"); 586 ": unknown memory configuration, disabling\n");
515 agp_generic_detach(sc); 587 agp_generic_detach(sc);
516 return EINVAL; 588 return EINVAL;
517 } 589 }
 590
 591 switch (gcc1 & AGP_I855_GCC1_GMS) {
 592 case AGP_I915_GCC1_GMS_STOLEN_48M:
 593 case AGP_I915_GCC1_GMS_STOLEN_64M:
 594 if (isc->chiptype != CHIP_I915 &&
 595 isc->chiptype != CHIP_I965 &&
 596 isc->chiptype != CHIP_G33 &&
 597 isc->chiptype != CHIP_G4X)
 598 stolen = 0;
 599 break;
 600 case AGP_G33_GCC1_GMS_STOLEN_128M:
 601 case AGP_G33_GCC1_GMS_STOLEN_256M:
 602 if (isc->chiptype != CHIP_I965 &&
 603 isc->chiptype != CHIP_G33 &&
 604 isc->chiptype != CHIP_G4X)
 605 stolen = 0;
 606 break;
 607 case AGP_G4X_GCC1_GMS_STOLEN_96M:
 608 case AGP_G4X_GCC1_GMS_STOLEN_160M:
 609 case AGP_G4X_GCC1_GMS_STOLEN_224M:
 610 case AGP_G4X_GCC1_GMS_STOLEN_352M:
 611 if (isc->chiptype != CHIP_I965 &&
 612 isc->chiptype != CHIP_G4X)
 613 stolen = 0;
 614 break;
 615 }
 616
 617 /* BIOS space */
 618 gtt_size += 4;
 619
 620 isc->stolen = (stolen - gtt_size) * 1024 / 4096;
 621
518 if (isc->stolen > 0) { 622 if (isc->stolen > 0) {
519 aprint_normal(": detected %dk stolen memory\n%s", 623 aprint_normal(": detected %dk stolen memory\n%s",
520 isc->stolen * 4, device_xname(sc->as_dev)); 624 isc->stolen * 4, device_xname(sc->as_dev));
521 } 625 }
522 626
523 /* GATT address is already in there, make sure it's enabled */ 627 /* GATT address is already in there, make sure it's enabled */
524 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 
525 pgtblctl |= 1; 628 pgtblctl |= 1;
526 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 629 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
527 630
528 gatt->ag_physical = pgtblctl & ~1; 631 gatt->ag_physical = pgtblctl & ~1;
529 } 632 }
530 633
531 /* 634 /*
532 * Make sure the chipset can see everything. 635 * Make sure the chipset can see everything.
533 */ 636 */
534 agp_flush_cache(); 637 agp_flush_cache();
535 638
536 return 0; 639 return 0;
537} 640}
@@ -565,61 +668,70 @@ agp_i810_detach(struct agp_softc *sc) @@ -565,61 +668,70 @@ agp_i810_detach(struct agp_softc *sc)
565 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 668 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1);
566 } 669 }
567 free(sc->gatt, M_AGP); 670 free(sc->gatt, M_AGP);
568 671
569 return 0; 672 return 0;
570} 673}
571#endif 674#endif
572 675
573static u_int32_t 676static u_int32_t
574agp_i810_get_aperture(struct agp_softc *sc) 677agp_i810_get_aperture(struct agp_softc *sc)
575{ 678{
576 struct agp_i810_softc *isc = sc->as_chipc; 679 struct agp_i810_softc *isc = sc->as_chipc;
577 pcireg_t reg; 680 pcireg_t reg;
 681 u_int32_t size;
578 u_int16_t miscc, gcc1, msac; 682 u_int16_t miscc, gcc1, msac;
579 683
 684 size = 0;
 685
580 switch (isc->chiptype) { 686 switch (isc->chiptype) {
581 case CHIP_I810: 687 case CHIP_I810:
582 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 688 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM);
583 miscc = (u_int16_t)(reg >> 16); 689 miscc = (u_int16_t)(reg >> 16);
584 if ((miscc & AGP_I810_MISCC_WINSIZE) == 690 if ((miscc & AGP_I810_MISCC_WINSIZE) ==
585 AGP_I810_MISCC_WINSIZE_32) 691 AGP_I810_MISCC_WINSIZE_32)
586 return 32 * 1024 * 1024; 692 size = 32 * 1024 * 1024;
587 else 693 else
588 return 64 * 1024 * 1024; 694 size = 64 * 1024 * 1024;
 695 break;
589 case CHIP_I830: 696 case CHIP_I830:
590 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 697 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);
591 gcc1 = (u_int16_t)(reg >> 16); 698 gcc1 = (u_int16_t)(reg >> 16);
592 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 699 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
593 return 64 * 1024 * 1024; 700 size = 64 * 1024 * 1024;
594 else 701 else
595 return 128 * 1024 * 1024; 702 size = 128 * 1024 * 1024;
 703 break;
596 case CHIP_I855: 704 case CHIP_I855:
597 return 128 * 1024 * 1024; 705 size = 128 * 1024 * 1024;
 706 break;
598 case CHIP_I915: 707 case CHIP_I915:
599 case CHIP_G33: 708 case CHIP_G33:
 709 case CHIP_G4X:
600 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC); 710 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC);
601 msac = (u_int16_t)(reg >> 16); 711 msac = (u_int16_t)(reg >> 16);
602 if (msac & AGP_I915_MSAC_APER_128M) 712 if (msac & AGP_I915_MSAC_APER_128M)
603 return 128 * 1024 * 1024; 713 size = 128 * 1024 * 1024;
604 else 714 else
605 return 256 * 1024 * 1024; 715 size = 256 * 1024 * 1024;
 716 break;
606 case CHIP_I965: 717 case CHIP_I965:
607 return 512 * 1024 * 1024; 718 size = 512 * 1024 * 1024;
 719 break;
608 default: 720 default:
609 aprint_error(": Unknown chipset\n"); 721 aprint_error(": Unknown chipset\n");
610 } 722 }
611 723
612 return 0; 724 return size;
613} 725}
614 726
615static int 727static int
616agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 728agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture)
617{ 729{
618 struct agp_i810_softc *isc = sc->as_chipc; 730 struct agp_i810_softc *isc = sc->as_chipc;
619 pcireg_t reg; 731 pcireg_t reg;
620 u_int16_t miscc, gcc1; 732 u_int16_t miscc, gcc1;
621 733
622 switch (isc->chiptype) { 734 switch (isc->chiptype) {
623 case CHIP_I810: 735 case CHIP_I810:
624 /* 736 /*
625 * Double check for sanity. 737 * Double check for sanity.
@@ -696,49 +808,49 @@ agp_i810_bind_page(struct agp_softc *sc, @@ -696,49 +808,49 @@ agp_i810_bind_page(struct agp_softc *sc,
696 return EINVAL; 808 return EINVAL;
697 } 809 }
698 810
699 if (isc->chiptype != CHIP_I830) { 811 if (isc->chiptype != CHIP_I830) {
700 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 812 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) {
701#ifdef AGP_DEBUG 813#ifdef AGP_DEBUG
702 printf("%s: trying to bind into stolen memory", 814 printf("%s: trying to bind into stolen memory",
703 device_xname(sc->as_dev)); 815 device_xname(sc->as_dev));
704#endif 816#endif
705 return EINVAL; 817 return EINVAL;
706 } 818 }
707 } 819 }
708 820
709 WRITEGTT(offset, physical | 1); 821 agp_i810_write_gtt_entry(isc, offset, physical | 1);
710 return 0; 822 return 0;
711} 823}
712 824
713static int 825static int
714agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 826agp_i810_unbind_page(struct agp_softc *sc, off_t offset)
715{ 827{
716 struct agp_i810_softc *isc = sc->as_chipc; 828 struct agp_i810_softc *isc = sc->as_chipc;
717 829
718 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 830 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT))
719 return EINVAL; 831 return EINVAL;
720 832
721 if (isc->chiptype != CHIP_I810 ) { 833 if (isc->chiptype != CHIP_I810 ) {
722 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 834 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) {
723#ifdef AGP_DEBUG 835#ifdef AGP_DEBUG
724 printf("%s: trying to unbind from stolen memory", 836 printf("%s: trying to unbind from stolen memory",
725 device_xname(sc->as_dev)); 837 device_xname(sc->as_dev));
726#endif 838#endif
727 return EINVAL; 839 return EINVAL;
728 } 840 }
729 } 841 }
730 842
731 WRITEGTT(offset, 0); 843 agp_i810_write_gtt_entry(isc, offset, 0);
732 return 0; 844 return 0;
733} 845}
734 846
735/* 847/*
736 * Writing via memory mapped registers already flushes all TLBs. 848 * Writing via memory mapped registers already flushes all TLBs.
737 */ 849 */
738static void 850static void
739agp_i810_flush_tlb(struct agp_softc *sc) 851agp_i810_flush_tlb(struct agp_softc *sc)
740{ 852{
741} 853}
742 854
743static int 855static int
744agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 856agp_i810_enable(struct agp_softc *sc, u_int32_t mode)
@@ -850,65 +962,65 @@ agp_i810_bind_memory(struct agp_softc *s @@ -850,65 +962,65 @@ agp_i810_bind_memory(struct agp_softc *s
850 * X server for mysterious reasons which leads to crashes if we write 962 * X server for mysterious reasons which leads to crashes if we write
851 * to the GTT through the MMIO window. 963 * to the GTT through the MMIO window.
852 * Until the issue is solved, simply restore it. 964 * Until the issue is solved, simply restore it.
853 */ 965 */
854 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 966 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL);
855 if (regval != (isc->gatt->ag_physical | 1)) { 967 if (regval != (isc->gatt->ag_physical | 1)) {
856 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 968 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n",
857 regval); 969 regval);
858 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 970 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL,
859 isc->gatt->ag_physical | 1); 971 isc->gatt->ag_physical | 1);
860 } 972 }
861 973
862 if (mem->am_type == 2) { 974 if (mem->am_type == 2) {
863 WRITEGTT(offset, mem->am_physical | 1); 975 agp_i810_write_gtt_entry(isc, offset, mem->am_physical | 1);
864 mem->am_offset = offset; 976 mem->am_offset = offset;
865 mem->am_is_bound = 1; 977 mem->am_is_bound = 1;
866 return 0; 978 return 0;
867 } 979 }
868 980
869 if (mem->am_type != 1) 981 if (mem->am_type != 1)
870 return agp_generic_bind_memory(sc, mem, offset); 982 return agp_generic_bind_memory(sc, mem, offset);
871 983
872 if (isc->chiptype != CHIP_I810) 984 if (isc->chiptype != CHIP_I810)
873 return EINVAL; 985 return EINVAL;
874 986
875 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 987 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
876 WRITEGTT(offset, i | 3); 988 agp_i810_write_gtt_entry(isc, offset, i | 3);
877 mem->am_is_bound = 1; 989 mem->am_is_bound = 1;
878 return 0; 990 return 0;
879} 991}
880 992
881static int 993static int
882agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 994agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem)
883{ 995{
884 struct agp_i810_softc *isc = sc->as_chipc; 996 struct agp_i810_softc *isc = sc->as_chipc;
885 u_int32_t i; 997 u_int32_t i;
886 998
887 if (mem->am_type == 2) { 999 if (mem->am_type == 2) {
888 WRITEGTT(mem->am_offset, 0); 1000 agp_i810_write_gtt_entry(isc, mem->am_offset, 0);
889 mem->am_offset = 0; 1001 mem->am_offset = 0;
890 mem->am_is_bound = 0; 1002 mem->am_is_bound = 0;
891 return 0; 1003 return 0;
892 } 1004 }
893 1005
894 if (mem->am_type != 1) 1006 if (mem->am_type != 1)
895 return agp_generic_unbind_memory(sc, mem); 1007 return agp_generic_unbind_memory(sc, mem);
896 1008
897 if (isc->chiptype != CHIP_I810) 1009 if (isc->chiptype != CHIP_I810)
898 return EINVAL; 1010 return EINVAL;
899 1011
900 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1012 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
901 WRITEGTT(i, 0); 1013 agp_i810_write_gtt_entry(isc, i, 0);
902 mem->am_is_bound = 0; 1014 mem->am_is_bound = 0;
903 return 0; 1015 return 0;
904} 1016}
905 1017
906static bool 1018static bool
907agp_i810_resume(device_t dv PMF_FN_ARGS) 1019agp_i810_resume(device_t dv PMF_FN_ARGS)
908{ 1020{
909 struct agp_softc *sc = device_private(dv); 1021 struct agp_softc *sc = device_private(dv);
910 struct agp_i810_softc *isc = sc->as_chipc; 1022 struct agp_i810_softc *isc = sc->as_chipc;
911 1023
912 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1024 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL);
913 agp_flush_cache(); 1025 agp_flush_cache();
914 1026
cvs diff -r1.19 -r1.19.14.1 src/sys/dev/pci/agpreg.h (expand / switch to unified diff)

--- src/sys/dev/pci/agpreg.h 2008/03/11 13:36:14 1.19
+++ src/sys/dev/pci/agpreg.h 2009/05/05 18:17:57 1.19.14.1
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: agpreg.h,v 1.19 2008/03/11 13:36:14 joerg Exp $ */ 1/* $NetBSD: agpreg.h,v 1.19.14.1 2009/05/05 18:17:57 bouyer Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2000 Doug Rabson 4 * Copyright (c) 2000 Doug Rabson
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -166,30 +166,39 @@ @@ -166,30 +166,39 @@
166#define AGP_I810_MISCC_RPTC_50 0x0080 166#define AGP_I810_MISCC_RPTC_50 0x0080
167#define AGP_I810_MISCC_RPTC_37 0x00c0 167#define AGP_I810_MISCC_RPTC_37 0x00c0
168 168
169/* 169/*
170 * Config registers for i810 device 1 170 * Config registers for i810 device 1
171 */ 171 */
172#define AGP_I810_GMADR 0x10 172#define AGP_I810_GMADR 0x10
173#define AGP_I810_MMADR 0x14 173#define AGP_I810_MMADR 0x14
174 174
175/* 175/*
176 * Memory mapped register offsets for i810 chipset. 176 * Memory mapped register offsets for i810 chipset.
177 */ 177 */
178#define AGP_I810_PGTBL_CTL 0x2020 178#define AGP_I810_PGTBL_CTL 0x2020
179#define AGP_I810_DRT 0x3000 179
180#define AGP_I810_DRT_UNPOPULATED 0x00 180/**
181#define AGP_I810_DRT_POPULATED 0x01 181 * This field determines the actual size of the global GTT on the 965
182#define AGP_I810_GTT 0x10000 182 * and G33
 183 */
 184#define AGP_I810_PGTBL_SIZE_MASK 0x0000000e
 185#define AGP_I810_PGTBL_SIZE_512KB (0 << 1)
 186#define AGP_I810_PGTBL_SIZE_256KB (1 << 1)
 187#define AGP_I810_PGTBL_SIZE_128KB (2 << 1)
 188#define AGP_I810_DRT 0x3000
 189#define AGP_I810_DRT_UNPOPULATED 0x00
 190#define AGP_I810_DRT_POPULATED 0x01
 191#define AGP_I810_GTT 0x10000
183 192
184/* 193/*
185 * Config registers for i830MG device 0 194 * Config registers for i830MG device 0
186 */ 195 */
187#define AGP_I830_GCC0 0x50 196#define AGP_I830_GCC0 0x50
188#define AGP_I830_GCC1 0x52 197#define AGP_I830_GCC1 0x52
189#define AGP_I830_GCC1_DEV2 0x08 198#define AGP_I830_GCC1_DEV2 0x08
190#define AGP_I830_GCC1_DEV2_ENABLED 0x00 199#define AGP_I830_GCC1_DEV2_ENABLED 0x00
191#define AGP_I830_GCC1_DEV2_DISABLED 0x08 200#define AGP_I830_GCC1_DEV2_DISABLED 0x08
192#define AGP_I830_GCC1_GMS 0x70 201#define AGP_I830_GCC1_GMS 0x70
193#define AGP_I830_GCC1_GMS_STOLEN_512 0x20 202#define AGP_I830_GCC1_GMS_STOLEN_512 0x20
194#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 203#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30
195#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 204#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40
@@ -210,56 +219,76 @@ @@ -210,56 +219,76 @@
210#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 219#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10
211#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 220#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20
212#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 221#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30
213#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 222#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40
214#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 223#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50
215 224
216/* 225/*
217 * Config registers for 915G/915GM 226 * Config registers for 915G/915GM
218 */ 227 */
219#define AGP_I915_MMADR 0x10 228#define AGP_I915_MMADR 0x10
220#define AGP_I915_GMADR 0x18 229#define AGP_I915_GMADR 0x18
221#define AGP_I915_GTTADR 0x1c 230#define AGP_I915_GTTADR 0x1c
222#define AGP_I915_GCC1 0x52 231#define AGP_I915_GCC1 0x52
223#define AGP_I915_GCC1_GMS 0x70 232#define AGP_I915_GCC1_GMS 0x70
224#define AGP_I915_GCC1_GMS_STOLEN_0M 0x00 233#define AGP_I915_GCC1_GMS_STOLEN_0M 0x00
225#define AGP_I915_GCC1_GMS_STOLEN_1M 0x10 234#define AGP_I915_GCC1_GMS_STOLEN_1M 0x10
226#define AGP_I915_GCC1_GMS_STOLEN_8M 0x30 235#define AGP_I915_GCC1_GMS_STOLEN_8M 0x30
227#define AGP_I915_GCC1_GMS_STOLEN_16M 0x40 236#define AGP_I915_GCC1_GMS_STOLEN_16M 0x40
228#define AGP_I915_GCC1_GMS_STOLEN_32M 0x50 237#define AGP_I915_GCC1_GMS_STOLEN_32M 0x50
229#define AGP_I915_GCC1_GMS_STOLEN_48M 0x60 238#define AGP_I915_GCC1_GMS_STOLEN_48M 0x60
230#define AGP_I915_GCC1_GMS_STOLEN_64M 0x70 239#define AGP_I915_GCC1_GMS_STOLEN_64M 0x70
231#define AGP_I915_MSAC 0x60 /* upper word */ 240#define AGP_I915_MSAC 0x60 /* upper word */
232#define AGP_I915_MSAC_APER_128M 0x02 241#define AGP_I915_MSAC_APER_128M 0x02
233 242
234/* 243/*
235 * Config registers for 965G/965Q 244 * Config registers for 965G/965Q
236 */ 245 */
237#define AGP_I965_MMADR 0x10 246#define AGP_I965_MMADR 0x10
238#define AGP_I965_GMADR 0x18 247#define AGP_I965_GMADR 0x18
239 248
240#define AGP_I965_GTT 0x80000 249#define AGP_I965_GTT (512*1024)
 250
 251#define AGP_I965_PGTBL_SIZE_1MB (3 << 1)
 252#define AGP_I965_PGTBL_SIZE_2MB (4 << 1)
 253#define AGP_I965_PGTBL_SIZE_1_5MB (5 << 1)
 254
241 255
242/* 256/*
243 * Config registers for G33 257 * Config registers for G33
244 */ 258 */
245#define AGP_G33_PGTBL_SIZE_MASK (3U << 8) 259#define AGP_G33_PGTBL_SIZE_MASK (3U << 8)
246#define AGP_G33_PGTBL_SIZE_1M (1U << 8) 260#define AGP_G33_PGTBL_SIZE_1M (1U << 8)
247#define AGP_G33_PGTBL_SIZE_2M (2U << 8) 261#define AGP_G33_PGTBL_SIZE_2M (2U << 8)
248 262
249#define AGP_G33_GCC1_GMS_STOLEN_128M 0x80 263#define AGP_G33_GCC1_GMS_STOLEN_128M 0x80
250#define AGP_G33_GCC1_GMS_STOLEN_256M 0x90 264#define AGP_G33_GCC1_GMS_STOLEN_256M 0x90
251 265
252/* 266/*
 267 * Config registers for G4X
 268 */
 269#define AGP_G4X_MSAC 0x64 /* upper word */
 270#define AGP_G4X_MSAC_MASK 0xff
 271#define AGP_G4X_MSAC_APER_256M 0x02
 272#define AGP_G4X_MSAC_APER_512M 0x04
 273
 274#define AGP_G4X_GTT (2*1024*1024)
 275
 276#define AGP_G4X_GCC1_GMS_STOLEN_96M 0xa0
 277#define AGP_G4X_GCC1_GMS_STOLEN_160M 0xb0
 278#define AGP_G4X_GCC1_GMS_STOLEN_224M 0xc0
 279#define AGP_G4X_GCC1_GMS_STOLEN_352M 0xd0
 280
 281/*
253 * AMD64 GART registers 282 * AMD64 GART registers
254 */ 283 */
255#define AGP_AMD64_APCTRL 0x90 284#define AGP_AMD64_APCTRL 0x90
256#define AGP_AMD64_APBASE 0x94 285#define AGP_AMD64_APBASE 0x94
257#define AGP_AMD64_ATTBASE 0x98 286#define AGP_AMD64_ATTBASE 0x98
258#define AGP_AMD64_CACHECTRL 0x9c 287#define AGP_AMD64_CACHECTRL 0x9c
259#define AGP_AMD64_APCTRL_GARTEN 0x00000001 288#define AGP_AMD64_APCTRL_GARTEN 0x00000001
260#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e 289#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e
261#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010 290#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010
262#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020 291#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020
263#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040 292#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040
264#define AGP_AMD64_APBASE_MASK 0x00007fff 293#define AGP_AMD64_APBASE_MASK 0x00007fff
265#define AGP_AMD64_ATTBASE_MASK 0xfffffff0 294#define AGP_AMD64_ATTBASE_MASK 0xfffffff0
cvs diff -r1.962.4.2 -r1.962.4.3 src/sys/dev/pci/pcidevs (expand / switch to unified diff)

--- src/sys/dev/pci/pcidevs 2009/05/03 23:14:57 1.962.4.2
+++ src/sys/dev/pci/pcidevs 2009/05/05 18:17:57 1.962.4.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1$NetBSD: pcidevs,v 1.962.4.2 2009/05/03 23:14:57 snj Exp $ 1$NetBSD: pcidevs,v 1.962.4.3 2009/05/05 18:17:57 bouyer Exp $
2 2
3/* 3/*
4 * Copyright (c) 1995, 1996 Christopher G. Demetriou 4 * Copyright (c) 1995, 1996 Christopher G. Demetriou
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -2484,52 +2484,59 @@ product INTEL 82801H_EHCI_2 0x283a 82801 @@ -2484,52 +2484,59 @@ product INTEL 82801H_EHCI_2 0x283a 82801
2484product INTEL 82801H_SMB 0x283e 82801H SMBus Controller 2484product INTEL 82801H_SMB 0x283e 82801H SMBus Controller
2485product INTEL 82801H_EXP_1 0x283f 82801H PCI Express Port #1 2485product INTEL 82801H_EXP_1 0x283f 82801H PCI Express Port #1
2486product INTEL 82801H_EXP_2 0x2841 82801H PCI Express Port #2 2486product INTEL 82801H_EXP_2 0x2841 82801H PCI Express Port #2
2487product INTEL 82801H_EXP_3 0x2843 82801H PCI Express Port #3 2487product INTEL 82801H_EXP_3 0x2843 82801H PCI Express Port #3
2488product INTEL 82801H_EXP_4 0x2845 82801H PCI Express Port #4 2488product INTEL 82801H_EXP_4 0x2845 82801H PCI Express Port #4
2489product INTEL 82801H_EXP_5 0x2847 82801H PCI Express Port #5 2489product INTEL 82801H_EXP_5 0x2847 82801H PCI Express Port #5
2490product INTEL 82801H_EXP_6 0x2849 82801H PCI Express Port #6 2490product INTEL 82801H_EXP_6 0x2849 82801H PCI Express Port #6
2491product INTEL 82801HBM_IDE 0x2850 82801H IDE Controller 2491product INTEL 82801HBM_IDE 0x2850 82801H IDE Controller
2492product INTEL 82801H_HDA 0x284b 82801H High Definition Audio Controller 2492product INTEL 82801H_HDA 0x284b 82801H High Definition Audio Controller
2493product INTEL 82801H_THERMAL 0x284f 82801H Thermal Controller 2493product INTEL 82801H_THERMAL 0x284f 82801H Thermal Controller
2494product INTEL 82801IH_LPC 0x2912 82801IH LPC Interface Bridge 2494product INTEL 82801IH_LPC 0x2912 82801IH LPC Interface Bridge
2495product INTEL 82801IO_LPC 0x2914 82801IO LPC Interface Bridge 2495product INTEL 82801IO_LPC 0x2914 82801IO LPC Interface Bridge
2496product INTEL 82801IR_LPC 0x2916 82801IR LPC Interface Bridge 2496product INTEL 82801IR_LPC 0x2916 82801IR LPC Interface Bridge
 2497product INTEL 82801IEM_LPC 0x2917 82801IEM LPC Interface Bridge
2497product INTEL 82801IB_LPC 0x2918 82801IB LPC Interface Bridge 2498product INTEL 82801IB_LPC 0x2918 82801IB LPC Interface Bridge
 2499product INTEL 82801IM_LPC 0x2919 82801IM LPC Interface Bridge
2498product INTEL 82801I_SATA_1 0x2920 82801I SATA Controller with 4 ports 2500product INTEL 82801I_SATA_1 0x2920 82801I SATA Controller with 4 ports
2499product INTEL 82801I_SATA_2 0x2921 82801I SATA Controller with 2 ports 2501product INTEL 82801I_SATA_2 0x2921 82801I SATA Controller with 2 ports
2500product INTEL 82801I_SATA_AHCI6 0x2922 82801I AHCI SATA Controller with 6 ports 2502product INTEL 82801I_SATA_AHCI6 0x2922 82801I AHCI SATA Controller with 6 ports
2501product INTEL 82801I_SATA_AHCI4 0x2923 82801I AHCI SATA Controller with 4 ports 2503product INTEL 82801I_SATA_AHCI4 0x2923 82801I AHCI SATA Controller with 4 ports
2502product INTEL 82801I_SATA_3 0x2926 82801I SATA Controller with 2 ports 2504product INTEL 82801I_SATA_3 0x2926 82801I SATA Controller with 2 ports
 2505product INTEL 82801I_SATA_4 0x2928 82801I Mobile AHCI SATA Controller with 2 ports
 2506product INTEL 82801I_SATA_5 0x2929 82801I Mobile AHCI SATA Controller with 4 ports
2503product INTEL 82801I_SMB 0x2930 82801I SMBus Controller 2507product INTEL 82801I_SMB 0x2930 82801I SMBus Controller
2504product INTEL 82801I_THERMAL 0x2932 82801I Thermal Controller 2508product INTEL 82801I_THERMAL 0x2932 82801I Thermal Controller
2505product INTEL 82801I_USB_1 0x2934 82801I USB UHCI Controller 2509product INTEL 82801I_USB_1 0x2934 82801I USB UHCI Controller
2506product INTEL 82801I_USB_2 0x2935 82801I USB UHCI Controller 2510product INTEL 82801I_USB_2 0x2935 82801I USB UHCI Controller
2507product INTEL 82801I_USB_3 0x2936 82801I USB UHCI Controller 2511product INTEL 82801I_USB_3 0x2936 82801I USB UHCI Controller
2508product INTEL 82801I_USB_4 0x2937 82801I USB UHCI Controller 2512product INTEL 82801I_USB_4 0x2937 82801I USB UHCI Controller
2509product INTEL 82801I_USB_5 0x2938 82801I USB UHCI Controller 2513product INTEL 82801I_USB_5 0x2938 82801I USB UHCI Controller
2510product INTEL 82801I_USB_6 0x2939 82801I USB UHCI Controller 2514product INTEL 82801I_USB_6 0x2939 82801I USB UHCI Controller
2511product INTEL 82801I_EHCI_1 0x293a 82801I USB EHCI Controller 2515product INTEL 82801I_EHCI_1 0x293a 82801I USB EHCI Controller
2512product INTEL 82801I_EHCI_2 0x293c 82801I USB EHCI Controller 2516product INTEL 82801I_EHCI_2 0x293c 82801I USB EHCI Controller
2513product INTEL 82801I_HDA 0x293e 82801I High Definition Audio Controller 2517product INTEL 82801I_HDA 0x293e 82801I High Definition Audio Controller
2514product INTEL 82801I_EXP_1 0x2940 82801I PCI Express Port #1 2518product INTEL 82801I_EXP_1 0x2940 82801I PCI Express Port #1
2515product INTEL 82801I_EXP_2 0x2942 82801I PCI Express Port #2 2519product INTEL 82801I_EXP_2 0x2942 82801I PCI Express Port #2
2516product INTEL 82801I_EXP_3 0x2944 82801I PCI Express Port #3 2520product INTEL 82801I_EXP_3 0x2944 82801I PCI Express Port #3
2517product INTEL 82801I_EXP_4 0x2946 82801I PCI Express Port #4 2521product INTEL 82801I_EXP_4 0x2946 82801I PCI Express Port #4
2518product INTEL 82801I_EXP_5 0x2948 82801I PCI Express Port #5 2522product INTEL 82801I_EXP_5 0x2948 82801I PCI Express Port #5
2519product INTEL 82801I_EXP_6 0x294a 82801I PCI Express Port #6 2523product INTEL 82801I_EXP_6 0x294a 82801I PCI Express Port #6
2520product INTEL 82801I_IGP_C 0x294c 82801I (C) LAN Controller 2524product INTEL 82801I_IGP_C 0x294c 82801I (C) LAN Controller
2521product INTEL 82946GZ_HB 0x2970 82946GZ Host Bridge 2525product INTEL 82946GZ_HB 0x2970 82946GZ Host Bridge
2522product INTEL 82946GZ_IGD 0x2972 82946GZ Integrated Graphics Device 2526product INTEL 82946GZ_IGD 0x2972 82946GZ Integrated Graphics Device
 2527product INTEL 82G35_HB 0x2980 82G35 Host Bridge
 2528product INTEL 82G35_IGD 0x2982 82G35 Integrated Graphics Device
 2529product INTEL 82G35_IGD_1 0x2983 82G35 Integrated Graphics Device
2523product INTEL 82965Q_HB 0x2990 82965Q Host Bridge 2530product INTEL 82965Q_HB 0x2990 82965Q Host Bridge
2524product INTEL 82965Q_EXP 0x2991 82965Q PCI Express Bridge 2531product INTEL 82965Q_EXP 0x2991 82965Q PCI Express Bridge
2525product INTEL 82965Q_IGD 0x2992 82965Q Integrated Graphics Device 2532product INTEL 82965Q_IGD 0x2992 82965Q Integrated Graphics Device
2526product INTEL 82965Q_IGD_1 0x2993 82965Q Integrated Graphics Device 2533product INTEL 82965Q_IGD_1 0x2993 82965Q Integrated Graphics Device
2527product INTEL 82965G_HB 0x29a0 82965G Host Bridge 2534product INTEL 82965G_HB 0x29a0 82965G Host Bridge
2528product INTEL 82965G_EXP 0x29a1 82965G PCI Express Bridge 2535product INTEL 82965G_EXP 0x29a1 82965G PCI Express Bridge
2529product INTEL 82965G_IGD 0x29a2 82965G Integrated Graphics Device 2536product INTEL 82965G_IGD 0x29a2 82965G Integrated Graphics Device
2530product INTEL 82965G_IGD_1 0x29a3 82965G Integrated Graphics Device 2537product INTEL 82965G_IGD_1 0x29a3 82965G Integrated Graphics Device
2531product INTEL 82Q35_HB 0x29b0 82Q35 Host Bridge 2538product INTEL 82Q35_HB 0x29b0 82Q35 Host Bridge
2532product INTEL 82Q35_EXP 0x29b1 82Q35 PCI Express Bridge 2539product INTEL 82Q35_EXP 0x29b1 82Q35 PCI Express Bridge
2533product INTEL 82Q35_IGD 0x29b2 82Q35 Integrated Graphics Device 2540product INTEL 82Q35_IGD 0x29b2 82Q35 Integrated Graphics Device
2534product INTEL 82Q35_IGD_1 0x29b3 82Q35 Integrated Graphics Device 2541product INTEL 82Q35_IGD_1 0x29b3 82Q35 Integrated Graphics Device
2535product INTEL 82G33_HB 0x29c0 82G33/P35 Host Bridge 2542product INTEL 82G33_HB 0x29c0 82G33/P35 Host Bridge
@@ -2538,26 +2545,35 @@ product INTEL 82G33_IGD 0x29c2 82G33 In @@ -2538,26 +2545,35 @@ product INTEL 82G33_IGD 0x29c2 82G33 In
2538product INTEL 82G33_IGD_1 0x29c3 82G33 Integrated Graphics Device 2545product INTEL 82G33_IGD_1 0x29c3 82G33 Integrated Graphics Device
2539product INTEL 82801I_LAN 0x29c4 82801I LAN Controller 2546product INTEL 82801I_LAN 0x29c4 82801I LAN Controller
2540product INTEL 82Q33_HB 0x29d0 82Q35 Host Bridge 2547product INTEL 82Q33_HB 0x29d0 82Q35 Host Bridge
2541product INTEL 82Q33_EXP 0x29d1 82Q35 PCI Express Bridge 2548product INTEL 82Q33_EXP 0x29d1 82Q35 PCI Express Bridge
2542product INTEL 82Q33_IGD 0x29d2 82Q35 Integrated Graphics Device 2549product INTEL 82Q33_IGD 0x29d2 82Q35 Integrated Graphics Device
2543product INTEL 82Q33_IGD_1 0x29d3 82Q35 Integrated Graphics Device 2550product INTEL 82Q33_IGD_1 0x29d3 82Q35 Integrated Graphics Device
2544product INTEL 82965PM_HB 0x2a00 82965PM Host Bridge 2551product INTEL 82965PM_HB 0x2a00 82965PM Host Bridge
2545product INTEL 80862A01 0x2a01 80862A01 Mobile PCI Express Root Port 2552product INTEL 80862A01 0x2a01 80862A01 Mobile PCI Express Root Port
2546product INTEL 82965PM_IGD 0x2a02 82965PM Integrated Graphics Device 2553product INTEL 82965PM_IGD 0x2a02 82965PM Integrated Graphics Device
2547product INTEL 82965PM_IGD_1 0x2a03 82965PM Integrated Graphics Device 2554product INTEL 82965PM_IGD_1 0x2a03 82965PM Integrated Graphics Device
2548product INTEL 82965PM_MEI 0x2a04 82965PM MEI Controller 2555product INTEL 82965PM_MEI 0x2a04 82965PM MEI Controller
2549product INTEL 82965PM_IDE 0x2a06 82965PM IDE Interface 2556product INTEL 82965PM_IDE 0x2a06 82965PM IDE Interface
2550product INTEL 82965PM_KT 0x2a07 82965PM Serial Interface 2557product INTEL 82965PM_KT 0x2a07 82965PM Serial Interface
 2558product INTEL 82GM45_HB 0x2a40 82GM45 Host Bridge
 2559product INTEL 82GM45_IGD 0x2a42 82GM45 Integrated Graphics Device
 2560product INTEL 82GM45_IGD_1 0x2a43 82GM45 Integrated Graphics Device
 2561product INTEL 82IGD_E_HB 0x2e00 82IGD_E Host Bridge
 2562product INTEL 82IGD_E_IGD 0x2e02 82IGD_E Integrated Graphics
 2563product INTEL 82Q45_HB 0x2e10 82Q45 Host Bridge
 2564product INTEL 82Q45_IGD 0x2e12 82Q45 Integrated Graphics Device
 2565product INTEL 82G45_HB 0x2e20 82G45 Host Bridge
 2566product INTEL 82G45_IGD 0x2e22 82G45 Integrated Graphics Device
2551product INTEL 31244 0x3200 31244 Serial ATA Controller 2567product INTEL 31244 0x3200 31244 Serial ATA Controller
2552product INTEL 82855PM_DDR 0x3340 82855PM MCH Host Controller 2568product INTEL 82855PM_DDR 0x3340 82855PM MCH Host Controller
2553product INTEL 82855PM_AGP 0x3341 82855PM Host-AGP Bridge 2569product INTEL 82855PM_AGP 0x3341 82855PM Host-AGP Bridge
2554product INTEL 82855PM_PM 0x3342 82855PM Power Management Controller 2570product INTEL 82855PM_PM 0x3342 82855PM Power Management Controller
2555product INTEL 63XXESB_EXP_UP 0x3500 63xxESB PCI Express Upstream Port 2571product INTEL 63XXESB_EXP_UP 0x3500 63xxESB PCI Express Upstream Port
2556product INTEL 63XXESB_PCIX 0x350c 63xxESB PCI Express to PCI-X Bridge 2572product INTEL 63XXESB_PCIX 0x350c 63xxESB PCI Express to PCI-X Bridge
2557product INTEL 63XXESB_EXP_DN_1 0x3510 63xxESB PCI Express Downstream Port #1 2573product INTEL 63XXESB_EXP_DN_1 0x3510 63xxESB PCI Express Downstream Port #1
2558product INTEL 63XXESB_EXP_DN_2 0x3514 63xxESB PCI Express Downstream Port #2 2574product INTEL 63XXESB_EXP_DN_2 0x3514 63xxESB PCI Express Downstream Port #2
2559product INTEL 63XXESB_EXP_DN_3 0x3518 63xxESB PCI Express Downstream Port #3 2575product INTEL 63XXESB_EXP_DN_3 0x3518 63xxESB PCI Express Downstream Port #3
2560product INTEL 82830MP_IO_1 0x3575 82830MP CPU to I/O Bridge 1 2576product INTEL 82830MP_IO_1 0x3575 82830MP CPU to I/O Bridge 1
2561product INTEL 82830MP_AGP 0x3576 82830MP CPU to AGP Bridge 2577product INTEL 82830MP_AGP 0x3576 82830MP CPU to AGP Bridge
2562product INTEL 82830MP_IV 0x3577 82830MP Integrated Video 2578product INTEL 82830MP_IV 0x3577 82830MP Integrated Video
2563product INTEL 82830MP_IO_2 0x3578 82830MP CPU to I/O Bridge 2 2579product INTEL 82830MP_IO_2 0x3578 82830MP CPU to I/O Bridge 2