Wed May 27 00:32:10 2009 UTC ()
add a bunch of register definitions


(macallan)
diff -r1.4 -r1.5 src/sys/dev/sbus/p9100reg.h
cvs diff -r1.4 -r1.5 src/sys/dev/sbus/p9100reg.h (expand / switch to unified diff)

--- src/sys/dev/sbus/p9100reg.h 2008/04/28 20:23:57 1.4
+++ src/sys/dev/sbus/p9100reg.h 2009/05/27 00:32:10 1.5
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: p9100reg.h,v 1.4 2008/04/28 20:23:57 martin Exp $ */ 1/* $NetBSD: p9100reg.h,v 1.5 2009/05/27 00:32:10 macallan Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas. 8 * by Matt Thomas.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -40,61 +40,134 @@ @@ -40,61 +40,134 @@
40#define VIDEO_ENABLED 0x00000020 40#define VIDEO_ENABLED 0x00000020
41#define PWRUP_CNFG 0x0194 /* Power Up Configuration */ 41#define PWRUP_CNFG 0x0194 /* Power Up Configuration */
42#define DAC_CMAP_WRIDX 0x0200 /* IBM RGB528 Palette Address (Write) */ 42#define DAC_CMAP_WRIDX 0x0200 /* IBM RGB528 Palette Address (Write) */
43#define DAC_CMAP_DATA 0x0204 /* IBM RGB528 Palette Data */ 43#define DAC_CMAP_DATA 0x0204 /* IBM RGB528 Palette Data */
44#define DAC_PXL_MASK 0x0208 /* IBM RGB528 Pixel Mask */ 44#define DAC_PXL_MASK 0x0208 /* IBM RGB528 Pixel Mask */
45#define DAC_CMAP_RDIDX 0x020c /* IBM RGB528 Palette Address (Read) */ 45#define DAC_CMAP_RDIDX 0x020c /* IBM RGB528 Palette Address (Read) */
46#define DAC_INDX_LO 0x0210 /* IBM RGB528 Index Low */ 46#define DAC_INDX_LO 0x0210 /* IBM RGB528 Index Low */
47#define DAC_INDX_HI 0x0214 /* IBM RGB528 Index High */ 47#define DAC_INDX_HI 0x0214 /* IBM RGB528 Index High */
48#define DAC_INDX_DATA 0x0218 /* IBM RGB528 Index Data (Indexed Registers) */ 48#define DAC_INDX_DATA 0x0218 /* IBM RGB528 Index Data (Indexed Registers) */
49#define DAC_INDX_CTL 0x021c /* IBM RGB528 Index Control */ 49#define DAC_INDX_CTL 0x021c /* IBM RGB528 Index Control */
50 #define DAC_INDX_AUTOINCR 0x01 50 #define DAC_INDX_AUTOINCR 0x01
51  51
52#define DAC_VERSION 0x01 52#define DAC_VERSION 0x01
53#define DAC_POWER 0x05 53#define DAC_MISC_CLK 0x02
 54#define DAC_POWER_MGT 0x05
54 #define DAC_POWER_SCLK_DISABLE 0x10 55 #define DAC_POWER_SCLK_DISABLE 0x10
55 #define DAC_POWER_DDOT_DISABLE 0x08 56 #define DAC_POWER_DDOT_DISABLE 0x08
56 #define DAC_POWER_SYNC_DISABLE 0x04 57 #define DAC_POWER_SYNC_DISABLE 0x04
57 /* Disable internal DAC clock */ 58 /* Disable internal DAC clock */
58 #define DAC_POWER_ICLK_DISABLE 0x02 59 #define DAC_POWER_ICLK_DISABLE 0x02
59 /* Disable internal DAC power */ 60 /* Disable internal DAC power */
60 #define DAC_POWER_IPWR_DISABLE 0x01  61 #define DAC_POWER_IPWR_DISABLE 0x01
61 62#define DAC_OPERATION 0x06
 63 #define DAC_SYNC_ON_GREEN 0x08
 64#define DAC_PALETTE_CTRL 0x07
 65#define DAC_PIXEL_FMT 0x0a
 66#define DAC_8BIT_CTRL 0x0b
 67 #define DAC8_DIRECT_COLOR 0x01
 68#define DAC_16BIT_CTRL 0x0c
 69 #define DAC16_INDIRECT_COLOR 0x00
 70 #define DAC16_DYNAMIC_COLOR 0x40
 71 #define DAC16_DIRECT_COLOR 0xc0
 72 #define DAC16_BYPASS_POLARITY 0x20
 73 #define DAC16_BIT_FILL_LINEAR 0x04
 74 #define DAC16_555 0x00
 75 #define DAC16_565 0x02
 76 #define DAC16_CONTIGUOUS 0x01
 77#define DAC_24BIT_CTRL 0x0d
 78 #define DAC24_DIRECT_COLOR 0x01
 79#define DAC_32BIT_CTRL 0x0e
 80 #define DAC32_BYPASS_POLARITY 0x04
 81 #define DAC32_INDIRECT_COLOR 0x00
 82 #define DAC32_DYNAMIC_COLOR 0x01
 83 #define DAC32_DIRECT_COLOR 0x03
 84#define DAC_VCO_DIV 0x16
 85#define DAC_PLL0 0x20
 86#define DAC_MISC_1 0x70
 87#define DAC_MISC_2 0x71
 88#define DAC_MISC_3 0x72
 89
62#define DAC_CURSOR_CTL 0x30 90#define DAC_CURSOR_CTL 0x30
63 #define DAC_CURSOR_OFF 0x00 91 #define DAC_CURSOR_OFF 0x00
64 #define DAC_CURSOR_WIN 0x02 92 #define DAC_CURSOR_WIN 0x02
65 #define DAC_CURSOR_X11 0x03 93 #define DAC_CURSOR_X11 0x03
66 #define DAC_CURSOR_64 0x04 /* clear for 32x32 cursor */ 94 #define DAC_CURSOR_64 0x04 /* clear for 32x32 cursor */
67#define DAC_CURSOR_X 0x31 /* 8-low, 8-high */ 95#define DAC_CURSOR_X 0x31 /* 8-low, 8-high */
68#define DAC_CURSOR_Y 0x33 /* 8-low, 8-high */ 96#define DAC_CURSOR_Y 0x33 /* 8-low, 8-high */
69#define DAC_CURSOR_HOT_X 0x35 /* hotspot */ 97#define DAC_CURSOR_HOT_X 0x35 /* hotspot */
70#define DAC_CURSOR_HOT_Y 0x36 98#define DAC_CURSOR_HOT_Y 0x36
71#define DAC_CURSOR_COL_1 0x40 /* red. green and blue */ 99#define DAC_CURSOR_COL_1 0x40 /* red. green and blue */
72#define DAC_CURSOR_COL_2 0x43  100#define DAC_CURSOR_COL_2 0x43
73#define DAC_CURSOR_COL_3 0x46  101#define DAC_CURSOR_COL_3 0x46
74#define DAC_PIX_PLL 0x8e 102#define DAC_PIX_PLL 0x8e
75#define DAC_CURSOR_DATA 0x100 103#define DAC_CURSOR_DATA 0x100
76 104
 105/* main registers */
 106#define SYS_CONF 0x0004 /* System Configuration Register */
 107 #define BUFFER_WRITE_1 0x0200 /* writes got o buffer 1 */
 108 #define BUFFER_WRITE_0 0x0000 /* writes go to buffer 0 */
 109 #define BUFFER_READ_1 0x0400 /* read from buffer 1 */
 110 #define BUFFER_READ_0 0x0000
 111 #define MEM_SWAP_BITS 0x0800 /* swap bits when accessing VRAM */
 112 #define MEM_SWAP_BYTES 0x1000 /* swap bytes when accessing VRAM */
 113 #define MEM_SWAP_HWORDS 0x2000 /* swap halfwords when accessing VRAM */
 114 #define SHIFT_0 14
 115 #define SHIFT_1 17
 116 #define SHIFT_2 20
 117 #define SHIFT_3 29
 118 #define PIXEL_SHIFT 26
 119 #define SWAP_SHIFT 11
 120 /* this is what the 3GX manual says */
 121 #define SC_8BIT 2
 122 #define SC_16BIT 3
 123 #define SC_24BIT 7
 124 #define SC_32BIT 5
 125
 126/* video controller registers */
 127#define VID_HCOUNTER 0x104
 128#define VID_HTOTAL 0x108
 129#define VID_HSRE 0x10c /* hsync raising edge */
 130#define VID_HBRE 0x110 /* hblank raising edge */
 131#define VID_HBFE 0x114 /* hblank falling edge */
 132#define VID_HCNTPRLD 0x118 /* hcounter preload */
 133#define VID_VCOUNTER 0x11c /* vcounter */
 134#define VID_VLENGTH 0x120 /* lines, including blanks */
 135#define VID_VSRE 0x124 /* vsync raising edge */
 136#define VID_VBRE 0x128 /* vblank raising edge */
 137#define VID_VBFE 0x12c /* vblank falling edge */
 138#define VID_VCNTPRLD 0x130 /* vcounter preload */
 139#define VID_SRADDR 0x134 /* screen repaint address */
 140#define VID_SRTC 0x138 /* screen repaint timing control */
 141#define VID_QSFCNTR 0x13c /* QSF counter */
 142
 143#define VID_MEM_CONFIG 0x184 /* memory config */
 144#define VID_RFPERIOD 0x188 /* refresh period */
 145#define VID_RFCOUNT 0x18c /* refresh counter */
 146#define VID_RLMAX 0x190 /* RAS low max */
 147#define VID_RLCUR 0x194 /* RAS low current */
 148#define VID_DACSYNC 0x198 /* read after last DAC access */
 149
77#define ENGINE_STATUS 0x2000 /* drawing engine status register */ 150#define ENGINE_STATUS 0x2000 /* drawing engine status register */
78 #define BLITTER_BUSY 0x80000000 151 #define BLITTER_BUSY 0x80000000
79 #define ENGINE_BUSY 0x40000000 152 #define ENGINE_BUSY 0x40000000
80#define COMMAND_BLIT 0x2004 153#define COMMAND_BLIT 0x2004
81#define COMMAND_QUAD 0x2008 154#define COMMAND_QUAD 0x2008
82/* pixel data for monochrome colour expansion */ 155/* pixel data for monochrome colour expansion */
83#define PIXEL_1 0x2080  156#define PIXEL_1 0x2080
84/* apparently bits 2-6 control how many pixels we write - n+1 */ 157/* apparently bits 2-6 control how many pixels we write - n+1 */
85 158
86/* drawing engine registers */ 159/* drawing engine registers */
87#define COORD_INDEX 0x218c 160#define COORD_INDEX 0x218c
88#define WINDOW_OFFSET 0x2190 161#define WINDOW_OFFSET 0x2190
89 162
90#define FOREGROUND_COLOR 0x2200 163#define FOREGROUND_COLOR 0x2200
91#define BACKGROUND_COLOR 0x2204 164#define BACKGROUND_COLOR 0x2204
92#define PLANE_MASK 0x2208 165#define PLANE_MASK 0x2208
93#define DRAW_MODE 0x220c  166#define DRAW_MODE 0x220c
94#define PATTERN_ORIGIN_X 0x2210 167#define PATTERN_ORIGIN_X 0x2210
95#define PATTERN_ORIGIN_Y 0x2214 168#define PATTERN_ORIGIN_Y 0x2214
96#define RASTER_OP 0x2218 169#define RASTER_OP 0x2218
97 #define ROP_NO_SOLID 0x02000 /* if set use pattern instead of color for quad operations */ 170 #define ROP_NO_SOLID 0x02000 /* if set use pattern instead of color for quad operations */
98 #define ROP_2BIT_PATTERN 0x04000 /* 4-colour pattern instead of mono */ 171 #define ROP_2BIT_PATTERN 0x04000 /* 4-colour pattern instead of mono */
99 #define ROP_PIX1_TRANS 0x08000 /* transparent background in mono */ 172 #define ROP_PIX1_TRANS 0x08000 /* transparent background in mono */
100 #define ROP_OVERSIZE 0x10000 173 #define ROP_OVERSIZE 0x10000