 @@ -1,1770 +1,1734 @@
-/*	$NetBSD: cpu.c,v 1.214 2009/05/18 01:36:11 mrg Exp $ */
+/*	$NetBSD: cpu.c,v 1.215 2009/05/27 02:19:49 mrg Exp $ */
 /*
  * Copyright (c) 1996
  *	The President and Fellows of Harvard College. All rights reserved.
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
  * must display the following acknowledgement:
  *	This product includes software developed by Harvard University.
  *	This product includes software developed by the University of
  *	California, Lawrence Berkeley Laboratory.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
+ *
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Aaron Brown and
  *	Harvard University.
  *	This product includes software developed by the University of
  *	California, Berkeley and its contributors.
  * 4. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)cpu.c	8.5 (Berkeley) 11/23/93
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.214 2009/05/18 01:36:11 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.215 2009/05/27 02:19:49 mrg Exp $");
 #include "opt_multiprocessor.h"
 #include "opt_lockdebug.h"
 #include "opt_ddb.h"
 #include "opt_sparc_arch.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <sys/simplelock.h>
 #include <sys/kernel.h>
 #include <uvm/uvm.h>
 #include <machine/promlib.h>
 #include <machine/autoconf.h>
 #include <machine/cpu.h>
 #include <machine/reg.h>
 #include <machine/ctlreg.h>
 #include <machine/trap.h>
 #include <machine/pcb.h>
 #include <machine/pmap.h>
 #if defined(MULTIPROCESSOR) && defined(DDB)
 #include <machine/db_machdep.h>
 #endif
 #include <sparc/sparc/cache.h>
 #include <sparc/sparc/asm.h>
 #include <sparc/sparc/cpuvar.h>
 #include <sparc/sparc/memreg.h>
 #if defined(SUN4D)
 #include <sparc/sparc/cpuunitvar.h>
 #endif
 struct cpu_softc {
 	struct device	sc_dev;		/* generic device info */
 	struct cpu_info	*sc_cpuinfo;
 };
 /* The following are used externally (sysctl_hw). */
 char	machine[] = MACHINE;		/* from <machine/param.h> */
 char	machine_arch[] = MACHINE_ARCH;	/* from <machine/param.h> */
 int	cpu_arch;			/* sparc architecture version */
 char	cpu_model[100];			/* machine model (primary CPU) */
 extern char machine_model[];
 int	sparc_ncpus;			/* # of CPUs detected by PROM */
-#ifdef MULTIPROCESSOR
+struct cpu_info *cpus[_MAXNCPU];	/* we only support 4 CPUs. */
 struct cpu_info *cpus[4];		/* we only support 4 CPUs. */
 u_int	cpu_ready_mask;			/* the set of CPUs marked as READY */
 #endif
 /* The CPU configuration driver. */
 static void cpu_mainbus_attach(struct device *, struct device *, void *);
 int  cpu_mainbus_match(struct device *, struct cfdata *, void *);
 CFATTACH_DECL(cpu_mainbus, sizeof(struct cpu_softc),
     cpu_mainbus_match, cpu_mainbus_attach, NULL, NULL);
 #if defined(SUN4D)
 static int cpu_cpuunit_match(struct device *, struct cfdata *, void *);
 static void cpu_cpuunit_attach(struct device *, struct device *, void *);
 CFATTACH_DECL(cpu_cpuunit, sizeof(struct cpu_softc),
     cpu_cpuunit_match, cpu_cpuunit_attach, NULL, NULL);
 #endif /* SUN4D */
 static void cpu_attach(struct cpu_softc *, int, int);
 static const char *fsrtoname(int, int, int);
 void cache_print(struct cpu_softc *);
 void cpu_setup(void);
 void fpu_init(struct cpu_info *);
 #define	IU_IMPL(psr)	((u_int)(psr) >> 28)
 #define	IU_VERS(psr)	(((psr) >> 24) & 0xf)
 #define SRMMU_IMPL(mmusr)	((u_int)(mmusr) >> 28)
 #define SRMMU_VERS(mmusr)	(((mmusr) >> 24) & 0xf)
 int bootmid;		/* Module ID of boot CPU */
 #if defined(MULTIPROCESSOR)
 void cpu_spinup(struct cpu_info *);
 static void init_cpuinfo(struct cpu_info *, int);
 int go_smp_cpus = 0;	/* non-primary CPUs wait for this to go */
 /* lock this to send IPI's */
 struct simplelock xpmsg_lock = SIMPLELOCK_INITIALIZER;
 static void
 init_cpuinfo(struct cpu_info *cpi, int node)
 	vaddr_t intstack, va;
 	/*
 	 * Finish initialising this cpu_info.
 	 */
 	getcpuinfo(cpi, node);
 	/*
 	 * Arrange interrupt stack.  This cpu will also abuse the bottom
 	 * half of the interrupt stack before it gets to run its idle LWP.
 	 */
 	intstack = uvm_km_alloc(kernel_map, INT_STACK_SIZE, 0, UVM_KMF_WIRED);
 	if (intstack == 0)
 		panic("%s: no uspace/intstack", __func__);
 	cpi->eintstack = (void*)(intstack + INT_STACK_SIZE);
 	/* Allocate virtual space for pmap page_copy/page_zero */
 	va = uvm_km_alloc(kernel_map, 2*PAGE_SIZE, 0, UVM_KMF_VAONLY);
 	if (va == 0)
 		panic("%s: no virtual space", __func__);
 	cpi->vpage[0] = (void *)(va + 0);
 	cpi->vpage[1] = (void *)(va + PAGE_SIZE);
 #endif /* MULTIPROCESSOR */
 #ifdef notdef
 /*
  * IU implementations are parceled out to vendors (with some slight
  * glitches).  Printing these is cute but takes too much space.
  */
 static char *iu_vendor[16] = {
 	"Fujitsu",	/* and also LSI Logic */
 	"ROSS",		/* ROSS (ex-Cypress) */
 	"BIT",
 	"LSIL",		/* LSI Logic finally got their own */
 	"TI",		/* Texas Instruments */
 	"Matsushita",
 	"Philips",
 	"Harvest",	/* Harvest VLSI Design Center */
 	"SPEC",		/* Systems and Processes Engineering Corporation */
 	"Weitek",
 	"vendor#10",
 	"vendor#11",
 	"vendor#12",
 	"vendor#13",
 	"vendor#14",
 	"vendor#15"
 };
 #endif
 #if defined(MULTIPROCESSOR)
 u_int	cpu_ready_mask;			/* the set of CPUs marked as READY */
 void cpu_spinup(struct cpu_info *);
 static void cpu_attach_non_boot(struct cpu_softc *, struct cpu_info *, int);
 int go_smp_cpus = 0;	/* non-primary CPUs wait for this to go */
 /*
  * This must be locked around all message transactions to ensure only
  * one CPU is generating them.
  */
 static kmutex_t xpmsg_mutex;
 #endif /* MULTIPROCESSOR */
 /*
  * 4/110 comment: the 4/110 chops off the top 4 bits of an OBIO address.
  *	this confuses autoconf.  for example, if you try and map
  *	0xfe000000 in obio space on a 4/110 it actually maps 0x0e000000.
  *	this is easy to verify with the PROM.   this causes problems
  *	with devices like "esp0 at obio0 addr 0xfa000000" because the
  *	4/110 treats it as esp0 at obio0 addr 0x0a000000" which is the
  *	address of the 4/110's "sw0" scsi chip.   the same thing happens
  *	between zs1 and zs2.    since the sun4 line is "closed" and
  *	we know all the "obio" devices that will ever be on it we just
  *	put in some special case "if"'s in the match routines of esp,
  *	dma, and zs.
  */
 int
 cpu_mainbus_match(struct device *parent, struct cfdata *cf, void *aux)
+{
 	struct mainbus_attach_args *ma = aux;
 	return (strcmp(cf->cf_name, ma->ma_name) == 0);
+}
 static void
 cpu_mainbus_attach(struct device *parent, struct device *self, void *aux)
+{
 	struct mainbus_attach_args *ma = aux;
 	struct { uint32_t va; uint32_t size; } *mbprop = NULL;
 	struct openprom_addr *rrp = NULL;
 	struct cpu_info *cpi;
 	int mid, node;
 	int error, n;
 	node = ma->ma_node;
 	mid = (node != 0) ? prom_getpropint(node, "mid", 0) : 0;
 	cpu_attach((struct cpu_softc *)self, node, mid);
 	cpi = ((struct cpu_softc *)self)->sc_cpuinfo;
 	if (cpi == NULL)
 		return;
 	/*
 	 * Map CPU mailbox if available
 	 */
 	if (node != 0 && (error = prom_getprop(node, "mailbox-virtual",
 					sizeof(*mbprop),
 					&n, &mbprop)) == 0) {
 		cpi->mailbox = mbprop->va;
 		free(mbprop, M_DEVBUF);
 	} else if (node != 0 && (error = prom_getprop(node, "mailbox",
 					sizeof(struct openprom_addr),
 					&n, &rrp)) == 0) {
 		/* XXX - map cached/uncached? If cached, deal with
 		 *	 cache congruency!
 		 */
 		if (rrp[0].oa_space == 0)
 			printf("%s: mailbox in mem space\n", self->dv_xname);
 		if (bus_space_map(ma->ma_bustag,
 				BUS_ADDR(rrp[0].oa_space, rrp[0].oa_base),
 				rrp[0].oa_size,
 				BUS_SPACE_MAP_LINEAR,
 				&cpi->mailbox) != 0)
 			panic("%s: can't map CPU mailbox", self->dv_xname);
 		free(rrp, M_DEVBUF);
+	}
 	/*
 	 * Map Module Control Space if available
 	 */
 	if (cpi->mxcc == 0)
 		/* We only know what it means on MXCCs */
 		return;
 	rrp = NULL;
 	if (node == 0 || (error = prom_getprop(node, "reg",
 					sizeof(struct openprom_addr),
 					&n, &rrp)) != 0)
 		return;
 	/* register set #0 is the MBus port register */
 	if (bus_space_map(ma->ma_bustag,
 			BUS_ADDR(rrp[0].oa_space, rrp[0].oa_base),
 			rrp[0].oa_size,
 			BUS_SPACE_MAP_LINEAR,
 			&cpi->ci_mbusport) != 0) {
 		panic("%s: can't map CPU regs", self->dv_xname);
+	}
 	/* register set #1: MCXX control */
 	if (bus_space_map(ma->ma_bustag,
 			BUS_ADDR(rrp[1].oa_space, rrp[1].oa_base),
 			rrp[1].oa_size,
 			BUS_SPACE_MAP_LINEAR,
 			&cpi->ci_mxccregs) != 0) {
 		panic("%s: can't map CPU regs", self->dv_xname);
+	}
 	/* register sets #3 and #4 are E$ cache data and tags */
 	free(rrp, M_DEVBUF);
+}
 #if defined(SUN4D)
 static int
 cpu_cpuunit_match(struct device *parent, struct cfdata *cf, void *aux)
+{
 	struct cpuunit_attach_args *cpua = aux;
 	return (strcmp(cf->cf_name, cpua->cpua_type) == 0);
+}
 static void
 cpu_cpuunit_attach(struct device *parent, struct device *self, void *aux)
+{
 	struct cpuunit_attach_args *cpua = aux;
 	cpu_attach((struct cpu_softc *)self, cpua->cpua_node,
 	    cpua->cpua_device_id);
+}
 #endif /* SUN4D */
 /*
  * Attach the CPU.
  * Discover interesting goop about the virtual address cache
  * (slightly funny place to do it, but this is where it is to be found).
  */
 static void
 cpu_attach(struct cpu_softc *sc, int node, int mid)
+{
 	char buf[100];
 	struct cpu_info *cpi;
 	int idx;
 	static int cpu_attach_count = 0;
 	/*
 	 * The first CPU we're attaching must be the boot CPU.
 	 * (see autoconf.c and cpuunit.c)
 	 */
 	idx = cpu_attach_count++;
 	if (cpu_attach_count == 1) {
 		getcpuinfo(&cpuinfo, node);
 #if defined(MULTIPROCESSOR)
 		cpi = sc->sc_cpuinfo = cpus[idx];
 #else
 		/* The `local' VA is global for uniprocessor. */
 		cpi = sc->sc_cpuinfo = (struct cpu_info *)CPUINFO_VA;
 #endif
 		cpi->master = 1;
 		cpi->eintstack = eintstack;
 		/* Note: `curpcb' is set to `proc0' in locore */
 		/*
 		 * If we haven't been able to determine the Id of the
 		 * boot CPU, set it now. In this case we can only boot
 		 * from CPU #0 (see also the CPU attach code in autoconf.c)
 		 */
 		if (bootmid == 0)
 			bootmid = mid;
 	} else {
 #if defined(MULTIPROCESSOR)
 		int error;
 		/*
 		 * Initialise this cpu's cpu_info.
 		 */
 		cpi = sc->sc_cpuinfo = cpus[idx];
 		init_cpuinfo(cpi, node);
-		/*
+#if !defined(MULTIPROCESSOR)
-		 * Call the MI attach which creates an idle LWP for us.
+	if (cpu_attach_count > 1) {
 		 */
 		error = mi_cpu_attach(cpi);
 		if (error != 0) {
 			aprint_normal("\n");
 			aprint_error("%s: mi_cpu_attach failed with %d\n",
 			    sc->sc_dev.dv_xname, error);
 			return;
 		/*
 		 * Note: `eintstack' is set in init_cpuinfo() above.
 		 * The %wim register will be initialized in cpu_hatch().
 		 */
 		cpi->ci_curlwp = cpi->ci_data.cpu_idlelwp;
 		cpi->curpcb = (struct pcb *)cpi->ci_curlwp->l_addr;
 		cpi->curpcb->pcb_wim = 1;
 #else
 		sc->sc_cpuinfo = NULL;
 		printf(": no SMP support in kernel\n");
 		return;
 #endif
+	}
 #ifdef DEBUG
 	cpi->redzone = (void *)((long)cpi->eintstack + REDSIZE);
 #endif
 	/*
 	 * Initialise this cpu's cpu_info.
 	 */
 	cpi = sc->sc_cpuinfo = cpus[idx];
 	getcpuinfo(cpi, node);
 	cpi->ci_cpuid = idx;
 	cpi->mid = mid;
 	cpi->node = node;
 #ifdef DEBUG
 	cpi->redzone = (void *)((long)cpi->eintstack + REDSIZE);
 #endif
 	if (sparc_ncpus > 1) {
 		printf(": mid %d", mid);
 		if (mid == 0 && !CPU_ISSUN4D)
 			printf(" [WARNING: mid should not be 0]");
+	}
 #if defined(MULTIPROCESSOR)
 	if (cpu_attach_count > 1) {
 		cpu_attach_non_boot(sc, cpi, node);
 		return;
+	}
 #endif /* MULTIPROCESSOR */
 	/* Stuff to only run on the boot CPU */
 	cpu_setup();
 	snprintf(buf, sizeof buf, "%s @ %s MHz, %s FPU",
 		cpi->cpu_name, clockfreq(cpi->hz), cpi->fpu_name);
 	snprintf(cpu_model, sizeof cpu_model, "%s (%s)",
 		machine_model, buf);
 	printf(": %s\n", buf);
 	cache_print(sc);
 	cpi->master = 1;
 	cpi->eintstack = eintstack;
 	/*
 	 * If we haven't been able to determine the Id of the
 	 * boot CPU, set it now. In this case we can only boot
 	 * from CPU #0 (see also the CPU attach code in autoconf.c)
 	 */
 	if (bootmid == 0)
 		bootmid = mid;
+}
 /*
  * Finish CPU attach.
  * Must be run by the CPU which is being attached.
  */
 void
 cpu_setup(void)
+{
  	if (cpuinfo.hotfix)
 		(*cpuinfo.hotfix)(&cpuinfo);
 	/* Initialize FPU */
 	fpu_init(&cpuinfo);
 	/* Enable the cache */
 	cpuinfo.cache_enable();
 	cpuinfo.flags |= CPUFLG_HATCHED;
+}
 #if defined(MULTIPROCESSOR)
 /*
  * Perform most of the tasks needed for a non-boot CPU.
  */
 static void
 cpu_attach_non_boot(struct cpu_softc *sc, struct cpu_info *cpi, int node)
+{
 	vaddr_t intstack, va;
 	int error;
 	/*
 	 * Arrange interrupt stack.  This cpu will also abuse the bottom
 	 * half of the interrupt stack before it gets to run its idle LWP.
 	 */
 	intstack = uvm_km_alloc(kernel_map, INT_STACK_SIZE, 0, UVM_KMF_WIRED);
 	if (intstack == 0)
 		panic("%s: no uspace/intstack", __func__);
 	cpi->eintstack = (void*)(intstack + INT_STACK_SIZE);
-	if (cpi->master) {
+	/* Allocate virtual space for pmap page_copy/page_zero */
-		char buf[100];
+	va = uvm_km_alloc(kernel_map, 2*PAGE_SIZE, 0, UVM_KMF_VAONLY);
 	if (va == 0)
 		panic("%s: no virtual space", __func__);
-		cpu_setup();
+	cpi->vpage[0] = (void *)(va + 0);
-		snprintf(buf, sizeof buf, "%s @ %s MHz, %s FPU",
+	cpi->vpage[1] = (void *)(va + PAGE_SIZE);
 			cpi->cpu_name, clockfreq(cpi->hz), cpi->fpu_name);
-		snprintf(cpu_model, sizeof cpu_model, "%s (%s)",
+	/*
-			machine_model, buf);
+	 * Call the MI attach which creates an idle LWP for us.
-		printf(": %s\n", buf);
+	 */
-		cache_print(sc);
+	error = mi_cpu_attach(cpi);
 	if (error != 0) {
 		aprint_normal("\n");
 		aprint_error("%s: mi_cpu_attach failed with %d\n",
 		    sc->sc_dev.dv_xname, error);
 		return;
+	}
-#if defined(MULTIPROCESSOR)
+	/*
 	 * Note: `eintstack' is set in init_cpuinfo() above.
 	 * The %wim register will be initialized in cpu_hatch().
 	 */
 	cpi->ci_curlwp = cpi->ci_data.cpu_idlelwp;
 	cpi->curpcb = (struct pcb *)cpi->ci_curlwp->l_addr;
 	cpi->curpcb->pcb_wim = 1;
 	/* for now use the fixed virtual addresses setup in autoconf.c */
 	cpi->intreg_4m = (struct icr_pi *)
-		(PI_INTR_VA + (_MAXNBPG * CPU_MID2CPUNO(mid)));
+		(PI_INTR_VA + (_MAXNBPG * CPU_MID2CPUNO(cpi->mid)));
 	/* Now start this CPU */
 	cpu_spinup(cpi);
 	printf(": %s @ %s MHz, %s FPU\n", cpi->cpu_name,
 		clockfreq(cpi->hz), cpi->fpu_name);
 	cache_print(sc);
-	if (sparc_ncpus > 1 && idx == sparc_ncpus-1) {
+	/*
 	 * Now we're on the last CPU to be attaching.
 	 */
 	if (sparc_ncpus > 1 && cpi->ci_cpuid == sparc_ncpus - 1) {
 		CPU_INFO_ITERATOR n;
 		/*
 		 * Install MP cache flush functions, unless the
 		 * single-processor versions are no-ops.
 		 */
 		for (CPU_INFO_FOREACH(n, cpi)) {
 #define SET_CACHE_FUNC(x) \
 	if (cpi->x != __CONCAT(noop_,x)) cpi->x = __CONCAT(smp_,x)
 			SET_CACHE_FUNC(vcache_flush_page);
 			SET_CACHE_FUNC(vcache_flush_segment);
 			SET_CACHE_FUNC(vcache_flush_region);
 			SET_CACHE_FUNC(vcache_flush_context);
+		}
+	}
-#endif /* MULTIPROCESSOR */
+#undef SET_CACHE_FUNC
+}
 #if defined(MULTIPROCESSOR)
 /*
  * Start secondary processors in motion.
  */
 void
 cpu_boot_secondary_processors(void)
+{
 	CPU_INFO_ITERATOR n;
 	struct cpu_info *cpi;
 	printf("cpu0: booting secondary processors:");
 	for (CPU_INFO_FOREACH(n, cpi)) {
 		if (cpuinfo.mid == cpi->mid ||
 		    (cpi->flags & CPUFLG_HATCHED) == 0)
 			continue;
 		printf(" cpu%d", cpi->ci_cpuid);
 		cpi->flags |= CPUFLG_READY;
 		cpu_ready_mask |= (1 << n);
+	}
 	/* Mark the boot CPU as ready */
 	cpuinfo.flags |= CPUFLG_READY;
 	cpu_ready_mask |= (1 << 0);
 	/* Tell the other CPU's to start up.  */
 	go_smp_cpus = 1;
 	printf("\n");
+}
 #endif /* MULTIPROCESSOR */
 /*
- * Finish CPU attach.
+ * Early initialisation, before main().
  * Must be run by the CPU which is being attached.
  */
 void
-cpu_setup(void)
+cpu_init_system(void)
+{
  	if (cpuinfo.hotfix)
 		(*cpuinfo.hotfix)(&cpuinfo);
 	/* Initialize FPU */
 	fpu_init(&cpuinfo);
-	/* Enable the cache */
+	mutex_init(&xpmsg_mutex, MUTEX_SPIN, IPL_VM);
 	cpuinfo.cache_enable();
 	cpuinfo.flags |= CPUFLG_HATCHED;
+}
 #if defined(MULTIPROCESSOR)
 extern void cpu_hatch(void); /* in locore.s */
 /*
  * Allocate per-CPU data, then start up this CPU using PROM.
  */
 void
 cpu_spinup(struct cpu_info *cpi)
+{
 	extern void cpu_hatch(void); /* in locore.s */
 	struct openprom_addr oa;
-	void *pc = (void *)cpu_hatch;
+	void *pc;
 	int n;
 	pc = (void *)cpu_hatch;
 	/* Setup CPU-specific MMU tables */
 	pmap_alloc_cpu(cpi);
 	cpi->flags &= ~CPUFLG_HATCHED;
 	/*
 	 * The physical address of the context table is passed to
 	 * the PROM in a "physical address descriptor".
 	 */
 	oa.oa_space = 0;
 	oa.oa_base = (uint32_t)cpi->ctx_tbl_pa;
 	oa.oa_size = cpi->mmu_ncontext * sizeof(cpi->ctx_tbl[0]); /*???*/
 	/*
 	 * Flush entire cache here, since the CPU may start with
 	 * caches off, hence no cache-coherency may be assumed.
 	 */
 	cpuinfo.cache_flush_all();
 	prom_cpustart(cpi->node, &oa, 0, pc);
 	/*
 	 * Wait for this CPU to spin up.
 	 */
 	for (n = 10000; n != 0; n--) {
 		cache_flush((void *) __UNVOLATILE(&cpi->flags),
 			    sizeof(cpi->flags));
 		if (cpi->flags & CPUFLG_HATCHED)
 			return;
 		delay(100);
+	}
 	printf("CPU did not spin up\n");
+}
 /*
  * Call a function on some CPUs.  `cpuset' can be set to CPUSET_ALL
  * to call every CPU, or `1 << cpi->ci_cpuid' for each CPU to call.
  */
 void
 xcall(xcall_func_t func, xcall_trap_t trap, int arg0, int arg1, int arg2,
       u_int cpuset)
+{
 	struct cpu_info *cpi;
-	int s, n, i, done, callself, mybit;
+	int n, i, done, callself, mybit;
 	volatile struct xpmsg_func *p;
 	int fasttrap;
 	int is_noop = func == (xcall_func_t)sparc_noop;
 	/* XXX - note p->retval is probably no longer useful */
 	mybit = (1 << cpuinfo.ci_cpuid);
 	callself = func && (cpuset & mybit) != 0;
 	cpuset &= ~mybit;
 	/*
 	 * If no cpus are configured yet, just call ourselves.
 	 */
 	if (cpus == NULL) {
 		p = &cpuinfo.msg.u.xpmsg_func;
 		if (callself)
 			p->retval = (*func)(arg0, arg1, arg2);
 		return;
 	/* Mask any CPUs that are not ready */
 	cpuset &= cpu_ready_mask;
 	/* prevent interrupts that grab the kernel lock */
-	s = splsched();
+	mutex_spin_enter(&xpmsg_mutex);
 #ifdef DEBUG
 	if (!cold) {
 		u_int pc, lvl = ((u_int)s & PSR_PIL) >> 8;
 		if (lvl > IPL_SCHED) {
 			__asm("mov %%i7, %0" : "=r" (pc) : );
 			printf_nolog("%d: xcall at lvl %u from 0x%x\n",
 				cpu_number(), lvl, pc);
 #endif
 	LOCK_XPMSG();
 	/*
 	 * Firstly, call each CPU.  We do this so that they might have
 	 * finished by the time we start looking.
 	 */
 	fasttrap = trap != NULL ? 1 : 0;
 	for (CPU_INFO_FOREACH(n, cpi)) {
 		/* Note: n == cpi->ci_cpuid */
 		if ((cpuset & (1 << n)) == 0)
 			continue;
 		cpi->msg.tag = XPMSG_FUNC;
 		cpi->msg.complete = 0;
 		p = &cpi->msg.u.xpmsg_func;
 		p->func = func;
 		p->trap = trap;
 		p->arg0 = arg0;
 		p->arg1 = arg1;
 		p->arg2 = arg2;
 		/* Fast cross calls use interrupt level 14 */
 		raise_ipi(cpi,13+fasttrap);/*xcall_cookie->pil*/
+	}
 	/*
 	 * Second, call ourselves.
 	 */
 	p = &cpuinfo.msg.u.xpmsg_func;
 	if (callself)
-		p->retval = (*func)(arg0, arg1, arg2);
+		(*func)(arg0, arg1, arg2);
 	/*
 	 * Lastly, start looping, waiting for all CPUs to register that they
 	 * have completed (bailing if it takes "too long", being loud about
 	 * this in the process).
 	 */
-	done = 0;
+	done = is_noop;
 	i = 100000;	/* time-out, not too long, but still an _AGE_ */
 	while (!done) {
 		if (--i < 0) {
 			printf_nolog("xcall(cpu%d,%p): couldn't ping cpus:",
 			    cpu_number(), func);
+		}
 		done = 1;
 		for (CPU_INFO_FOREACH(n, cpi)) {
 			if ((cpuset & (1 << n)) == 0)
 				continue;
 			if (cpi->msg.complete == 0) {
 				if (i < 0) {
 					printf_nolog(" cpu%d", cpi->ci_cpuid);
 				} else {
 					done = 0;
 					break;
+				}
+			}
+		}
+	}
 	if (i < 0)
 		printf_nolog("\n");
-	UNLOCK_XPMSG();
+	mutex_spin_exit(&xpmsg_mutex);
 	splx(s);
+}
 /*
  * Tell all CPUs other than the current one to enter the PROM idle loop.
  */
 void
 mp_pause_cpus(void)
+{
 	CPU_INFO_ITERATOR n;
 	struct cpu_info *cpi;
 	if (cpus == NULL)
 		return;
 	for (CPU_INFO_FOREACH(n, cpi)) {
 		if (cpuinfo.mid == cpi->mid ||
 		    (cpi->flags & CPUFLG_HATCHED) == 0)
 			continue;
 		/*
 		 * This PROM utility will put the OPENPROM_MBX_ABORT
 		 * message (0xfc) in the target CPU's mailbox and then
 		 * send it a level 15 soft interrupt.
 		 */
 		if (prom_cpuidle(cpi->node) != 0)
 			printf("cpu%d could not be paused\n", cpi->ci_cpuid);
+	}
+}
 /*
  * Resume all idling CPUs.
  */
 void
 mp_resume_cpus(void)
+{
 	CPU_INFO_ITERATOR n;
 	struct cpu_info *cpi;
 	if (cpus == NULL)
 		return;
 	for (CPU_INFO_FOREACH(n, cpi)) {
 		if (cpuinfo.mid == cpi->mid ||
 		    (cpi->flags & CPUFLG_HATCHED) == 0)
 			continue;
 		/*
 		 * This PROM utility makes the target CPU return
 		 * from its prom_cpuidle(0) call (see intr.c:nmi_soft()).
 		 */
 		if (prom_cpuresume(cpi->node) != 0)
 			printf("cpu%d could not be resumed\n", cpi->ci_cpuid);
+	}
+}
 /*
  * Tell all CPUs except the current one to hurry back into the prom
  */
 void
 mp_halt_cpus(void)
+{
 	CPU_INFO_ITERATOR n;
 	struct cpu_info *cpi;
 	if (cpus == NULL)
 		return;
 	for (CPU_INFO_FOREACH(n, cpi)) {
 		int r;
 		if (cpuinfo.mid == cpi->mid)
 			continue;
 		/*
 		 * This PROM utility will put the OPENPROM_MBX_STOP
 		 * message (0xfb) in the target CPU's mailbox and then
 		 * send it a level 15 soft interrupt.
 		 */
 		r = prom_cpustop(cpi->node);
 		printf("cpu%d %shalted\n", cpi->ci_cpuid,
 			r == 0 ? "" : "(boot CPU?) can not be ");
+	}
+}
 #if defined(DDB)
 void
 mp_pause_cpus_ddb(void)
+{
 	CPU_INFO_ITERATOR n;
 	struct cpu_info *cpi;
 	if (cpus == NULL)
 		return;
 	for (CPU_INFO_FOREACH(n, cpi)) {
 		if (cpi == NULL || cpi->mid == cpuinfo.mid ||
 		    (cpi->flags & CPUFLG_HATCHED) == 0)
 			continue;
 		cpi->msg_lev15.tag = XPMSG15_PAUSECPU;
 		raise_ipi(cpi,15);	/* high priority intr */
+	}
+}
 void
 mp_resume_cpus_ddb(void)
+{
 	CPU_INFO_ITERATOR n;
 	struct cpu_info *cpi;
 	if (cpus == NULL)
 		return;
 	for (CPU_INFO_FOREACH(n, cpi)) {
 		if (cpi == NULL || cpuinfo.mid == cpi->mid ||
 		    (cpi->flags & CPUFLG_PAUSED) == 0)
 			continue;
 		/* tell it to continue */
 		cpi->flags &= ~CPUFLG_PAUSED;
+	}
+}
 #endif /* DDB */
 #endif /* MULTIPROCESSOR */
 /*
  * fpu_init() must be run on associated CPU.
  */
 void
 fpu_init(struct cpu_info *sc)
+{
 	struct fpstate fpstate;
 	int fpuvers;
 	/*
 	 * Get the FSR and clear any exceptions.  If we do not unload
 	 * the queue here and it is left over from a previous crash, we
 	 * will panic in the first loadfpstate(), due to a sequence
 	 * error, so we need to dump the whole state anyway.
+	 *
 	 * If there is no FPU, trap.c will advance over all the stores,
 	 * so we initialize fs_fsr here.
 	 */
 	/* 7 is reserved for "none" */
 	fpstate.fs_fsr = 7 << FSR_VER_SHIFT;
 	savefpstate(&fpstate);
 	sc->fpuvers = fpuvers =
 		(fpstate.fs_fsr >> FSR_VER_SHIFT) & (FSR_VER >> FSR_VER_SHIFT);
 	if (fpuvers == 7) {
 		sc->fpu_name = "no";
 		return;
+	}
 	sc->fpupresent = 1;
 	sc->fpu_name = fsrtoname(sc->cpu_impl, sc->cpu_vers, fpuvers);
 	if (sc->fpu_name == NULL) {
 		sprintf(sc->fpu_namebuf, "version 0x%x", fpuvers);
 		sc->fpu_name = sc->fpu_namebuf;
+	}
+}
 void
 cache_print(struct cpu_softc *sc)
+{
 	struct cacheinfo *ci = &sc->sc_cpuinfo->cacheinfo;
 	if (sc->sc_cpuinfo->flags & CPUFLG_SUN4CACHEBUG)
 		printf("%s: cache chip bug; trap page uncached\n",
 		    sc->sc_dev.dv_xname);
 	printf("%s: ", sc->sc_dev.dv_xname);
 	if (ci->c_totalsize == 0) {
 		printf("no cache\n");
 		return;
+	}
 	if (ci->c_split) {
 		const char *sep = "";
 		printf("%s", (ci->c_physical ? "physical " : ""));
 		if (ci->ic_totalsize > 0) {
 			printf("%s%dK instruction (%d b/l)", sep,
 			    ci->ic_totalsize/1024, ci->ic_linesize);
 			sep = ", ";
+		}
 		if (ci->dc_totalsize > 0) {
 			printf("%s%dK data (%d b/l)", sep,
 			    ci->dc_totalsize/1024, ci->dc_linesize);
+		}
 	} else if (ci->c_physical) {
 		/* combined, physical */
 		printf("physical %dK combined cache (%d bytes/line)",
 		    ci->c_totalsize/1024, ci->c_linesize);
 	} else {
 		/* combined, virtual */
 		printf("%dK byte write-%s, %d bytes/line, %cw flush",
 		    ci->c_totalsize/1024,
 		    (ci->c_vactype == VAC_WRITETHROUGH) ? "through" : "back",
 		    ci->c_linesize,
 		    ci->c_hwflush ? 'h' : 's');
+	}
 	if (ci->ec_totalsize > 0) {
 		printf(", %dK external (%d b/l)",
 		    ci->ec_totalsize/1024, ci->ec_linesize);
+	}
 	printf(": ");
 	if (ci->c_enabled)
 		printf("cache enabled");
 	printf("\n");
+}
 /*------------*/
 void cpumatch_unknown(struct cpu_info *, struct module_info *, int);
 void cpumatch_sun4(struct cpu_info *, struct module_info *, int);
 void cpumatch_sun4c(struct cpu_info *, struct module_info *, int);
 void cpumatch_ms1(struct cpu_info *, struct module_info *, int);
 void cpumatch_viking(struct cpu_info *, struct module_info *, int);
 void cpumatch_hypersparc(struct cpu_info *, struct module_info *, int);
 void cpumatch_turbosparc(struct cpu_info *, struct module_info *, int);
 void getcacheinfo_sun4(struct cpu_info *, int node);
 void getcacheinfo_sun4c(struct cpu_info *, int node);
 void getcacheinfo_obp(struct cpu_info *, int node);
 void getcacheinfo_sun4d(struct cpu_info *, int node);
 void sun4_hotfix(struct cpu_info *);
 void viking_hotfix(struct cpu_info *);
 void turbosparc_hotfix(struct cpu_info *);
 void swift_hotfix(struct cpu_info *);
 void ms1_mmu_enable(void);
 void viking_mmu_enable(void);
 void swift_mmu_enable(void);
 void hypersparc_mmu_enable(void);
 void srmmu_get_syncflt(void);
 void ms1_get_syncflt(void);
 void viking_get_syncflt(void);
 void swift_get_syncflt(void);
 void turbosparc_get_syncflt(void);
 void hypersparc_get_syncflt(void);
 void cypress_get_syncflt(void);
 int srmmu_get_asyncflt(u_int *, u_int *);
 int hypersparc_get_asyncflt(u_int *, u_int *);
 int cypress_get_asyncflt(u_int *, u_int *);
 int no_asyncflt_regs(u_int *, u_int *);
 int hypersparc_getmid(void);
 /* cypress and hypersparc can share this function, see ctlreg.h */
 #define cypress_getmid	hypersparc_getmid
 int viking_getmid(void);
 int	(*moduleerr_handler)(void);
 int viking_module_error(void);
 struct module_info module_unknown = {
 	CPUTYP_UNKNOWN,
 	VAC_UNKNOWN,
 	cpumatch_unknown
 };
 void
 cpumatch_unknown(struct cpu_info *sc, struct module_info *mp, int node)
+{
 	panic("Unknown CPU type: "
 	      "cpu: impl %d, vers %d; mmu: impl %d, vers %d",
 		sc->cpu_impl, sc->cpu_vers,
 		sc->mmu_impl, sc->mmu_vers);
+}
 #if defined(SUN4)
 struct module_info module_sun4 = {
 	CPUTYP_UNKNOWN,
 	VAC_WRITETHROUGH,
 	cpumatch_sun4,
 	getcacheinfo_sun4,
 	sun4_hotfix,
 ,
 	sun4_cache_enable,
 ,
 ,			/* ncontext set in `match' function */
 ,			/* get_syncflt(); unused in sun4c */
 ,			/* get_asyncflt(); unused in sun4c */
 	sun4_cache_flush,
 	sun4_vcache_flush_page, NULL,
 	sun4_vcache_flush_segment, NULL,
 	sun4_vcache_flush_region, NULL,
 	sun4_vcache_flush_context, NULL,
 	NULL, NULL,
 	noop_pcache_flush_page,
 	noop_pure_vcache_flush,
 	noop_cache_flush_all,
 ,
 	pmap_zero_page4_4c,
 	pmap_copy_page4_4c
 };
 void
 getcacheinfo_sun4(struct cpu_info *sc, int node)
+{
 	struct cacheinfo *ci = &sc->cacheinfo;
 	switch (sc->cpu_type) {
 	case CPUTYP_4_100:
 		ci->c_vactype = VAC_NONE;
 		ci->c_totalsize = 0;
 		ci->c_hwflush = 0;
 		ci->c_linesize = 0;
 		ci->c_l2linesize = 0;
 		ci->c_split = 0;
 		ci->c_nlines = 0;
 		/* Override cache flush functions */
 		sc->cache_flush = noop_cache_flush;
 		sc->sp_vcache_flush_page = noop_vcache_flush_page;
 		sc->sp_vcache_flush_segment = noop_vcache_flush_segment;
 		sc->sp_vcache_flush_region = noop_vcache_flush_region;
 		sc->sp_vcache_flush_context = noop_vcache_flush_context;
 		break;
 	case CPUTYP_4_200:
 		ci->c_vactype = VAC_WRITEBACK;
 		ci->c_totalsize = 128*1024;
 		ci->c_hwflush = 0;
 		ci->c_linesize = 16;
 		ci->c_l2linesize = 4;
 		ci->c_split = 0;
 		ci->c_nlines = ci->c_totalsize >> ci->c_l2linesize;
 		break;
 	case CPUTYP_4_300:
 		ci->c_vactype = VAC_WRITEBACK;
 		ci->c_totalsize = 128*1024;
 		ci->c_hwflush = 0;
 		ci->c_linesize = 16;
 		ci->c_l2linesize = 4;
 		ci->c_split = 0;
 		ci->c_nlines = ci->c_totalsize >> ci->c_l2linesize;
 		sc->flags |= CPUFLG_SUN4CACHEBUG;
 		break;
 	case CPUTYP_4_400:
 		ci->c_vactype = VAC_WRITEBACK;
 		ci->c_totalsize = 128 * 1024;
 		ci->c_hwflush = 0;
 		ci->c_linesize = 32;
 		ci->c_l2linesize = 5;
 		ci->c_split = 0;
 		ci->c_nlines = ci->c_totalsize >> ci->c_l2linesize;
 		break;
+	}
+}
 void
 cpumatch_sun4(struct cpu_info *sc, struct module_info *mp, int node)
+{
 	struct idprom *idp = prom_getidprom();
 	switch (idp->idp_machtype) {
 	case ID_SUN4_100:
 		sc->cpu_type = CPUTYP_4_100;
 		sc->classlvl = 100;
 		sc->mmu_ncontext = 8;
 		sc->mmu_nsegment = 256;
 /*XXX*/		sc->hz = 14280000;
 		break;
 	case ID_SUN4_200:
 		sc->cpu_type = CPUTYP_4_200;
 		sc->classlvl = 200;
 		sc->mmu_nsegment = 512;
 		sc->mmu_ncontext = 16;
 /*XXX*/		sc->hz = 16670000;
 		break;
 	case ID_SUN4_300:
 		sc->cpu_type = CPUTYP_4_300;
 		sc->classlvl = 300;
 		sc->mmu_nsegment = 256;
 		sc->mmu_ncontext = 16;
 /*XXX*/		sc->hz = 25000000;
 		break;
 	case ID_SUN4_400:
 		sc->cpu_type = CPUTYP_4_400;
 		sc->classlvl = 400;
 		sc->mmu_nsegment = 1024;
 		sc->mmu_ncontext = 64;
 		sc->mmu_nregion = 256;
 /*XXX*/		sc->hz = 33000000;
 		sc->sun4_mmu3l = 1;
 		break;
+	}
+}
 #endif /* SUN4 */
 #if defined(SUN4C)
 struct module_info module_sun4c = {
 	CPUTYP_UNKNOWN,
 	VAC_WRITETHROUGH,
 	cpumatch_sun4c,
 	getcacheinfo_sun4c,
 	sun4_hotfix,
 ,
 	sun4_cache_enable,
 ,
 ,			/* ncontext set in `match' function */
 ,			/* get_syncflt(); unused in sun4c */
 ,			/* get_asyncflt(); unused in sun4c */
 	sun4_cache_flush,
 	sun4_vcache_flush_page, NULL,
 	sun4_vcache_flush_segment, NULL,
 	sun4_vcache_flush_region, NULL,
 	sun4_vcache_flush_context, NULL,
 	NULL, NULL,
 	noop_pcache_flush_page,
 	noop_pure_vcache_flush,
 	noop_cache_flush_all,
 ,
 	pmap_zero_page4_4c,
 	pmap_copy_page4_4c
 };
 void
 cpumatch_sun4c(struct cpu_info *sc, struct module_info *mp, int node)
+{
 	int	rnode;
 	rnode = findroot();
 	sc->mmu_npmeg = sc->mmu_nsegment =
 		prom_getpropint(rnode, "mmu-npmg", 128);
 	sc->mmu_ncontext = prom_getpropint(rnode, "mmu-nctx", 8);
 	/* Get clock frequency */
 	sc->hz = prom_getpropint(rnode, "clock-frequency", 0);
+}
 void
 getcacheinfo_sun4c(struct cpu_info *sc, int node)
+{
 	struct cacheinfo *ci = &sc->cacheinfo;
 	int i, l;
 	if (node == 0)
 		/* Bootstrapping */
 		return;
 	/* Sun4c's have only virtually-addressed caches */
 	ci->c_physical = 0;
 	ci->c_totalsize = prom_getpropint(node, "vac-size", 65536);
 	/*
 	 * Note: vac-hwflush is spelled with an underscore
 	 * on the 4/75s.
 	 */
 	ci->c_hwflush =
 		prom_getpropint(node, "vac_hwflush", 0) |
 		prom_getpropint(node, "vac-hwflush", 0);
 	ci->c_linesize = l = prom_getpropint(node, "vac-linesize", 16);
 	for (i = 0; (1 << i) < l; i++)
 		/* void */;
 	if ((1 << i) != l)
 		panic("bad cache line size %d", l);
 	ci->c_l2linesize = i;
 	ci->c_associativity = 1;
 	ci->c_nlines = ci->c_totalsize >> i;
 	ci->c_vactype = VAC_WRITETHROUGH;
 	/*
 	 * Machines with "buserr-type" 1 have a bug in the cache
 	 * chip that affects traps.  (I wish I knew more about this
 	 * mysterious buserr-type variable....)
 	 */
 	if (prom_getpropint(node, "buserr-type", 0) == 1)
 		sc->flags |= CPUFLG_SUN4CACHEBUG;
+}
 #endif /* SUN4C */
 void
 sun4_hotfix(struct cpu_info *sc)
+{
 	if ((sc->flags & CPUFLG_SUN4CACHEBUG) != 0)
 		kvm_uncache((char *)trapbase, 1);
 	/* Use the hardware-assisted page flush routine, if present */
 	if (sc->cacheinfo.c_hwflush)
 		sc->vcache_flush_page = sun4_vcache_flush_page_hw;
+}
 #if defined(SUN4M)
 void
 getcacheinfo_obp(struct cpu_info *sc, int node)
+{
 	struct cacheinfo *ci = &sc->cacheinfo;
 	int i, l;
 	if (node == 0)
 		/* Bootstrapping */
 		return;
 	/*
 	 * Determine the Sun4m cache organization.
 	 */
 	ci->c_physical = node_has_property(node, "cache-physical?");
 	if (prom_getpropint(node, "ncaches", 1) == 2)
 		ci->c_split = 1;
 	else
 		ci->c_split = 0;
 	/* hwflush is used only by sun4/4c code */
 	ci->c_hwflush = 0;
 	if (node_has_property(node, "icache-nlines") &&
 	    node_has_property(node, "dcache-nlines") &&
 	    ci->c_split) {
 		/* Harvard architecture: get I and D cache sizes */
 		ci->ic_nlines = prom_getpropint(node, "icache-nlines", 0);
 		ci->ic_linesize = l =
 			prom_getpropint(node, "icache-line-size", 0);
 		for (i = 0; (1 << i) < l && l; i++)
 			/* void */;
 		if ((1 << i) != l && l)
 			panic("bad icache line size %d", l);
 		ci->ic_l2linesize = i;
 		ci->ic_associativity =
 			prom_getpropint(node, "icache-associativity", 1);
 		ci->ic_totalsize = l * ci->ic_nlines * ci->ic_associativity;
 		ci->dc_nlines = prom_getpropint(node, "dcache-nlines", 0);
 		ci->dc_linesize = l =
 			prom_getpropint(node, "dcache-line-size",0);
 		for (i = 0; (1 << i) < l && l; i++)
 			/* void */;
 		if ((1 << i) != l && l)
 			panic("bad dcache line size %d", l);
 		ci->dc_l2linesize = i;
 		ci->dc_associativity =
 			prom_getpropint(node, "dcache-associativity", 1);
 		ci->dc_totalsize = l * ci->dc_nlines * ci->dc_associativity;
 		ci->c_l2linesize = min(ci->ic_l2linesize, ci->dc_l2linesize);
 		ci->c_linesize = min(ci->ic_linesize, ci->dc_linesize);
 		ci->c_totalsize = max(ci->ic_totalsize, ci->dc_totalsize);
 		ci->c_nlines = ci->c_totalsize >> ci->c_l2linesize;
 	} else {
 		/* unified I/D cache */
 		ci->c_nlines = prom_getpropint(node, "cache-nlines", 128);
 		ci->c_linesize = l =
 			prom_getpropint(node, "cache-line-size", 0);
 		for (i = 0; (1 << i) < l && l; i++)
 			/* void */;
 		if ((1 << i) != l && l)
 			panic("bad cache line size %d", l);
 		ci->c_l2linesize = i;
 		ci->c_associativity =
 			prom_getpropint(node, "cache-associativity", 1);
 		ci->dc_associativity = ci->ic_associativity =
 			ci->c_associativity;
 		ci->c_totalsize = l * ci->c_nlines * ci->c_associativity;
+	}
 	if (node_has_property(node, "ecache-nlines")) {
 		/* we have a L2 "e"xternal cache */
 		ci->ec_nlines = prom_getpropint(node, "ecache-nlines", 32768);
 		ci->ec_linesize = l = prom_getpropint(node, "ecache-line-size", 0);
 		for (i = 0; (1 << i) < l && l; i++)
 			/* void */;
 		if ((1 << i) != l && l)
 			panic("bad ecache line size %d", l);
 		ci->ec_l2linesize = i;
 		ci->ec_associativity =
 			prom_getpropint(node, "ecache-associativity", 1);
 		ci->ec_totalsize = l * ci->ec_nlines * ci->ec_associativity;
+	}
 	if (ci->c_totalsize == 0)
 		printf("warning: couldn't identify cache\n");
+}
 /*
  * We use the max. number of contexts on the micro and
  * hyper SPARCs. The SuperSPARC would let us use up to 65536
  * contexts (by powers of 2), but we keep it at 4096 since
  * the table must be aligned to #context*4. With 4K contexts,
  * we waste at most 16K of memory. Note that the context
  * table is *always* page-aligned, so there can always be
  * 1024 contexts without sacrificing memory space (given
  * that the chip supports 1024 contexts).
+ *
  * Currently known limits: MS1=64, MS2=256, HS=4096, SS=65536
  * 	some old SS's=4096
  */
 /* TI Microsparc I */
 struct module_info module_ms1 = {
 	CPUTYP_MS1,
 	VAC_NONE,
 	cpumatch_ms1,
 	getcacheinfo_obp,
 ,
 	ms1_mmu_enable,
 	ms1_cache_enable,
 ,
 ,
 	ms1_get_syncflt,
 	no_asyncflt_regs,
 	ms1_cache_flush,
 	noop_vcache_flush_page, NULL,
 	noop_vcache_flush_segment, NULL,
 	noop_vcache_flush_region, NULL,
 	noop_vcache_flush_context, NULL,
 	noop_vcache_flush_range, NULL,
 	noop_pcache_flush_page,
 	noop_pure_vcache_flush,
 	ms1_cache_flush_all,
 	memerr4m,
 	pmap_zero_page4m,
 	pmap_copy_page4m
 };
 void
 cpumatch_ms1(struct cpu_info *sc, struct module_info *mp, int node)
+{
 	/*
 	 * Turn off page zeroing in the idle loop; an unidentified
 	 * bug causes (very sporadic) user process corruption.
 	 */
 	vm_page_zero_enable = 0;
+}
 void
 ms1_mmu_enable(void)
+{
+}
 /* TI Microsparc II */
 struct module_info module_ms2 = {		/* UNTESTED */
 	CPUTYP_MS2,
 	VAC_WRITETHROUGH,
 ,
 	getcacheinfo_obp,
 ,
 ,
 	swift_cache_enable,
 ,
 ,
 	srmmu_get_syncflt,
 	srmmu_get_asyncflt,
 	srmmu_cache_flush,
 	srmmu_vcache_flush_page, NULL,
 	srmmu_vcache_flush_segment, NULL,
 	srmmu_vcache_flush_region, NULL,
 	srmmu_vcache_flush_context, NULL,
 	srmmu_vcache_flush_range, NULL,
 	noop_pcache_flush_page,
 	noop_pure_vcache_flush,
 	srmmu_cache_flush_all,
 	memerr4m,
 	pmap_zero_page4m,
 	pmap_copy_page4m
 };
 struct module_info module_swift = {
 	CPUTYP_MS2,
 	VAC_WRITETHROUGH,
 ,
 	getcacheinfo_obp,
 	swift_hotfix,
 ,
 	swift_cache_enable,
 ,
 ,
 	swift_get_syncflt,
 	no_asyncflt_regs,
 	srmmu_cache_flush,
 	srmmu_vcache_flush_page, NULL,
 	srmmu_vcache_flush_segment, NULL,
 	srmmu_vcache_flush_region, NULL,
 	srmmu_vcache_flush_context, NULL,
 	srmmu_vcache_flush_range, NULL,
 	noop_pcache_flush_page,
 	noop_pure_vcache_flush,
 	srmmu_cache_flush_all,
 	memerr4m,
 	pmap_zero_page4m,
 	pmap_copy_page4m
 };
 void
 swift_hotfix(struct cpu_info *sc)
+{
 	int pcr = lda(SRMMU_PCR, ASI_SRMMU);
 	/* Turn off branch prediction */
 	pcr &= ~SWIFT_PCR_BF;
 	sta(SRMMU_PCR, ASI_SRMMU, pcr);
+}
 void
 swift_mmu_enable(void)
+{
+}
 /* ROSS Hypersparc */
 struct module_info module_hypersparc = {
 	CPUTYP_UNKNOWN,
 	VAC_WRITEBACK,
 	cpumatch_hypersparc,
 	getcacheinfo_obp,
 ,
 	hypersparc_mmu_enable,
 	hypersparc_cache_enable,
 	hypersparc_getmid,
 ,
 	hypersparc_get_syncflt,
 	hypersparc_get_asyncflt,
 	srmmu_cache_flush,
 	srmmu_vcache_flush_page, ft_srmmu_vcache_flush_page,
 	srmmu_vcache_flush_segment, ft_srmmu_vcache_flush_segment,
 	srmmu_vcache_flush_region, ft_srmmu_vcache_flush_region,
 	srmmu_vcache_flush_context, ft_srmmu_vcache_flush_context,
 	srmmu_vcache_flush_range, ft_srmmu_vcache_flush_range,
 	noop_pcache_flush_page,
 	hypersparc_pure_vcache_flush,
 	hypersparc_cache_flush_all,
 	hypersparc_memerr,
 	pmap_zero_page4m,
 	pmap_copy_page4m
 };
 void
 cpumatch_hypersparc(struct cpu_info *sc, struct module_info *mp, int node)
+{
 	sc->cpu_type = CPUTYP_HS_MBUS;/*XXX*/
 	if (node == 0) {
 		/* Flush I-cache */
 		sta(0, ASI_HICACHECLR, 0);
 		/* Disable `unimplemented flush' traps during boot-up */
 		wrasr(rdasr(HYPERSPARC_ASRNUM_ICCR) | HYPERSPARC_ICCR_FTD,
 			HYPERSPARC_ASRNUM_ICCR);
+	}
+}
 void
 hypersparc_mmu_enable(void)
+{
 #if 0
 	int pcr;
 	pcr = lda(SRMMU_PCR, ASI_SRMMU);
 	pcr |= HYPERSPARC_PCR_C;
 	pcr &= ~HYPERSPARC_PCR_CE;
 	sta(SRMMU_PCR, ASI_SRMMU, pcr);
 #endif
+}
 int
 hypersparc_getmid(void)
+{
 	u_int pcr = lda(SRMMU_PCR, ASI_SRMMU);
 	return ((pcr & HYPERSPARC_PCR_MID) >> 15);
+}
 /* Cypress 605 */
 struct module_info module_cypress = {
 	CPUTYP_CYPRESS,
 	VAC_WRITEBACK,
 ,
 	getcacheinfo_obp,
 ,
 ,
 	cypress_cache_enable,
 	cypress_getmid,
 ,
 	cypress_get_syncflt,
 	cypress_get_asyncflt,
 	srmmu_cache_flush,
 	srmmu_vcache_flush_page, ft_srmmu_vcache_flush_page,
 	srmmu_vcache_flush_segment, ft_srmmu_vcache_flush_segment,
 	srmmu_vcache_flush_region, ft_srmmu_vcache_flush_region,
 	srmmu_vcache_flush_context, ft_srmmu_vcache_flush_context,
 	srmmu_vcache_flush_range, ft_srmmu_vcache_flush_range,
 	noop_pcache_flush_page,
 	noop_pure_vcache_flush,
 	cypress_cache_flush_all,
 	memerr4m,
 	pmap_zero_page4m,
 	pmap_copy_page4m
 };
 /* Fujitsu Turbosparc */
 struct module_info module_turbosparc = {
 	CPUTYP_MS2,
 	VAC_WRITEBACK,
 	cpumatch_turbosparc,
 	getcacheinfo_obp,
 	turbosparc_hotfix,
 ,
 	turbosparc_cache_enable,
 ,
 ,
 	turbosparc_get_syncflt,
 	no_asyncflt_regs,
 	srmmu_cache_flush,
 	srmmu_vcache_flush_page, NULL,
 	srmmu_vcache_flush_segment, NULL,
 	srmmu_vcache_flush_region, NULL,
 	srmmu_vcache_flush_context, NULL,
 	srmmu_vcache_flush_range, NULL,
 	noop_pcache_flush_page,
 	noop_pure_vcache_flush,
 	srmmu_cache_flush_all,
 	memerr4m,
 	pmap_zero_page4m,
 	pmap_copy_page4m
 };
 void
 cpumatch_turbosparc(struct cpu_info *sc, struct module_info *mp, int node)
+{
 	int i;
 	if (node == 0 || sc->master == 0)
 		return;
 	i = getpsr();
 	if (sc->cpu_vers == IU_VERS(i))
 		return;
 	/*
 	 * A cloaked Turbosparc: clear any items in cpuinfo that
 	 * might have been set to uS2 versions during bootstrap.
 	 */
 	sc->cpu_name = 0;
 	sc->mmu_ncontext = 0;
 	sc->cpu_type = 0;
 	sc->cacheinfo.c_vactype = 0;
 	sc->hotfix = 0;
 	sc->mmu_enable = 0;
 	sc->cache_enable = 0;
 	sc->get_syncflt = 0;
 	sc->cache_flush = 0;
 	sc->sp_vcache_flush_page = 0;
 	sc->sp_vcache_flush_segment = 0;
 	sc->sp_vcache_flush_region = 0;
 	sc->sp_vcache_flush_context = 0;
 	sc->pcache_flush_page = 0;
+}
 void
 turbosparc_hotfix(struct cpu_info *sc)
+{
 	int pcf;
 	pcf = lda(SRMMU_PCFG, ASI_SRMMU);
 	if (pcf & TURBOSPARC_PCFG_US2) {
 		/* Turn off uS2 emulation bit */
 		pcf &= ~TURBOSPARC_PCFG_US2;
 		sta(SRMMU_PCFG, ASI_SRMMU, pcf);
+	}
+}
 #endif /* SUN4M */
 #if defined(SUN4M)
 struct module_info module_viking = {
 	CPUTYP_UNKNOWN,		/* set in cpumatch() */
 	VAC_NONE,
 	cpumatch_viking,
 	getcacheinfo_obp,
 	viking_hotfix,
 	viking_mmu_enable,
 	viking_cache_enable,
 	viking_getmid,
 ,
 	viking_get_syncflt,
 	no_asyncflt_regs,
 	/* supersparcs use cached DVMA, no need to flush */
 	noop_cache_flush,
 	noop_vcache_flush_page, NULL,
 	noop_vcache_flush_segment, NULL,
 	noop_vcache_flush_region, NULL,
 	noop_vcache_flush_context, NULL,
 	noop_vcache_flush_range, NULL,
 	viking_pcache_flush_page,
 	noop_pure_vcache_flush,
 	noop_cache_flush_all,
 	viking_memerr,
 	pmap_zero_page4m,
 	pmap_copy_page4m
 };
 #endif /* SUN4M */
 #if defined(SUN4M) || defined(SUN4D)
 void
 cpumatch_viking(struct cpu_info *sc, struct module_info *mp, int node)
+{
 	if (node == 0)
 		viking_hotfix(sc);
+}
 void
 viking_hotfix(struct cpu_info *sc)
+{
 static	int mxcc = -1;
 	int pcr = lda(SRMMU_PCR, ASI_SRMMU);
 	/* Test if we're directly on the MBus */
 	if ((pcr & VIKING_PCR_MB) == 0) {
 		sc->mxcc = 1;
 		sc->flags |= CPUFLG_CACHE_MANDATORY;
 		sc->zero_page = pmap_zero_page_viking_mxcc;
 		sc->copy_page = pmap_copy_page_viking_mxcc;
 		moduleerr_handler = viking_module_error;
 		/*
 		 * Ok to cache PTEs; set the flag here, so we don't
 		 * uncache in pmap_bootstrap().
 		 */
 		if ((pcr & VIKING_PCR_TC) == 0)
 			printf("[viking: PCR_TC is off]");
 		else
 			sc->flags |= CPUFLG_CACHEPAGETABLES;
 	} else {
 #ifdef MULTIPROCESSOR
 		if ((sparc_ncpus > 1) && (sc->cacheinfo.ec_totalsize == 0))
 			sc->cache_flush = srmmu_cache_flush;
 #endif
+	}
 	/* Check all modules have the same MXCC configuration */
 	if (mxcc != -1 && sc->mxcc != mxcc)
 		panic("MXCC module mismatch");
 	mxcc = sc->mxcc;
 	/* XXX! */
 	if (sc->mxcc)
 		sc->cpu_type = CPUTYP_SS1_MBUS_MXCC;
 	else
 		sc->cpu_type = CPUTYP_SS1_MBUS_NOMXCC;
+}
 void
 viking_mmu_enable(void)
+{
 	int pcr;
 	pcr = lda(SRMMU_PCR, ASI_SRMMU);
 	if (cpuinfo.mxcc) {
 		if ((pcr & VIKING_PCR_TC) == 0) {
 			printf("[viking: turn on PCR_TC]");
+		}
 		pcr |= VIKING_PCR_TC;
 		cpuinfo.flags |= CPUFLG_CACHEPAGETABLES;
 	} else
 		pcr &= ~VIKING_PCR_TC;
 	sta(SRMMU_PCR, ASI_SRMMU, pcr);
+}
 int
 viking_getmid(void)
+{
 	if (cpuinfo.mxcc) {
 		u_int v = ldda(MXCC_MBUSPORT, ASI_CONTROL) & 0xffffffff;
 		return ((v >> 24) & 0xf);
+	}
 	return (0);
+}
 int
 viking_module_error(void)
+{
 	uint64_t v;
 	int n = 0, fatal = 0;
 	struct cpu_info *cpi;
 	/* Report on MXCC error registers in each module */
 	for (CPU_INFO_FOREACH(n, cpi)) {
 		if (cpi->ci_mxccregs == 0) {
 			printf("\tMXCC registers not mapped\n");
 			continue;
+		}
 		printf("module%d:\n", cpi->ci_cpuid);
 		v = *((uint64_t *)(cpi->ci_mxccregs + 0xe00));
 		printf("\tmxcc error 0x%llx\n", v);
 		v = *((uint64_t *)(cpi->ci_mxccregs + 0xb00));
 		printf("\tmxcc status 0x%llx\n", v);
 		v = *((uint64_t *)(cpi->ci_mxccregs + 0xc00));
 		printf("\tmxcc reset 0x%llx", v);
 		if (v & MXCC_MRST_WD)
 			printf(" (WATCHDOG RESET)"), fatal = 1;
 		if (v & MXCC_MRST_SI)
 			printf(" (SOFTWARE RESET)"), fatal = 1;
 		printf("\n");
+	}
 	return (fatal);
+}
 #endif /* SUN4M || SUN4D */
 #if defined(SUN4D)
 void
 getcacheinfo_sun4d(struct cpu_info *sc, int node)
+{
 	struct cacheinfo *ci = &sc->cacheinfo;
 	int i, l;
 	if (node == 0)
 		/* Bootstrapping */
 		return;
 	/*
 	 * The Sun4d always has TI TMS390Z55 Viking CPUs; we hard-code
 	 * much of the cache information here.
 	 */
 	ci->c_physical = 1;
 	ci->c_split = 1;
 	/* hwflush is used only by sun4/4c code */
 	ci->c_hwflush = 0;
 	ci->ic_nlines = 0x00000040;
 	ci->ic_linesize = 0x00000040;
 	ci->ic_l2linesize = 6;
 	ci->ic_associativity = 0x00000005;
 	ci->ic_totalsize = ci->ic_linesize * ci->ic_nlines *
 	    ci->ic_associativity;
 	ci->dc_nlines = 0x00000080;
 	ci->dc_linesize = 0x00000020;
 	ci->dc_l2linesize = 5;
 	ci->dc_associativity = 0x00000004;
 	ci->dc_totalsize = ci->dc_linesize * ci->dc_nlines *
 	    ci->dc_associativity;
 	ci->c_l2linesize = min(ci->ic_l2linesize, ci->dc_l2linesize);
 	ci->c_linesize = min(ci->ic_linesize, ci->dc_linesize);
 	ci->c_totalsize = max(ci->ic_totalsize, ci->dc_totalsize);
 	ci->c_nlines = ci->c_totalsize >> ci->c_l2linesize;
 	if (node_has_property(node, "ecache-nlines")) {
 		/* we have a L2 "e"xternal cache */
 		ci->ec_nlines = prom_getpropint(node, "ecache-nlines", 32768);
 		ci->ec_linesize = l = prom_getpropint(node, "ecache-line-size", 0);
 		for (i = 0; (1 << i) < l && l; i++)
 			/* void */;
 		if ((1 << i) != l && l)
 			panic("bad ecache line size %d", l);
 		ci->ec_l2linesize = i;
 		ci->ec_associativity =
 			prom_getpropint(node, "ecache-associativity", 1);
 		ci->ec_totalsize = l * ci->ec_nlines * ci->ec_associativity;
+	}
+}
 struct module_info module_viking_sun4d = {
 	CPUTYP_UNKNOWN,		/* set in cpumatch() */
 	VAC_NONE,
 	cpumatch_viking,
 	getcacheinfo_sun4d,
 	viking_hotfix,
 	viking_mmu_enable,
 	viking_cache_enable,
 	viking_getmid,
 ,
 	viking_get_syncflt,
 	no_asyncflt_regs,
 	/* supersparcs use cached DVMA, no need to flush */
 	noop_cache_flush,
 	noop_vcache_flush_page, NULL,
 	noop_vcache_flush_segment, NULL,
 	noop_vcache_flush_region, NULL,
 	noop_vcache_flush_context, NULL,
 	noop_vcache_flush_range, NULL,
 	viking_pcache_flush_page,
 	noop_pure_vcache_flush,
 	noop_cache_flush_all,
 	viking_memerr,
 	pmap_zero_page4m,
 	pmap_copy_page4m
 };
 #endif /* SUN4D */
 #define	ANY	-1	/* match any version */
 struct cpu_conf {
 	int	arch;
 	int	cpu_impl;
 	int	cpu_vers;
 	int	mmu_impl;
 	int	mmu_vers;
 	const char	*name;
 	struct	module_info *minfo;

 @@ -1,796 +1,796 @@
-/*	$NetBSD: intr.c,v 1.103 2009/05/18 00:25:15 mrg Exp $ */
+/*	$NetBSD: intr.c,v 1.104 2009/05/27 02:19:50 mrg Exp $ */
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
  * must display the following acknowledgement:
  *	This product includes software developed by the University of
  *	California, Lawrence Berkeley Laboratory.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)intr.c	8.3 (Berkeley) 11/11/93
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.103 2009/05/18 00:25:15 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.104 2009/05/27 02:19:50 mrg Exp $");
 #include "opt_multiprocessor.h"
 #include "opt_sparc_arch.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/malloc.h>
 #include <sys/cpu.h>
 #include <sys/intr.h>
 #include <sys/simplelock.h>
 #include <uvm/uvm_extern.h>
 #include <dev/cons.h>
 #include <machine/ctlreg.h>
 #include <machine/instr.h>
 #include <machine/trap.h>
 #include <machine/promlib.h>
 #include <sparc/sparc/asm.h>
 #include <sparc/sparc/cpuvar.h>
 #if defined(MULTIPROCESSOR) && defined(DDB)
 #include <machine/db_machdep.h>
 #endif
 #if defined(MULTIPROCESSOR)
 void *xcall_cookie;
 /* Stats */
 struct evcnt lev13_evcnt = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,0,"xcall","std");
 struct evcnt lev14_evcnt = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,0,"xcall","fast");
 EVCNT_ATTACH_STATIC(lev13_evcnt);
 EVCNT_ATTACH_STATIC(lev14_evcnt);
 #endif
 void	strayintr(struct clockframe *);
 #ifdef DIAGNOSTIC
 void	bogusintr(struct clockframe *);
 #endif
 /*
  * Stray interrupt handler.  Clear it if possible.
  * If not, and if we get 10 interrupts in 10 seconds, panic.
  * XXXSMP: We are holding the kernel lock at entry & exit.
  */
 void
 strayintr(struct clockframe *fp)
+{
 	static int straytime, nstray;
 	char bits[64];
 	int timesince;
 	snprintb(bits, sizeof(bits), PSR_BITS, fp->psr);
 	printf("stray interrupt cpu%d ipl 0x%x pc=0x%x npc=0x%x psr=%s\n",
 	    cpu_number(), fp->ipl, fp->pc, fp->npc, bits);
 	timesince = time_uptime - straytime;
 	if (timesince <= 10) {
 		if (++nstray > 10)
 			panic("crazy interrupts");
 	} else {
 		straytime = time_uptime;
 		nstray = 1;
+	}
+}
 #ifdef DIAGNOSTIC
 /*
  * Bogus interrupt for which neither hard nor soft interrupt bit in
  * the IPR was set.
  */
 void
 bogusintr(struct clockframe *fp)
+{
 	char bits[64];
 	snprintb(bits, sizeof(bits), PSR_BITS, fp->psr);
 	printf("cpu%d: bogus interrupt ipl 0x%x pc=0x%x npc=0x%x psr=%s\n",
 	    cpu_number(), fp->ipl, fp->pc, fp->npc, bits);
+}
 #endif /* DIAGNOSTIC */
 /*
  * Get module ID of interrupt target.
  */
 u_int
 getitr(void)
+{
 #if defined(MULTIPROCESSOR)
 	u_int v;
 	if (!CPU_ISSUN4M || sparc_ncpus <= 1)
 		return (0);
 	v = *((u_int *)ICR_ITR);
 	return (v + 8);
 #else
 	return (0);
 #endif
+}
 /*
  * Set interrupt target.
  * Return previous value.
  */
 u_int
 setitr(u_int mid)
+{
 #if defined(MULTIPROCESSOR)
 	u_int v;
 	if (!CPU_ISSUN4M || sparc_ncpus <= 1)
 		return (0);
 	v = *((u_int *)ICR_ITR);
 	*((u_int *)ICR_ITR) = CPU_MID2CPUNO(mid);
 	return (v + 8);
 #else
 	return (0);
 #endif
+}
 #if (defined(SUN4M) && !defined(MSIIEP)) || defined(SUN4D)
 void	nmi_hard(void);
 void	nmi_soft(struct trapframe *);
 int	(*memerr_handler)(void);
 int	(*sbuserr_handler)(void);
 int	(*vmeerr_handler)(void);
 int	(*moduleerr_handler)(void);
 #if defined(MULTIPROCESSOR)
 volatile int nmi_hard_wait = 0;
 struct simplelock nmihard_lock = SIMPLELOCK_INITIALIZER;
 int drop_into_rom_on_fatal = 1;
 #endif
 void
 nmi_hard(void)
+{
 	/*
 	 * A level 15 hard interrupt.
 	 */
 	int fatal = 0;
 	uint32_t si;
 	char bits[64];
 	u_int afsr, afva;
 	afsr = afva = 0;
 	if ((*cpuinfo.get_asyncflt)(&afsr, &afva) == 0) {
 		snprintb(bits, sizeof(bits), AFSR_BITS, afsr);
 		printf("Async registers (mid %d): afsr=%s; afva=0x%x%x\n",
 			cpuinfo.mid, bits,
 			(afsr & AFSR_AFA) >> AFSR_AFA_RSHIFT, afva);
+	}
 #if defined(MULTIPROCESSOR)
 	/*
 	 * Increase nmi_hard_wait.  If we aren't the master, loop while this
 	 * variable is non-zero.  If we are the master, loop while this
 	 * variable is less than the number of cpus.
 	 */
 	simple_lock(&nmihard_lock);
 	nmi_hard_wait++;
 	simple_unlock(&nmihard_lock);
 	if (cpuinfo.master == 0) {
 		while (nmi_hard_wait)
+			;
 		return;
 	} else {
 		int n = 100000;
 		while (nmi_hard_wait < sparc_ncpus) {
 			DELAY(1);
 			if (n-- > 0)
 				continue;
 			printf("nmi_hard: SMP botch.");
 			break;
+		}
+	}
 #endif
 	/*
 	 * Examine pending system interrupts.
 	 */
 	si = *((uint32_t *)ICR_SI_PEND);
 	snprintb(bits, sizeof(bits), SINTR_BITS, si);
 	printf("cpu%d: NMI: system interrupts: %s\n", cpu_number(), bits);
 	if ((si & SINTR_M) != 0) {
 		/* ECC memory error */
 		if (memerr_handler != NULL)
 			fatal |= (*memerr_handler)();
+	}
 	if ((si & SINTR_I) != 0) {
 		/* MBus/SBus async error */
 		if (sbuserr_handler != NULL)
 			fatal |= (*sbuserr_handler)();
+	}
 	if ((si & SINTR_V) != 0) {
 		/* VME async error */
 		if (vmeerr_handler != NULL)
 			fatal |= (*vmeerr_handler)();
+	}
 	if ((si & SINTR_ME) != 0) {
 		/* Module async error */
 		if (moduleerr_handler != NULL)
 			fatal |= (*moduleerr_handler)();
+	}
 #if defined(MULTIPROCESSOR)
 	/*
 	 * Tell everyone else we've finished dealing with the hard NMI.
 	 */
 	simple_lock(&nmihard_lock);
 	nmi_hard_wait = 0;
 	simple_unlock(&nmihard_lock);
 	if (fatal && drop_into_rom_on_fatal) {
 		prom_abort();
 		return;
+	}
 #endif
 	if (fatal)
 		panic("nmi");
+}
 /*
  * Non-maskable soft interrupt level 15 handler
  */
 void
 nmi_soft(struct trapframe *tf)
+{
 	if (cpuinfo.mailbox) {
 		/* Check PROM messages */
 		uint8_t msg = *(uint8_t *)cpuinfo.mailbox;
 		switch (msg) {
 		case OPENPROM_MBX_STOP:
 		case OPENPROM_MBX_WD:
 			/* In case there's an xcall in progress (unlikely) */
 			spl0();
 			cpuinfo.flags &= ~CPUFLG_READY;
 #ifdef MULTIPROCESSOR
 			cpu_ready_mask &= ~(1 << cpu_number());
 #endif
 			prom_cpustop(0);
 			break;
 		case OPENPROM_MBX_ABORT:
 		case OPENPROM_MBX_BPT:
 			prom_cpuidle(0);
 			/*
 			 * We emerge here after someone does a
 			 * prom_resumecpu(ournode).
 			 */
 			return;
 		default:
 			break;
+		}
+	}
 #if defined(MULTIPROCESSOR)
 	switch (cpuinfo.msg_lev15.tag) {
 	case XPMSG15_PAUSECPU:
 		/* XXX - assumes DDB is the only user of mp_pause_cpu() */
 		cpuinfo.flags |= CPUFLG_PAUSED;
 #if defined(DDB)
 		/* trap(T_DBPAUSE) */
 		__asm("ta 0x8b");
 #else
 		while (cpuinfo.flags & CPUFLG_PAUSED)
 			/* spin */;
 #endif /* DDB */
+	}
 	cpuinfo.msg_lev15.tag = 0;
 #endif /* MULTIPROCESSOR */
+}
 #if defined(MULTIPROCESSOR)
 /*
  * Respond to an xcall() request from another CPU.
  */
 static void
 xcallintr(void *v)
+{
 	/* Tally */
 	lev13_evcnt.ev_count++;
 	/* notyet - cpuinfo.msg.received = 1; */
 	switch (cpuinfo.msg.tag) {
 	case XPMSG_FUNC:
+	    {
 		volatile struct xpmsg_func *p = &cpuinfo.msg.u.xpmsg_func;
 		if (p->func)
-			p->retval = (*p->func)(p->arg0, p->arg1, p->arg2);
+			(*p->func)(p->arg0, p->arg1, p->arg2);
 		break;
+	    }
+	}
 	cpuinfo.msg.tag = 0;
 	cpuinfo.msg.complete = 1;
+}
 #endif /* MULTIPROCESSOR */
 #endif /* SUN4M || SUN4D */
 #ifdef MSIIEP
 /*
  * It's easier to make this separate so that not to further obscure
  * SUN4M case with more ifdefs.  There's no common functionality
  * anyway.
  */
 #include <sparc/sparc/msiiepreg.h>
 void	nmi_hard_msiiep(void);
 void	nmi_soft_msiiep(void);
 void
 nmi_hard_msiiep(void)
+{
 	uint32_t si;
 	char bits[128];
 	int fatal = 0;
 	si = mspcic_read_4(pcic_sys_ipr);
 	snprintb(bits, sizeof(bits), MSIIEP_SYS_IPR_BITS, si);
 	printf("NMI: system interrupts: %s\n", bits);
 	if (si & MSIIEP_SYS_IPR_MEM_FAULT) {
 		uint32_t afsr, afar, mfsr, mfar;
 		afar = *(volatile uint32_t *)MSIIEP_AFAR;
 		afsr = *(volatile uint32_t *)MSIIEP_AFSR;
 		mfar = *(volatile uint32_t *)MSIIEP_MFAR;
 		mfsr = *(volatile uint32_t *)MSIIEP_MFSR;
 		if (afsr & MSIIEP_AFSR_ERR) {
 			snprintb(bits, sizeof(bits), MSIIEP_AFSR_BITS, afsr);
 			printf("async fault: afsr=%s; afar=%08x\n", bits, afsr);
+		}
 		if (mfsr & MSIIEP_MFSR_ERR) {
 			snprintb(bits, sizeof(bits), MSIIEP_MFSR_BITS, mfsr);
 			printf("mem fault: mfsr=%s; mfar=%08x\n", bits, mfsr);
+		}
 		fatal = 0;
+	}
 	if (si & MSIIEP_SYS_IPR_SERR) {	/* XXX */
 		printf("serr#\n");
 		fatal = 0;
+	}
 	if (si & MSIIEP_SYS_IPR_DMA_ERR) {
 		printf("dma: %08x\n",
 		       mspcic_read_stream_4(pcic_iotlb_err_addr));
 		fatal = 0;
+	}
 	if (si & MSIIEP_SYS_IPR_PIO_ERR) {
 		printf("pio: addr=%08x, cmd=%x\n",
 		       mspcic_read_stream_4(pcic_pio_err_addr),
 		       mspcic_read_stream_1(pcic_pio_err_cmd));
 		fatal = 0;
+	}
 	if (fatal)
 		panic("nmi");
 	/* Clear the NMI if it was PCIC related */
 	mspcic_write_1(pcic_sys_ipr_clr, MSIIEP_SYS_IPR_CLR_ALL);
+}
 void
 nmi_soft_msiiep(void)
+{
 	panic("soft nmi");
+}
 #endif /* MSIIEP */
 /*
  * Level 15 interrupts are special, and not vectored here.
  * Only `prewired' interrupts appear here; boot-time configured devices
  * are attached via intr_establish() below.
  */
 struct intrhand *intrhand[15] = {
 	NULL,			/*  0 = error */
 	NULL,			/*  1 = software level 1 + Sbus */
 	NULL,	 		/*  2 = Sbus level 2 (4m: Sbus L1) */
 	NULL,			/*  3 = SCSI + DMA + Sbus level 3 (4m: L2,lpt)*/
 	NULL,			/*  4 = software level 4 (tty softint) (scsi) */
 	NULL,			/*  5 = Ethernet + Sbus level 4 (4m: Sbus L3) */
 	NULL,			/*  6 = software level 6 (not used) (4m: enet)*/
 	NULL,			/*  7 = video + Sbus level 5 */
 	NULL,			/*  8 = Sbus level 6 */
 	NULL,			/*  9 = Sbus level 7 */
 	NULL, 			/* 10 = counter 0 = clock */
 	NULL,			/* 11 = floppy */
 	NULL,			/* 12 = zs hardware interrupt */
 	NULL,			/* 13 = audio chip */
 	NULL, 			/* 14 = counter 1 = profiling timer */
 };
 /*
  * Soft interrupts use a separate set of handler chains.
  * This is necessary since soft interrupt handlers do not return a value
  * and therefore cannot be mixed with hardware interrupt handlers on a
  * shared handler chain.
  */
 struct intrhand *sintrhand[15] = { NULL };
 static void
 ih_insert(struct intrhand **head, struct intrhand *ih)
+{
 	struct intrhand **p, *q;
 	/*
 	 * This is O(N^2) for long chains, but chains are never long
 	 * and we do want to preserve order.
 	 */
 	for (p = head; (q = *p) != NULL; p = &q->ih_next)
 		continue;
 	*p = ih;
 	ih->ih_next = NULL;
+}
 static void
 ih_remove(struct intrhand **head, struct intrhand *ih)
+{
 	struct intrhand **p, *q;
 	for (p = head; (q = *p) != ih; p = &q->ih_next)
 		continue;
 	if (q == NULL)
 		panic("intr_remove: intrhand %p fun %p arg %p",
 			ih, ih->ih_fun, ih->ih_arg);
 	*p = q->ih_next;
 	q->ih_next = NULL;
+}
 static int fastvec;		/* marks fast vectors (see below) */
 extern int sparc_interrupt4m[];
 extern int sparc_interrupt44c[];
 #ifdef DIAGNOSTIC
 static void
 check_tv(int level)
+{
 	struct trapvec *tv;
 	int displ;
 	/* double check for legal hardware interrupt */
 	tv = &trapbase[T_L1INT - 1 + level];
 	displ = (CPU_ISSUN4M || CPU_ISSUN4D)
 		? &sparc_interrupt4m[0] - &tv->tv_instr[1]
 		: &sparc_interrupt44c[0] - &tv->tv_instr[1];
 	/* has to be `mov level,%l3; ba _sparc_interrupt; rdpsr %l0' */
 	if (tv->tv_instr[0] != I_MOVi(I_L3, level) ||
 	    tv->tv_instr[1] != I_BA(0, displ) ||
 	    tv->tv_instr[2] != I_RDPSR(I_L0))
 		panic("intr_establish(%d)\n0x%x 0x%x 0x%x != 0x%x 0x%x 0x%x",
 		    level,
 		    tv->tv_instr[0], tv->tv_instr[1], tv->tv_instr[2],
 		    I_MOVi(I_L3, level), I_BA(0, displ), I_RDPSR(I_L0));
+}
 #endif
 /*
  * Wire a fast trap vector.  Only one such fast trap is legal for any
  * interrupt, and it must be a hardware interrupt.
  */
 static void
 inst_fasttrap(int level, void (*vec)(void))
+{
 	struct trapvec *tv;
 	u_long hi22, lo10;
 	int s;
 	if (CPU_ISSUN4 || CPU_ISSUN4C) {
 		/* Can't wire to softintr slots */
 		if (level == 1 || level == 4 || level == 6)
 			return;
+	}
 #ifdef DIAGNOSTIC
 	check_tv(level);
 #endif
 	tv = &trapbase[T_L1INT - 1 + level];
 	hi22 = ((u_long)vec) >> 10;
 	lo10 = ((u_long)vec) & 0x3ff;
 	s = splhigh();
 	/* kernel text is write protected -- let us in for a moment */
 	pmap_kprotect((vaddr_t)tv & -PAGE_SIZE, PAGE_SIZE,
 	    VM_PROT_READ|VM_PROT_WRITE);
 	cpuinfo.cache_flush_all();
 	tv->tv_instr[0] = I_SETHI(I_L3, hi22);	/* sethi %hi(vec),%l3 */
 	tv->tv_instr[1] = I_JMPLri(I_G0, I_L3, lo10);/* jmpl %l3+%lo(vec),%g0 */
 	tv->tv_instr[2] = I_RDPSR(I_L0);	/* mov %psr, %l0 */
 	pmap_kprotect((vaddr_t)tv & -PAGE_SIZE, PAGE_SIZE, VM_PROT_READ);
 	cpuinfo.cache_flush_all();
 	fastvec |= 1 << level;
 	splx(s);
+}
 /*
  * Uninstall a fast trap handler.
  */
 static void
 uninst_fasttrap(int level)
+{
 	struct trapvec *tv;
 	int displ;	/* suspenders, belt, and buttons too */
 	int s;
 	tv = &trapbase[T_L1INT - 1 + level];
 	s = splhigh();
 	displ = (CPU_ISSUN4M || CPU_ISSUN4D)
 		? &sparc_interrupt4m[0] - &tv->tv_instr[1]
 		: &sparc_interrupt44c[0] - &tv->tv_instr[1];
 	/* kernel text is write protected -- let us in for a moment */
 	pmap_kprotect((vaddr_t)tv & -PAGE_SIZE, PAGE_SIZE,
 	    VM_PROT_READ|VM_PROT_WRITE);
 	cpuinfo.cache_flush_all();
 	tv->tv_instr[0] = I_MOVi(I_L3, level);
 	tv->tv_instr[1] = I_BA(0, displ);
 	tv->tv_instr[2] = I_RDPSR(I_L0);
 	pmap_kprotect((vaddr_t)tv & -PAGE_SIZE, PAGE_SIZE, VM_PROT_READ);
 	cpuinfo.cache_flush_all();
 	fastvec &= ~(1 << level);
 	splx(s);
+}
 /*
  * Attach an interrupt handler to the vector chain for the given level.
  * This is not possible if it has been taken away as a fast vector.
  */
 void
 intr_establish(int level, int classipl,
 	       struct intrhand *ih, void (*vec)(void))
+{
 	int s = splhigh();
 #ifdef DIAGNOSTIC
 	if (CPU_ISSUN4C) {
 		/*
 		 * Check reserved softintr slots on SUN4C only.
 		 * No check for SUN4, as 4/300's have
 		 * esp0 at level 4 and le0 at level 6.
 		 */
 		if (level == 1 || level == 4 || level == 6)
 			panic("intr_establish: reserved softintr level");
+	}
 #endif
 	/*
 	 * If a `fast vector' is currently tied to this level, we must
 	 * first undo that.
 	 */
 	if (fastvec & (1 << level)) {
 		printf("intr_establish: untie fast vector at level %d\n",
 		    level);
 		uninst_fasttrap(level);
 	} else if (vec != NULL &&
 		   intrhand[level] == NULL && sintrhand[level] == NULL) {
 		inst_fasttrap(level, vec);
+	}
 	if (classipl == 0)
 		classipl = level;
 	/* A requested IPL cannot exceed its device class level */
 	if (classipl < level)
 		panic("intr_establish: class lvl (%d) < pil (%d)\n",
 			classipl, level);
 	/* pre-shift to PIL field in %psr */
 	ih->ih_classipl = (classipl << 8) & PSR_PIL;
 	ih_insert(&intrhand[level], ih);
 	splx(s);
+}
 void
 intr_disestablish(int level, struct intrhand *ih)
+{
 	ih_remove(&intrhand[level], ih);
+}
 /*
  * This is a softintr cookie.  NB that sic_pilreq MUST be the
  * first element in the struct, because the softintr_schedule()
  * macro in intr.h casts cookies to int * to get it.  On a
  * sun4m, sic_pilreq is an actual processor interrupt level that
  * is passed to raise(), and on a sun4 or sun4c sic_pilreq is a
  * bit to set in the interrupt enable register with ienab_bis().
  */
 struct softintr_cookie {
 	int sic_pilreq;		/* CPU-specific bits; MUST be first! */
 	int sic_pil;		/* Actual machine PIL that is used */
 	struct intrhand sic_hand;
 };
 /*
  * softintr_init(): initialise the MI softintr system.
  */
 void
 sparc_softintr_init(void)
+{
 #if defined(MULTIPROCESSOR) && (defined(SUN4M) || defined(SUN4D))
 	/* Establish a standard soft interrupt handler for cross calls */
 	xcall_cookie = sparc_softintr_establish(13, xcallintr, NULL);
 #endif
+}
 /*
  * softintr_establish(): MI interface.  establish a func(arg) as a
  * software interrupt.
  */
 void *
 sparc_softintr_establish(int level, void (*fun)(void *), void *arg)
+{
 	struct softintr_cookie *sic;
 	struct intrhand *ih;
 	int pilreq;
 	int pil;
 	/*
 	 * On a sun4m, the processor interrupt level is stored
 	 * in the softintr cookie to be passed to raise().
+	 *
 	 * On a sun4 or sun4c the appropriate bit to set
 	 * in the interrupt enable register is stored in
 	 * the softintr cookie to be passed to ienab_bis().
 	 */
 	pil = pilreq = level;
 	if (CPU_ISSUN4 || CPU_ISSUN4C) {
 		/* Select the most suitable of three available softint levels */
 		if (level >= 1 && level < 4) {
 			pil = 1;
 			pilreq = IE_L1;
 		} else if (level >= 4 && level < 6) {
 			pil = 4;
 			pilreq = IE_L4;
 		} else {
 			pil = 6;
 			pilreq = IE_L6;
+		}
+	}
 	sic = malloc(sizeof(*sic), M_DEVBUF, 0);
 	sic->sic_pil = pil;
 	sic->sic_pilreq = pilreq;
 	ih = &sic->sic_hand;
 	ih->ih_fun = (int (*)(void *))fun;
 	ih->ih_arg = arg;
 	/*
 	 * Always run the handler at the requested level, which might
 	 * be higher than the hardware can provide.
+	 *
 	 * pre-shift to PIL field in %psr
 	 */
 	ih->ih_classipl = (level << 8) & PSR_PIL;
 	if (fastvec & (1 << pil)) {
 		printf("softintr_establish: untie fast vector at level %d\n",
 		    pil);
 		uninst_fasttrap(level);
+	}
 	ih_insert(&sintrhand[pil], ih);
 	return (void *)sic;
+}
 /*
  * softintr_disestablish(): MI interface.  disestablish the specified
  * software interrupt.
  */
 void
 sparc_softintr_disestablish(void *cookie)
+{
 	struct softintr_cookie *sic = cookie;
 	ih_remove(&sintrhand[sic->sic_pil], &sic->sic_hand);
 	free(cookie, M_DEVBUF);
+}
 #if 0
 void
 sparc_softintr_schedule(void *cookie)
+{
 	struct softintr_cookie *sic = cookie;
 	if (CPU_ISSUN4M || CPU_ISSUN4D) {
 #if defined(SUN4M) || defined(SUN4D)
 		extern void raise(int,int);
 		raise(0, sic->sic_pilreq);
 #endif
 	} else {
 #if defined(SUN4) || defined(SUN4C)
 		ienab_bis(sic->sic_pilreq);
 #endif
+	}
+}
 #endif
 #ifdef MULTIPROCESSOR
 /*
  * Called by interrupt stubs, etc., to lock/unlock the kernel.
  */
 void
 intr_lock_kernel(void)
+{
 	KERNEL_LOCK(1, NULL);
+}
 void
 intr_unlock_kernel(void)
+{
 	KERNEL_UNLOCK_ONE(NULL);
+}
 #endif
 bool
 cpu_intr_p(void)
+{
 	return curcpu()->ci_idepth != 0;
+}

 @@ -1,1058 +1,1058 @@
-/*	$NetBSD: pmap.c,v 1.328 2009/05/18 02:28:35 mrg Exp $ */
+/*	$NetBSD: pmap.c,v 1.329 2009/05/27 02:19:50 mrg Exp $ */
 /*
  * Copyright (c) 1996
  * 	The President and Fellows of Harvard College. All rights reserved.
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
  * must display the following acknowledgement:
  *	This product includes software developed by Harvard University.
  *	This product includes software developed by the University of
  *	California, Lawrence Berkeley Laboratory.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
+ *
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Aaron Brown and
  *	Harvard University.
  *      This product includes software developed by the University of
  *      California, Berkeley and its contributors.
  * 4. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)pmap.c	8.4 (Berkeley) 2/5/94
+ *
  */
 /*
  * SPARC physical map management code.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.328 2009/05/18 02:28:35 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.329 2009/05/27 02:19:50 mrg Exp $");
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
 #include "opt_sparc_arch.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/proc.h>
 #include <sys/queue.h>
 #include <sys/pool.h>
 #include <sys/exec.h>
 #include <sys/core.h>
 #include <sys/kcore.h>
 #include <sys/kernel.h>
 #include <sys/atomic.h>
 #include <uvm/uvm.h>
 #include <machine/autoconf.h>
 #include <machine/bsd_openprom.h>
 #include <machine/oldmon.h>
 #include <machine/cpu.h>
 #include <machine/ctlreg.h>
 #include <machine/kcore.h>
 #include <sparc/sparc/asm.h>
 #include <sparc/sparc/cache.h>
 #include <sparc/sparc/vaddrs.h>
 #include <sparc/sparc/cpuvar.h>
 /*
  * The SPARCstation offers us the following challenges:
+ *
  *   1. A virtual address cache.  This is, strictly speaking, not
  *	part of the architecture, but the code below assumes one.
  *	This is a write-through cache on the 4c and a write-back cache
  *	on others.
+ *
  *   2. (4/4c only) An MMU that acts like a cache.  There is not enough
  *	space in the MMU to map everything all the time.  Instead, we need
  *	to load MMU with the `working set' of translations for each
  *	process. The sun4m does not act like a cache; tables are maintained
  *	in physical memory.
+ *
  *   3.	Segmented virtual and physical spaces.  The upper 12 bits of
  *	a virtual address (the virtual segment) index a segment table,
  *	giving a physical segment.  The physical segment selects a
  *	`Page Map Entry Group' (PMEG) and the virtual page number---the
  *	next 5 or 6 bits of the virtual address---select the particular
  *	`Page Map Entry' for the page.  We call the latter a PTE and
  *	call each Page Map Entry Group a pmeg (for want of a better name).
  *	Note that the sun4m has an unsegmented 36-bit physical space.
+ *
  *	Since there are no valid bits in the segment table, the only way
  *	to have an invalid segment is to make one full pmeg of invalid PTEs.
  *	We use the last one (since the ROM does as well) (sun4/4c only)
+ *
  *   4. Discontiguous physical pages.  The Mach VM expects physical pages
  *	to be in one sequential lump.
+ *
  *   5. The MMU is always on: it is not possible to disable it.  This is
  *	mainly a startup hassle.
  */
 struct pmap_stats {
 	int	ps_unlink_pvfirst;	/* # of pv_unlinks on head */
 	int	ps_unlink_pvsearch;	/* # of pv_unlink searches */
 	int	ps_changeprots;		/* # of calls to changeprot */
 	int	ps_enter_firstpv;	/* pv heads entered */
 	int	ps_enter_secondpv;	/* pv nonheads entered */
 	int	ps_useless_changewire;	/* useless wiring changes */
 	int	ps_npg_prot_all;	/* # of active pages protected */
 	int	ps_npg_prot_actual;	/* # pages actually affected */
 	int	ps_npmeg_free;		/* # of free pmegs */
 	int	ps_npmeg_locked;	/* # of pmegs on locked list */
 	int	ps_npmeg_lru;		/* # of pmegs on lru list */
 } pmap_stats;
 #if defined(SUN4) || defined(SUN4C)
 struct evcnt mmu_stolenpmegs_evcnt =
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR,0,"mmu","stln pmgs");
 EVCNT_ATTACH_STATIC(mmu_stolenpmegs_evcnt);
 struct evcnt mmu_pagein_evcnt =
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR,0,"mmu","pagein");
 EVCNT_ATTACH_STATIC(mmu_pagein_evcnt);
 #endif /* SUN4 || SUN4C */
 #ifdef DEBUG
 #define	PDB_CREATE	0x0001
 #define	PDB_DESTROY	0x0002
 #define	PDB_REMOVE	0x0004
 #define	PDB_CHANGEPROT	0x0008
 #define	PDB_ENTER	0x0010
 #define	PDB_FOLLOW	0x0020
 #define	PDB_MMU_ALLOC	0x0100
 #define	PDB_MMU_STEAL	0x0200
 #define	PDB_CTX_ALLOC	0x0400
 #define	PDB_CTX_STEAL	0x0800
 #define	PDB_MMUREG_ALLOC	0x1000
 #define	PDB_MMUREG_STEAL	0x2000
 #define	PDB_CACHESTUFF	0x4000
 #define	PDB_SWITCHMAP	0x8000
 #define	PDB_SANITYCHK	0x10000
 int	pmapdebug = 0;
 #endif
 /*
  * Bounds on managed physical addresses. Used by (MD) users
  * of uvm_pglistalloc() to provide search hints.
  */
 paddr_t	vm_first_phys = (paddr_t)-1;
 paddr_t	vm_last_phys = 0;
 psize_t vm_num_phys;
 #define	PMAP_LOCK()	KERNEL_LOCK(1, NULL)
 #define	PMAP_UNLOCK()	KERNEL_UNLOCK_ONE(NULL)
 /*
  * Flags in pvlist.pv_flags.  Note that PV_MOD must be 1 and PV_REF must be 2
  * since they must line up with the bits in the hardware PTEs (see pte.h).
  * SUN4M bits are at a slightly different location in the PTE.
+ *
  * Note: the REF, MOD and ANC flag bits occur only in the head of a pvlist.
  * The NC bit is meaningful in each individual pv entry and reflects the
  * requested non-cacheability at the time the entry was made through
  * pv_link() or when subsequently altered by kvm_uncache() (but the latter
  * does not happen in kernels as of the time of this writing (March 2001)).
  */
 #define PV_MOD		1	/* page modified */
 #define PV_REF		2	/* page referenced */
 #define PV_NC		4	/* page cannot be cached */
 #define PV_REF4M	1	/* page referenced (SRMMU) */
 #define PV_MOD4M	2	/* page modified (SRMMU) */
 #define PV_ANC		0x10	/* page has incongruent aliases */
 static struct pool pv_pool;
 /*
  * pvhead(pte): find a VM page given a PTE entry.
  */
 #if defined(SUN4) || defined(SUN4C)
 static struct vm_page *
 pvhead4_4c(u_int pte)
+{
 	paddr_t pa = (pte & PG_PFNUM) << PGSHIFT;
 	return (PHYS_TO_VM_PAGE(pa));
+}
 #endif
 #if defined(SUN4M) || defined(SUN4D)
 static struct vm_page *
 pvhead4m(u_int pte)
+{
 	paddr_t pa = (pte & SRMMU_PPNMASK) << SRMMU_PPNPASHIFT;
 	return (PHYS_TO_VM_PAGE(pa));
+}
 #endif
 /*
  * Each virtual segment within each pmap is either valid or invalid.
  * It is valid if pm_npte[VA_VSEG(va)] is not 0.  This does not mean
  * it is in the MMU, however; that is true iff pm_segmap[VA_VSEG(va)]
  * does not point to the invalid PMEG.
+ *
  * In the older SPARC architectures (sun4/sun4c), page tables are cached in
  * the MMU. The following discussion applies to these architectures:
+ *
  * If a virtual segment is valid and loaded, the correct PTEs appear
  * in the MMU only.  If it is valid and unloaded, the correct PTEs appear
  * in the pm_pte[VA_VSEG(va)] only.  However, some effort is made to keep
  * the software copies consistent enough with the MMU so that libkvm can
  * do user address translations.  In particular, pv_changepte() and
  * pmap_enu() maintain consistency, while less critical changes are
  * not maintained.  pm_pte[VA_VSEG(va)] always points to space for those
  * PTEs.
+ *
  * Each PMEG in the MMU is either free or contains PTEs corresponding to
  * some pmap and virtual segment.  If it contains some PTEs, it also contains
  * reference and modify bits that belong in the pv_table.  If we need
  * to steal a PMEG from some process (if we need one and none are free)
  * we must copy the ref and mod bits, and update pm_segmap in the other
  * pmap to show that its virtual segment is no longer in the MMU.
+ *
  * There are 128 PMEGs in a small Sun-4, of which only a few dozen are
  * tied down permanently, leaving `about' 100 to be spread among
  * running processes.  These are managed as an LRU cache.  Before
  * calling the VM paging code for a user page fault, the fault handler
  * calls mmu_load(pmap, va) to try to get a set of PTEs put into the
  * MMU.  mmu_load will check the validity of the segment and tell whether
  * it did something.
+ *
  * Since I hate the name PMEG I call this data structure an `mmu entry'.
  * Each mmuentry is on exactly one of three `usage' lists: free, LRU,
  * or locked.  The locked list is only used for kernel mappings that need
  * to be wired down.
+ *
+ *
  * In the sun4m architecture using the SPARC Reference MMU (SRMMU), three
  * levels of page tables are maintained in physical memory. We use the same
  * structures as with the 3-level old-style MMU (pm_regmap, pm_segmap,
  * rg_segmap, sg_pte, etc) to maintain kernel-edible page tables; we also
  * build a parallel set of physical tables that can be used by the MMU.
  * (XXX: This seems redundant, but is it necessary for the unified kernel?)
+ *
  * If a virtual segment is valid, its entries will be in both parallel lists.
  * If it is not valid, then its entry in the kernel tables will be zero, and
  * its entry in the MMU tables will either be nonexistent or zero as well.
+ *
  * The Reference MMU generally uses a Translation Look-aside Buffer (TLB)
  * to cache the result of recently executed page table walks. When
  * manipulating page tables, we need to ensure consistency of the
  * in-memory and TLB copies of the page table entries. This is handled
  * by flushing (and invalidating) a TLB entry when appropriate before
  * altering an in-memory page table entry.
  */
 struct mmuentry {
 	CIRCLEQ_ENTRY(mmuentry)	me_list;	/* usage list link */
 	TAILQ_ENTRY(mmuentry)	me_pmchain;	/* pmap owner link */
 	struct	pmap *me_pmap;		/* pmap, if in use */
 	u_short	me_vreg;		/* associated virtual region/segment */
 	u_short	me_vseg;		/* associated virtual region/segment */
 	u_short	me_cookie;		/* hardware SMEG/PMEG number */
 #ifdef DIAGNOSTIC
 	int *me_statp;/*XXX*/
 #endif
 };
 struct mmuentry *mmusegments;	/* allocated in pmap_bootstrap */
 struct mmuentry *mmuregions;	/* allocated in pmap_bootstrap */
 CIRCLEQ_HEAD(mmuq, mmuentry);
 struct mmuq segm_freelist, segm_lru, segm_locked;
 struct mmuq region_freelist, region_lru, region_locked;
 /*
  * We use a circular queue, since that allows us to remove an element
  * from a list without knowing the list header.
  */
 #define CIRCLEQ_REMOVE_NOH(elm, field) do {				\
 	(elm)->field.cqe_next->field.cqe_prev = (elm)->field.cqe_prev;	\
 	(elm)->field.cqe_prev->field.cqe_next = (elm)->field.cqe_next;	\
 } while (/*CONSTCOND*/0)
 #define MMUQ_INIT(head)			CIRCLEQ_INIT(head)
 #define MMUQ_REMOVE(elm,field)		CIRCLEQ_REMOVE_NOH(elm,field)
 #define MMUQ_INSERT_TAIL(head,elm,field)CIRCLEQ_INSERT_TAIL(head,elm,field)
 #define MMUQ_EMPTY(head)		CIRCLEQ_EMPTY(head)
 #define MMUQ_FIRST(head)		CIRCLEQ_FIRST(head)
 int	seginval;		/* [4/4c] the invalid segment number */
 int	reginval;		/* [4/3mmu] the invalid region number */
 static kmutex_t demap_lock;
 /*
  * (sun4/4c)
  * A context is simply a small number that dictates which set of 4096
  * segment map entries the MMU uses.  The Sun 4c has eight (SS1,IPC) or
  * sixteen (SS2,IPX) such sets. These are alloted in an `almost MRU' fashion.
  * (sun4m)
  * A context is simply a small number that indexes the context table, the
  * root-level page table mapping 4G areas. Each entry in this table points
  * to a 1st-level region table. A SPARC reference MMU will usually use 16
  * such contexts, but some offer as many as 64k contexts; the theoretical
  * maximum is 2^32 - 1, but this would create overlarge context tables.
+ *
  * Each context is either free or attached to a pmap.
+ *
  * Since the virtual address cache is tagged by context, when we steal
  * a context we have to flush (that part of) the cache.
  */
 union ctxinfo {
 	union	ctxinfo *c_nextfree;	/* free list (if free) */
 	struct	pmap *c_pmap;		/* pmap (if busy) */
 };
 static kmutex_t	ctx_lock;		/* lock for below */
 union	ctxinfo *ctxinfo;		/* allocated at in pmap_bootstrap */
 union	ctxinfo *ctx_freelist;		/* context free list */
 int	ctx_kick;			/* allocation rover when none free */
 int	ctx_kickdir;			/* ctx_kick roves both directions */
 int	ncontext;			/* sizeof ctx_freelist */
 void	ctx_alloc(struct pmap *);
 void	ctx_free(struct pmap *);
 void *	vmmap;			/* one reserved MI vpage for /dev/mem */
 /*void *	vdumppages;	-* 32KB worth of reserved dump pages */
 smeg_t		tregion;	/* [4/3mmu] Region for temporary mappings */
 static struct pmap	kernel_pmap_store;	/* the kernel's pmap */
 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; /* pmap_kernel() */
 struct regmap	kernel_regmap_store[NKREG];	/* the kernel's regmap */
 struct segmap	kernel_segmap_store[NKREG*NSEGRG];/* the kernel's segmaps */
 #if defined(SUN4M) || defined(SUN4D)
 u_int 	*kernel_regtable_store;		/* 1k of storage to map the kernel */
 u_int	*kernel_segtable_store;		/* 2k of storage to map the kernel */
 u_int	*kernel_pagtable_store;		/* 128k of storage to map the kernel */
 /*
  * Memory pools and back-end supplier for SRMMU page tables.
  * Share a pool between the level 2 and level 3 page tables,
  * since these are equal in size.
  */
 static struct pool L1_pool;
 static struct pool L23_pool;
 static void *pgt_page_alloc(struct pool *, int);
 static void  pgt_page_free(struct pool *, void *);
 static struct pool_allocator pgt_page_allocator = {
 	pgt_page_alloc, pgt_page_free, 0,
 };
 #endif /* SUN4M || SUN4D */
 #if defined(SUN4) || defined(SUN4C)
 /*
  * Memory pool for user and kernel PTE tables.
  */
 static struct pool pte_pool;
 #endif
 struct	memarr *pmemarr;	/* physical memory regions */
 int	npmemarr;		/* number of entries in pmemarr */
 static paddr_t	avail_start;	/* first available physical page, other
 				   than the `etext gap' defined below */
 static vaddr_t	etext_gap_start;/* start of gap between text & data */
 static vaddr_t	etext_gap_end;	/* end of gap between text & data */
 static vaddr_t	virtual_avail;	/* first free kernel virtual address */
 static vaddr_t	virtual_end;	/* last free kernel virtual address */
 static void pmap_page_upload(void);
 int mmu_has_hole;
 vaddr_t prom_vstart;	/* For /dev/kmem */
 vaddr_t prom_vend;
 /*
  * Memory pool for pmap structures.
  */
 static struct pool_cache pmap_cache;
 static int	pmap_pmap_pool_ctor(void *, void *, int);
 static void	pmap_pmap_pool_dtor(void *, void *);
 static struct pool segmap_pool;
 #if defined(SUN4)
 /*
  * [sun4]: segfixmask: on some systems (4/110) "getsegmap()" returns a
  * partly invalid value. getsegmap returns a 16 bit value on the sun4,
  * but only the first 8 or so bits are valid (the rest are *supposed* to
  * be zero. On the 4/110 the bits that are supposed to be zero are
  * all one instead. e.g. KERNBASE is usually mapped by pmeg number zero.
  * On a 4/300 getsegmap(KERNBASE) == 0x0000, but
  * on a 4/100 getsegmap(KERNBASE) == 0xff00
+ *
  * This confuses mmu_reservemon() and causes it to not reserve the PROM's
  * pmegs. Then the PROM's pmegs get used during autoconfig and everything
  * falls apart!  (not very fun to debug, BTW.)
+ *
  * solution: mask the invalid bits in the getsetmap macro.
  */
 static u_int segfixmask = 0xffffffff; /* all bits valid to start */
 #else
 #define segfixmask 0xffffffff	/* It's in getsegmap's scope */
 #endif
 /*
  * pseudo-functions for mnemonic value
  */
 #define	getsegmap(va)		(CPU_ISSUN4C \
 					? lduba(va, ASI_SEGMAP) \
 					: (lduha(va, ASI_SEGMAP) & segfixmask))
 #define	setsegmap(va, pmeg)	(CPU_ISSUN4C \
 					? stba(va, ASI_SEGMAP, pmeg) \
 					: stha(va, ASI_SEGMAP, pmeg))
 /* 3-level sun4 MMU only: */
 #define	getregmap(va)		((unsigned)lduha((va)+2, ASI_REGMAP) >> 8)
 #define	setregmap(va, smeg)	stha((va)+2, ASI_REGMAP, (smeg << 8))
 #if defined(SUN4M) || defined(SUN4D)
 #if 0
 #if VM_PROT_READ != 1 || VM_PROT_WRITE != 2 || VM_PROT_EXECUTE != 4
 #error fix protection code translation table
 #endif
 #endif
 /*
  * Translation table for kernel vs. PTE protection bits.
  */
 const u_int protection_codes[2][8] = {
 	/* kernel */
+	{
 	PPROT_N_RX,	/* VM_PROT_NONE    | VM_PROT_NONE  | VM_PROT_NONE */
 	PPROT_N_RX,	/* VM_PROT_NONE    | VM_PROT_NONE  | VM_PROT_READ */
 	PPROT_N_RWX,	/* VM_PROT_NONE    | VM_PROT_WRITE | VM_PROT_NONE */
 	PPROT_N_RWX,	/* VM_PROT_NONE    | VM_PROT_WRITE | VM_PROT_READ */
 	PPROT_N_RX,	/* VM_PROT_EXECUTE | VM_PROT_NONE  | VM_PROT_NONE */
 	PPROT_N_RX,	/* VM_PROT_EXECUTE | VM_PROT_NONE  | VM_PROT_READ */
 	PPROT_N_RWX,	/* VM_PROT_EXECUTE | VM_PROT_WRITE | VM_PROT_NONE */
 	PPROT_N_RWX,	/* VM_PROT_EXECUTE | VM_PROT_WRITE | VM_PROT_READ */
 	},
 	/* user */
+	{
 	PPROT_N_RX,	/* VM_PROT_NONE    | VM_PROT_NONE  | VM_PROT_NONE */
 	PPROT_R_R,	/* VM_PROT_NONE    | VM_PROT_NONE  | VM_PROT_READ */
 	PPROT_RW_RW,	/* VM_PROT_NONE    | VM_PROT_WRITE | VM_PROT_NONE */
 	PPROT_RW_RW,	/* VM_PROT_NONE    | VM_PROT_WRITE | VM_PROT_READ */
 	PPROT_X_X,	/* VM_PROT_EXECUTE | VM_PROT_NONE  | VM_PROT_NONE */
 	PPROT_RX_RX,	/* VM_PROT_EXECUTE | VM_PROT_NONE  | VM_PROT_READ */
 	PPROT_RWX_RWX,	/* VM_PROT_EXECUTE | VM_PROT_WRITE | VM_PROT_NONE */
 	PPROT_RWX_RWX,	/* VM_PROT_EXECUTE | VM_PROT_WRITE | VM_PROT_READ */
+	}
 };
 #define pte_kprot4m(prot) (protection_codes[0][(prot)])
 #define pte_uprot4m(prot) (protection_codes[1][(prot)])
 #define pte_prot4m(pm, prot) \
 	(protection_codes[(pm) == pmap_kernel() ? 0 : 1][(prot)])
 void		setpte4m(vaddr_t va, int pte);
 void		setpgt4m(int *ptep, int pte);
 void		setpgt4m_va(vaddr_t, int *, int, int, int, u_int);
 int		updatepte4m(vaddr_t, int *, int, int, int, u_int);
 #endif /* SUN4M || SUN4D */
 #if defined(MULTIPROCESSOR)
 #define PMAP_SET_CPUSET(pmap, cpi)	\
 	(pmap->pm_cpuset |= (1 << (cpi)->ci_cpuid))
 #define PMAP_CLR_CPUSET(pmap, cpi)	\
 	(pmap->pm_cpuset &= ~(1 << (cpi)->ci_cpuid))
 #define PMAP_CPUSET(pmap)		(pmap->pm_cpuset)
 #else
 #define PMAP_SET_CPUSET(pmap, cpi)	/* nothing */
 #define PMAP_CLR_CPUSET(pmap, cpi)	/* nothing */
 #define PMAP_CPUSET(pmap)		1	/* XXX: 1 or 0? */
 #endif /* MULTIPROCESSOR */
 /* Function pointer messiness for supporting multiple sparc architectures
  * within a single kernel: notice that there are two versions of many of the
  * functions within this file/module, one for the sun4/sun4c and the other
  * for the sun4m. For performance reasons (since things like pte bits don't
  * map nicely between the two architectures), there are separate functions
  * rather than unified functions which test the cputyp variable. If only
  * one architecture is being used, then the non-suffixed function calls
  * are macro-translated into the appropriate xxx4_4c or xxx4m call. If
  * multiple architectures are defined, the calls translate to (*xxx_p),
  * i.e. they indirect through function pointers initialized as appropriate
  * to the run-time architecture in pmap_bootstrap. See also pmap.h.
  */
 #if defined(SUN4M) || defined(SUN4D)
 static void mmu_setup4m_L1(int, struct pmap *);
 static void mmu_setup4m_L2(int, struct regmap *);
 static void  mmu_setup4m_L3(int, struct segmap *);
 /*static*/ void	mmu_reservemon4m(struct pmap *);
 /*static*/ void pmap_changeprot4m(pmap_t, vaddr_t, vm_prot_t, int);
 /*static*/ void pmap_rmk4m(struct pmap *, vaddr_t, vaddr_t, int, int);
 /*static*/ void pmap_rmu4m(struct pmap *, vaddr_t, vaddr_t, int, int);
 /*static*/ int  pmap_enk4m(struct pmap *, vaddr_t, vm_prot_t,
 				int, struct vm_page *, int);
 /*static*/ int  pmap_enu4m(struct pmap *, vaddr_t, vm_prot_t,
 				int, struct vm_page *, int);
 /*static*/ void pv_changepte4m(struct vm_page *, int, int);
 /*static*/ int  pv_syncflags4m(struct vm_page *);
 /*static*/ int  pv_link4m(struct vm_page *, struct pmap *, vaddr_t, u_int *);
 /*static*/ void pv_unlink4m(struct vm_page *, struct pmap *, vaddr_t);
 #endif
 #if defined(SUN4) || defined(SUN4C)
 /*static*/ void	mmu_reservemon4_4c(int *, int *);
 /*static*/ void pmap_changeprot4_4c(pmap_t, vaddr_t, vm_prot_t, int);
 /*static*/ void pmap_rmk4_4c(struct pmap *, vaddr_t, vaddr_t, int, int);
 /*static*/ void pmap_rmu4_4c(struct pmap *, vaddr_t, vaddr_t, int, int);
 /*static*/ int  pmap_enk4_4c(struct pmap *, vaddr_t, vm_prot_t,
 				  int, struct vm_page *, int);
 /*static*/ int  pmap_enu4_4c(struct pmap *, vaddr_t, vm_prot_t,
 				  int, struct vm_page *, int);
 /*static*/ void pv_changepte4_4c(struct vm_page *, int, int);
 /*static*/ int  pv_syncflags4_4c(struct vm_page *);
 /*static*/ int  pv_link4_4c(struct vm_page *, struct pmap *, vaddr_t, u_int *);
 /*static*/ void pv_unlink4_4c(struct vm_page *, struct pmap *, vaddr_t);
 #endif
 #if !(defined(SUN4M) || defined(SUN4D)) && (defined(SUN4) || defined(SUN4C))
 #define		pmap_rmk	pmap_rmk4_4c
 #define		pmap_rmu	pmap_rmu4_4c
 #elif (defined(SUN4M) || defined(SUN4D)) && !(defined(SUN4) || defined(SUN4C))
 #define		pmap_rmk	pmap_rmk4m
 #define		pmap_rmu	pmap_rmu4m
 #else  /* must use function pointers */
 /* function pointer declarations */
 /* from pmap.h: */
 bool		(*pmap_clear_modify_p)(struct vm_page *);
 bool		(*pmap_clear_reference_p)(struct vm_page *);
 int		(*pmap_enter_p)(pmap_t, vaddr_t, paddr_t, vm_prot_t, int);
 bool		(*pmap_extract_p)(pmap_t, vaddr_t, paddr_t *);
 bool		(*pmap_is_modified_p)(struct vm_page *);
 bool		(*pmap_is_referenced_p)(struct vm_page *);
 void		(*pmap_kenter_pa_p)(vaddr_t, paddr_t, vm_prot_t);
 void		(*pmap_kremove_p)(vaddr_t, vsize_t);
 void		(*pmap_kprotect_p)(vaddr_t, vsize_t, vm_prot_t);
 void		(*pmap_page_protect_p)(struct vm_page *, vm_prot_t);
 void		(*pmap_protect_p)(pmap_t, vaddr_t, vaddr_t, vm_prot_t);
 /* local: */
 void 		(*pmap_rmk_p)(struct pmap *, vaddr_t, vaddr_t, int, int);
 void 		(*pmap_rmu_p)(struct pmap *, vaddr_t, vaddr_t, int, int);
 #define		pmap_rmk	(*pmap_rmk_p)
 #define		pmap_rmu	(*pmap_rmu_p)
 #endif
 /* --------------------------------------------------------------*/
 /*
  * Next we have some sun4m/4d-specific routines which have no 4/4c
  * counterparts, or which are 4/4c macros.
  */
 #if defined(SUN4M) || defined(SUN4D)
 /*
  * SP versions of the tlb flush operations.
+ *
  * Turn off traps to prevent register window overflows
  * from writing user windows to the wrong stack.
  */
 static void
 sp_tlb_flush(int va, int ctx, int lvl)
+{
 	/* Traps off */
 	__asm("rd	%psr, %o3");
 	__asm("wr	%%o3, %0, %%psr" :: "n" (PSR_ET));
 	/* Save context */
 	__asm("mov	%0, %%o4" :: "n"(SRMMU_CXR));
 	__asm("lda	[%%o4]%0, %%o5" :: "n"(ASI_SRMMU));
 	/* Set new context and flush type bits */
 	__asm("andn	%o0, 0xfff, %o0");
 	__asm("sta	%%o1, [%%o4]%0" :: "n"(ASI_SRMMU));
 	__asm("or	%o0, %o2, %o0");
 	/* Do the TLB flush */
 	__asm("sta	%%g0, [%%o0]%0" :: "n"(ASI_SRMMUFP));
 	/* Restore context */
 	__asm("sta	%%o5, [%%o4]%0" :: "n"(ASI_SRMMU));
 	/* and turn traps on again */
 	__asm("wr	%o3, 0, %psr");
 	__asm("nop");
 	__asm("nop");
 	__asm("nop");
+}
 static inline void
 sp_tlb_flush_all(void)
+{
 	sta(ASI_SRMMUFP_LN, ASI_SRMMUFP, 0);
+}
 #if defined(MULTIPROCESSOR)
 /*
  * The SMP versions of the tlb flush routines.  We only need to
  * do a cross call for these on sun4m (Mbus) systems. sun4d systems
  * have an Xbus which broadcasts TLB demaps in hardware.
  */
 static inline void	smp_tlb_flush_page (int va, int ctx, u_int cpuset);
 static inline void	smp_tlb_flush_segment (int va, int ctx, u_int cpuset);
 static inline void	smp_tlb_flush_region (int va, int ctx, u_int cpuset);
 static inline void	smp_tlb_flush_context (int ctx, u_int cpuset);
 static inline void	smp_tlb_flush_all (void);
 /* From locore: */
 extern void ft_tlb_flush(int va, int ctx, int lvl);
 static inline void
 smp_tlb_flush_page(int va, int ctx, u_int cpuset)
+{
 	if (CPU_ISSUN4D) {
 		sp_tlb_flush(va, ctx, ASI_SRMMUFP_L3);
 	} else
 		FXCALL3(sp_tlb_flush, ft_tlb_flush, va, ctx, ASI_SRMMUFP_L3, cpuset);
+}
 static inline void
 smp_tlb_flush_segment(int va, int ctx, u_int cpuset)
+{
 	if (CPU_ISSUN4D) {
 		sp_tlb_flush(va, ctx, ASI_SRMMUFP_L2);
 	} else
 		FXCALL3(sp_tlb_flush, ft_tlb_flush, va, ctx, ASI_SRMMUFP_L2, cpuset);
+}
 static inline void
 smp_tlb_flush_region(int va, int ctx, u_int cpuset)
+{
 	if (CPU_ISSUN4D) {
 		sp_tlb_flush(va, ctx, ASI_SRMMUFP_L1);
 	} else
 		FXCALL3(sp_tlb_flush, ft_tlb_flush, va, ctx, ASI_SRMMUFP_L1, cpuset);
+}
 static inline void
 smp_tlb_flush_context(int ctx, u_int cpuset)
+{
 	if (CPU_ISSUN4D) {
 		sp_tlb_flush(ctx, 0, ASI_SRMMUFP_L0);
 	} else
 		FXCALL3(sp_tlb_flush, ft_tlb_flush, 0, ctx, ASI_SRMMUFP_L0, cpuset);
+}
 static inline void
 smp_tlb_flush_all(void)
+{
 	if (CPU_ISSUN4D) {
 		sp_tlb_flush_all();
 	} else
 		XCALL0(sp_tlb_flush_all, CPUSET_ALL);
+}
 #endif /* MULTIPROCESSOR */
 #if defined(MULTIPROCESSOR)
 #define tlb_flush_page(va,ctx,s)	smp_tlb_flush_page(va,ctx,s)
 #define tlb_flush_segment(va,ctx,s)	smp_tlb_flush_segment(va,ctx,s)
 #define tlb_flush_region(va,ctx,s)	smp_tlb_flush_region(va,ctx,s)
 #define tlb_flush_context(ctx,s)	smp_tlb_flush_context(ctx,s)
 #define tlb_flush_all()			smp_tlb_flush_all()
 #else
 #define tlb_flush_page(va,ctx,s)	sp_tlb_flush(va,ctx,ASI_SRMMUFP_L3)
 #define tlb_flush_segment(va,ctx,s)	sp_tlb_flush(va,ctx,ASI_SRMMUFP_L2)
 #define tlb_flush_region(va,ctx,s)	sp_tlb_flush(va,ctx,ASI_SRMMUFP_L1)
 #define tlb_flush_context(ctx,s)	sp_tlb_flush(ctx,0,ASI_SRMMUFP_L0)
 #define tlb_flush_all()			sp_tlb_flush_all()
 #endif /* MULTIPROCESSOR */
 static u_int	VA2PA(void *);
 static u_long	srmmu_bypass_read(u_long);
 /*
  * VA2PA(addr) -- converts a virtual address to a physical address using
  * the MMU's currently-installed page tables. As a side effect, the address
  * translation used may cause the associated pte to be encached. The correct
  * context for VA must be set before this is called.
+ *
  * This routine should work with any level of mapping, as it is used
  * during bootup to interact with the ROM's initial L1 mapping of the kernel.
  */
 static u_int
 VA2PA(void *addr)
+{
 	u_int pte;
 	/*
 	 * We'll use that handy SRMMU flush/probe.
 	 * Try each level in turn until we find a valid pte. Otherwise panic.
 	 */
 	pte = lda(((u_int)addr & ~0xfff) | ASI_SRMMUFP_L3, ASI_SRMMUFP);
 	/* Unlock fault status; required on Hypersparc modules */
 	(void)lda(SRMMU_SFSR, ASI_SRMMU);
 	if ((pte & SRMMU_TETYPE) == SRMMU_TEPTE)
 	    return (((pte & SRMMU_PPNMASK) << SRMMU_PPNPASHIFT) |
 		    ((u_int)addr & 0xfff));
 	/* A `TLB Flush Entire' is required before any L0, L1 or L2 probe */
 	tlb_flush_all_real();
 	pte = lda(((u_int)addr & ~0xfff) | ASI_SRMMUFP_L2, ASI_SRMMUFP);
 	if ((pte & SRMMU_TETYPE) == SRMMU_TEPTE)
 	    return (((pte & SRMMU_PPNMASK) << SRMMU_PPNPASHIFT) |
 		    ((u_int)addr & 0x3ffff));
 	pte = lda(((u_int)addr & ~0xfff) | ASI_SRMMUFP_L1, ASI_SRMMUFP);
 	if ((pte & SRMMU_TETYPE) == SRMMU_TEPTE)
 	    return (((pte & SRMMU_PPNMASK) << SRMMU_PPNPASHIFT) |
 		    ((u_int)addr & 0xffffff));
 	pte = lda(((u_int)addr & ~0xfff) | ASI_SRMMUFP_L0, ASI_SRMMUFP);
 	if ((pte & SRMMU_TETYPE) == SRMMU_TEPTE)
 	    return (((pte & SRMMU_PPNMASK) << SRMMU_PPNPASHIFT) |
 		    ((u_int)addr & 0xffffffff));
 #ifdef DIAGNOSTIC
 	panic("VA2PA: Asked to translate unmapped VA %p", addr);
 #else
 	return (0);
 #endif
+}
 /*
  * Atomically update a PTE entry, coping with hardware updating the
  * PTE at the same time we are.  This is the procedure that is
  * recommended in the SuperSPARC user's manual.
  */
 int
 updatepte4m(vaddr_t va, int *pte, int bic, int bis, int ctx, u_int cpuset)
+{
 	int oldval, swapval;
 	volatile int *vpte = (volatile int *)pte;
 	/*
 	 * Can only be one of these happening in the system
 	 * at any one time.
 	 */
 	mutex_spin_enter(&demap_lock);
 	/*
 	 * The idea is to loop swapping zero into the pte, flushing
 	 * it, and repeating until it stays zero.  At this point,
 	 * there should be no more hardware accesses to this PTE
 	 * so we can modify it without losing any mod/ref info.
 	 */
 	oldval = 0;
 	do {
 		swapval = 0;
 		swap(vpte, swapval);
 		tlb_flush_page(va, ctx, cpuset);
 		oldval |= swapval;
 	} while (__predict_false(*vpte != 0));
 	swapval = (oldval & ~bic) | bis;
 	swap(vpte, swapval);
 	mutex_spin_exit(&demap_lock);
 	return (oldval);
+}
 inline void
 setpgt4m(int *ptep, int pte)
+{
 	swap(ptep, pte);
+}
 inline void
 setpgt4m_va(vaddr_t va, int *ptep, int pte, int pageflush, int ctx,
 	    u_int cpuset)
+{
 #if defined(MULTIPROCESSOR)
 	updatepte4m(va, ptep, 0xffffffff, pte, pageflush ? ctx : 0, cpuset);
 #else
 	if (__predict_true(pageflush))
 		tlb_flush_page(va, ctx, 0);
 	setpgt4m(ptep, pte);
 #endif /* MULTIPROCESSOR */
+}
 /* Set the page table entry for va to pte. */
 void
 setpte4m(vaddr_t va, int pte)
+{
 	struct pmap *pm;
 	struct regmap *rp;
 	struct segmap *sp;
 #ifdef DEBUG
 	if (getcontext4m() != 0)
 		panic("setpte4m: user context");
 #endif
 	pm = pmap_kernel();
 	rp = &pm->pm_regmap[VA_VREG(va)];
 	sp = &rp->rg_segmap[VA_VSEG(va)];
 	tlb_flush_page(va, 0, CPUSET_ALL);
 	setpgt4m(sp->sg_pte + VA_SUN4M_VPG(va), pte);
+}
 /*
  * Page table pool back-end.
  */
 void *
 pgt_page_alloc(struct pool *pp, int flags)
+{
 	int cacheit = (cpuinfo.flags & CPUFLG_CACHEPAGETABLES) != 0;
 	struct vm_page *pg;
 	vaddr_t va;
 	paddr_t pa;
 	/* Allocate a page of physical memory */
 	if ((pg = uvm_pagealloc(NULL, 0, NULL, 0)) == NULL)
 		return (NULL);
 	/* Allocate virtual memory */
 	va = uvm_km_alloc(kmem_map, PAGE_SIZE, 0, UVM_KMF_VAONLY |
 		((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT | UVM_KMF_TRYLOCK));
 	if (va == 0) {
 		uvm_pagefree(pg);
 		return (NULL);
+	}
 	/*
 	 * On systems with a physical data cache we need to flush this page
 	 * from the cache if the pagetables cannot be cached.
 	 * On systems with a virtually indexed data cache, we only need
 	 * to map it non-cacheable, since the page is not currently mapped.
 	 */
 	pa = VM_PAGE_TO_PHYS(pg);
 	if (cacheit == 0)
 		pcache_flush_page(pa, 1);
 	/* Map the page */
 	pmap_kenter_pa(va, pa | (cacheit ? 0 : PMAP_NC),
 	    VM_PROT_READ | VM_PROT_WRITE);
 	pmap_update(pmap_kernel());
 	return ((void *)va);
+}
 void
 pgt_page_free(struct pool *pp, void *v)
+{
 	vaddr_t va;
 	paddr_t pa;
 	bool rv;
 	va = (vaddr_t)v;
 	rv = pmap_extract(pmap_kernel(), va, &pa);
 	KASSERT(rv);
 	uvm_pagefree(PHYS_TO_VM_PAGE(pa));
 	pmap_kremove(va, PAGE_SIZE);
 	uvm_km_free(kmem_map, va, PAGE_SIZE, UVM_KMF_VAONLY);
+}
 #endif /* SUN4M || SUN4D */
 /*----------------------------------------------------------------*/
 /*
  * The following three macros are to be used in sun4/sun4c code only.
  */
 #if defined(SUN4_MMU3L)
 #define CTX_USABLE(pm,rp) (					\
 		((pm)->pm_ctx != NULL &&			\
 		 (!HASSUN4_MMU3L || (rp)->rg_smeg != reginval))	\
+)
 #else
 #define CTX_USABLE(pm,rp)	((pm)->pm_ctx != NULL )
 #endif
 #define GAP_WIDEN(pm,vr) do if (CPU_HAS_SUNMMU) {		\
 	if (vr + 1 == pm->pm_gap_start)				\
 		pm->pm_gap_start = vr;				\
 	if (vr == pm->pm_gap_end)				\
 		pm->pm_gap_end = vr + 1;			\
 } while (0)
 #define GAP_SHRINK(pm,vr) do if (CPU_HAS_SUNMMU) {			\
 	int x;								\
 	x = pm->pm_gap_start + (pm->pm_gap_end - pm->pm_gap_start) / 2;	\
 	if (vr > x) {							\
 		if (vr < pm->pm_gap_end)				\
 			pm->pm_gap_end = vr;				\
 	} else {							\
 		if (vr >= pm->pm_gap_start && x != pm->pm_gap_start)	\
 			pm->pm_gap_start = vr + 1;			\
 	}								\
 } while (0)
 static void get_phys_mem(void **);
 #if 0 /* not used */
 void	kvm_iocache(char *, int);
 #endif
 #ifdef DEBUG
 void	pm_check(char *, struct pmap *);
 void	pm_check_k(char *, struct pmap *);
 void	pm_check_u(char *, struct pmap *);
 #endif
 /*
  * During the PMAP bootstrap, we can use a simple translation to map a
  * kernel virtual address to a psysical memory address (this is arranged
  * in locore).  Usually, KERNBASE maps to physical address 0. This is always
  * the case on sun4 and sun4c machines. On sun4m machines -- if no memory is
  * installed in the bank corresponding to physical address 0 -- the PROM may
  * elect to load us at some other address, presumably at the start of
  * the first memory bank that is available. We set the up the variable
  * `va2pa_offset' to hold the physical address corresponding to KERNBASE.
  */
 static u_long va2pa_offset;
 #define PMAP_BOOTSTRAP_VA2PA(v) ((paddr_t)((u_long)(v) - va2pa_offset))
 #define PMAP_BOOTSTRAP_PA2VA(p) ((vaddr_t)((u_long)(p) + va2pa_offset))
 /*
  * Grab physical memory list.
  * While here, compute `physmem'.
  */
 void
 get_phys_mem(void **top)
+{
 	struct memarr *mp;
 	char *p;
 	int i;
 	/* Load the memory descriptor array at the current kernel top */
 	p = (void *)ALIGN(*top);
 	pmemarr = (struct memarr *)p;
 	npmemarr = prom_makememarr(pmemarr, 1000, MEMARR_AVAILPHYS);
 	/* Update kernel top */
 	p += npmemarr * sizeof(struct memarr);
 	*top = p;
 	for (physmem = 0, mp = pmemarr, i = npmemarr; --i >= 0; mp++)
 		physmem += btoc(mp->len);
+}
 /*
  * Support functions for vm_page_bootstrap().
  */
 /*
  * How much virtual space does this kernel have?
  * (After mapping kernel text, data, etc.)
  */
 void
 pmap_virtual_space(vaddr_t *v_start, vaddr_t *v_end)
+{
         *v_start = virtual_avail;
         *v_end   = virtual_end;
+}
 #ifdef PMAP_GROWKERNEL
 vaddr_t
 pmap_growkernel(vaddr_t eva)
+{
 	struct regmap *rp;
 	struct segmap *sp;
 	int vr, evr, M, N, i;
 	struct vm_page *pg;
 	vaddr_t va;
 	if (eva <= virtual_end)
 		return (virtual_end);
 	/* For now, only implemented for sun4/sun4c */
 	KASSERT(CPU_HAS_SUNMMU);
 	/*
 	 * Map in the next region(s)
 	 */
 	/* Get current end-of-kernel */
 	vr = virtual_end >> RGSHIFT;
 	evr = (eva + NBPRG - 1) >> RGSHIFT;
 	eva = evr << RGSHIFT;
 	if (eva > VM_MAX_KERNEL_ADDRESS)
 		panic("growkernel: grown too large: %lx", eva);
 	/*
 	 * Divide a region in N blocks of M segments, where each segment
 	 * block can have its PTEs mapped by one page.
 	 * N should come out to 1 for 8K pages and to 4 for 4K pages.
 	 */
 	M = NBPG / (NPTESG * sizeof(int));
 	N = (NBPRG/NBPSG) / M;
 	while (vr < evr) {
 		rp = &pmap_kernel()->pm_regmap[vr];
 		for (i = 0; i < N; i++) {
 			sp = &rp->rg_segmap[i * M];
 			va = (vaddr_t)sp->sg_pte;
 			pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE);
 			if (pg == NULL)
 				panic("growkernel: out of memory");
 			pmap_kenter_pa(va, VM_PAGE_TO_PHYS(pg),
 					VM_PROT_READ | VM_PROT_WRITE);
+		}
+	}
 @@ -2506,2316 +2506,2326 @@ pv_link4_4c(struct vm_page *pg, struct p
 		pv0->pv_pmap = pm;
 		pv0->pv_va = va;
 		pv0->pv_flags |= nc;
 		return (0);
+	}
 	/*
 	 * Allocate the new PV entry now, and, if that fails, bail out
 	 * before changing the cacheable state of the existing mappings.
 	 */
 	npv = pool_get(&pv_pool, PR_NOWAIT);
 	if (npv == NULL)
 		return (ENOMEM);
 	pmap_stats.ps_enter_secondpv++;
 	/*
 	 * Before entering the new mapping, see if
 	 * it will cause old mappings to become aliased
 	 * and thus need to be `discached'.
 	 */
 	if (pv0->pv_flags & PV_ANC) {
 		/* already uncached, just stay that way */
 		*pteprotop |= PG_NC;
 		goto link_npv;
+	}
 	for (pv = pv0; pv != NULL; pv = pv->pv_next) {
 		if ((pv->pv_flags & PV_NC) != 0) {
 			*pteprotop |= PG_NC;
 #ifdef DEBUG
 			/* Check currently illegal condition */
 			if (nc == 0)
 				printf("pv_link: proc %s, va=0x%lx: "
 				"unexpected uncached mapping at 0x%lx\n",
 				    curproc ? curproc->p_comm : "--",
 				    va, pv->pv_va);
 #endif
+		}
 		if (BADALIAS(va, pv->pv_va)) {
 #ifdef DEBUG
 			if (pmapdebug & PDB_CACHESTUFF)
 				printf(
 			"pv_link: badalias: proc %s, 0x%lx<=>0x%lx, pg %p\n",
 				curproc ? curproc->p_comm : "--",
 				va, pv->pv_va, pg);
 #endif
 			/* Mark list head `uncached due to aliases' */
 			pv0->pv_flags |= PV_ANC;
 			pv_changepte4_4c(pg, PG_NC, 0);
 			*pteprotop |= PG_NC;
 			break;
+		}
+	}
 link_npv:
 	npv->pv_next = pv0->pv_next;
 	npv->pv_pmap = pm;
 	npv->pv_va = va;
 	npv->pv_flags = nc;
 	pv0->pv_next = npv;
 	return (0);
+}
 #endif /* SUN4 || SUN4C */
 #if defined(SUN4M) || defined(SUN4D)	/* SRMMU versions of above */
 /*
  * Walk the given pv list, and for each PTE, set or clear some bits
  * (e.g., PG_W or PG_NC).
+ *
  * This routine flushes the cache for any page whose PTE changes,
  * as long as the process has a context; this is overly conservative.
  * It also copies ref and mod bits to the pvlist, on the theory that
  * this might save work later.  (XXX should test this theory)
+ *
  * Called with PV lock and pmap main lock held.
  */
 void
 pv_changepte4m(struct vm_page *pg, int bis, int bic)
+{
 	struct pvlist *pv;
 	struct pmap *pm;
 	vaddr_t va;
 	struct regmap *rp;
 	struct segmap *sp;
 	pv = VM_MDPAGE_PVHEAD(pg);
 	if (pv->pv_pmap == NULL)
 		return;
 	for (; pv != NULL; pv = pv->pv_next) {
 		int tpte;
 		pm = pv->pv_pmap;
 		/* XXXSMP: should lock pm */
 		va = pv->pv_va;
 		rp = &pm->pm_regmap[VA_VREG(va)];
 		sp = &rp->rg_segmap[VA_VSEG(va)];
 		if (pm->pm_ctx) {
 			/*
 			 * XXX: always flush cache; conservative, but
 			 * needed to invalidate cache tag protection
 			 * bits and when disabling caching.
 			 */
 			cache_flush_page(va, pm->pm_ctxnum);
+		}
 		tpte = sp->sg_pte[VA_SUN4M_VPG(va)];
 		KASSERT((tpte & SRMMU_TETYPE) == SRMMU_TEPTE);
 		VM_MDPAGE_PVHEAD(pg)->pv_flags |= MR4M(updatepte4m(va,
 		    &sp->sg_pte[VA_SUN4M_VPG(va)], bic, bis, pm->pm_ctxnum,
 		    PMAP_CPUSET(pm)));
+	}
+}
 /*
  * Sync ref and mod bits in pvlist. If page has been ref'd or modified,
  * update ref/mod bits in pvlist, and clear the hardware bits.
+ *
  * Return the new flags.
  */
 int
 pv_syncflags4m(struct vm_page *pg)
+{
 	struct pvlist *pv;
 	struct pmap *pm;
 	int va, flags;
 	int s;
 	struct regmap *rp;
 	struct segmap *sp;
 	int tpte;
 	s = splvm();
 	PMAP_LOCK();
 	pv = VM_MDPAGE_PVHEAD(pg);
 	if (pv->pv_pmap == NULL) {
 		/* Page not mapped; pv_flags is already up to date */
 		flags = 0;
 		goto out;
+	}
 	flags = pv->pv_flags;
 	for (; pv != NULL; pv = pv->pv_next) {
 		pm = pv->pv_pmap;
 		va = pv->pv_va;
 		rp = &pm->pm_regmap[VA_VREG(va)];
 		sp = &rp->rg_segmap[VA_VSEG(va)];
 		tpte = sp->sg_pte[VA_SUN4M_VPG(va)];
 		if ((tpte & SRMMU_TETYPE) == SRMMU_TEPTE &&
 		    (tpte & (SRMMU_PG_R|SRMMU_PG_M)) != 0) {
 			/*
 			 * Flush cache if modified to make sure the PTE
 			 * M bit will be set again on the next write access.
 			 */
 			if (pm->pm_ctx && (tpte & SRMMU_PG_M) == SRMMU_PG_M)
 				cache_flush_page(va, pm->pm_ctxnum);
 			flags |= MR4M(updatepte4m(va,
 					&sp->sg_pte[VA_SUN4M_VPG(va)],
 					SRMMU_PG_M | SRMMU_PG_R,
 , pm->pm_ctxnum, PMAP_CPUSET(pm)));
+		}
+	}
 	VM_MDPAGE_PVHEAD(pg)->pv_flags = flags;
 out:
 	PMAP_UNLOCK();
 	splx(s);
 	return (flags);
+}
 /*
  * Should be called with pmap already locked.
  */
 void
 pv_unlink4m(struct vm_page *pg, struct pmap *pm, vaddr_t va)
+{
 	struct pvlist *pv0, *npv;
 	pv0 = VM_MDPAGE_PVHEAD(pg);
 	npv = pv0->pv_next;
 	/*
 	 * First entry is special (sigh).
 	 */
 	if (pv0->pv_pmap == pm && pv0->pv_va == va) {
 		pmap_stats.ps_unlink_pvfirst++;
 		if (npv != NULL) {
 			/*
 			 * Shift next entry into the head.
 			 * Make sure to retain the REF, MOD and ANC flags
 			 * on the list head.
 			 */
 			pv0->pv_next = npv->pv_next;
 			pv0->pv_pmap = npv->pv_pmap;
 			pv0->pv_va = npv->pv_va;
 			pv0->pv_flags &= ~PV_NC;
 			pv0->pv_flags |= (npv->pv_flags & PV_NC);
 			pool_put(&pv_pool, npv);
 		} else {
 			/*
 			 * No mappings left; we need to maintain
 			 * the REF and MOD flags, since pmap_is_modified()
 			 * can still be called for this page.
 			 */
 			pv0->pv_pmap = NULL;
 			pv0->pv_flags &= ~(PV_NC|PV_ANC);
 			return;
+		}
 	} else {
 		struct pvlist *prev;
 		pmap_stats.ps_unlink_pvsearch++;
 		for (prev = pv0;; prev = npv, npv = npv->pv_next) {
 			if (npv == NULL) {
 				panic("pv_unlink: pm %p is missing on pg %p",
 					pm, pg);
 				return;
+			}
 			if (npv->pv_pmap == pm && npv->pv_va == va)
 				break;
+		}
 		prev->pv_next = npv->pv_next;
 		pool_put(&pv_pool, npv);
+	}
 	if ((pv0->pv_flags & (PV_NC|PV_ANC)) == PV_ANC) {
 		/*
 		 * Not cached: check whether we can fix that now.
 		 */
 		va = pv0->pv_va;
 		for (npv = pv0->pv_next; npv != NULL; npv = npv->pv_next)
 			if (BADALIAS(va, npv->pv_va) ||
 			    (npv->pv_flags & PV_NC) != 0)
 				return;
 #ifdef DEBUG
 		if (pmapdebug & PDB_CACHESTUFF)
 			printf(
 			"pv_unlink: alias ok: proc %s, va 0x%lx, pg %p\n",
 				curproc ? curproc->p_comm : "--",
 				va, pg);
 #endif
 		pv0->pv_flags &= ~PV_ANC;
 		pv_changepte4m(pg, SRMMU_PG_C, 0);
+	}
+}
 /*
  * pv_link is the inverse of pv_unlink, and is used in pmap_enter.
  * May turn off the cacheable bit in the pte prototype for the new mapping.
  * Called with pm locked.
  */
 /*static*/ int
 pv_link4m(struct vm_page *pg, struct pmap *pm, vaddr_t va,
 	  unsigned int *pteprotop)
+{
 	struct pvlist *pv0, *pv, *npv;
 	int nc = (*pteprotop & SRMMU_PG_C) == 0 ? PV_NC : 0;
 	int error = 0;
 	pv0 = VM_MDPAGE_PVHEAD(pg);
 	if (pv0->pv_pmap == NULL) {
 		/* no pvlist entries yet */
 		pmap_stats.ps_enter_firstpv++;
 		pv0->pv_next = NULL;
 		pv0->pv_pmap = pm;
 		pv0->pv_va = va;
 		pv0->pv_flags |= nc;
 		goto out;
+	}
 	/*
 	 * Allocate the new PV entry now, and, if that fails, bail out
 	 * before changing the cacheable state of the existing mappings.
 	 */
 	npv = pool_get(&pv_pool, PR_NOWAIT);
 	if (npv == NULL) {
 		error = ENOMEM;
 		goto out;
+	}
 	pmap_stats.ps_enter_secondpv++;
 	/*
 	 * See if the new mapping will cause old mappings to
 	 * become aliased and thus need to be `discached'.
 	 */
 	if ((pv0->pv_flags & PV_ANC) != 0) {
 		/* already uncached, just stay that way */
 		*pteprotop &= ~SRMMU_PG_C;
 		goto link_npv;
+	}
 	for (pv = pv0; pv != NULL; pv = pv->pv_next) {
 		if ((pv->pv_flags & PV_NC) != 0) {
 			*pteprotop &= ~SRMMU_PG_C;
 #ifdef DEBUG
 			/* Check currently illegal condition */
 			if (nc == 0)
 				printf("pv_link: proc %s, va=0x%lx: "
 				"unexpected uncached mapping at 0x%lx\n",
 				    curproc ? curproc->p_comm : "--",
 				    va, pv->pv_va);
 #endif
+		}
 		if (BADALIAS(va, pv->pv_va)) {
 #ifdef DEBUG
 			if (pmapdebug & PDB_CACHESTUFF)
 				printf(
 			"pv_link: badalias: proc %s, 0x%lx<=>0x%lx, pg %p\n",
 				curproc ? curproc->p_comm : "--",
 				va, pv->pv_va, pg);
 #endif
 			/* Mark list head `uncached due to aliases' */
 			pv0->pv_flags |= PV_ANC;
 			pv_changepte4m(pg, 0, SRMMU_PG_C);
 			*pteprotop &= ~SRMMU_PG_C;
 			break;
+		}
+	}
 link_npv:
 	/* Now link in the new PV entry */
 	npv->pv_next = pv0->pv_next;
 	npv->pv_pmap = pm;
 	npv->pv_va = va;
 	npv->pv_flags = nc;
 	pv0->pv_next = npv;
 out:
 	return (error);
+}
 #endif
 /*
  * Uncache all entries on behalf of kvm_uncache(). In addition to
  * removing the cache bit from the PTE, we are also setting PV_NC
  * in each entry to stop pv_unlink() from re-caching (i.e. when a
  * a bad alias is going away).
  */
 static void
 pv_uncache(struct vm_page *pg)
+{
 	struct pvlist *pv;
 	int s;
 	s = splvm();
 	PMAP_LOCK();
 	for (pv = VM_MDPAGE_PVHEAD(pg); pv != NULL; pv = pv->pv_next)
 		pv->pv_flags |= PV_NC;
 #if defined(SUN4M) || defined(SUN4D)
 	if (CPU_HAS_SRMMU)
 		pv_changepte4m(pg, 0, SRMMU_PG_C);
 #endif
 #if defined(SUN4) || defined(SUN4C)
 	if (CPU_HAS_SUNMMU)
 		pv_changepte4_4c(pg, PG_NC, 0);
 #endif
 	PMAP_UNLOCK();
 	splx(s);
+}
 /*
  * Walk the given list and flush the cache for each (MI) page that is
  * potentially in the cache. Called only if vactype != VAC_NONE.
  */
 #if defined(SUN4) || defined(SUN4C)
 static void
 pv_flushcache4_4c(struct vm_page *pg)
+{
 	struct pvlist *pv;
 	struct pmap *pm;
 	int s, ctx;
 	pv = VM_MDPAGE_PVHEAD(pg);
 	write_user_windows();	/* paranoia? */
 	s = splvm();		/* XXX extreme paranoia */
 	if ((pm = pv->pv_pmap) != NULL) {
 		ctx = getcontext4();
 		for (;;) {
 			if (pm->pm_ctx) {
 				setcontext4(pm->pm_ctxnum);
 				cache_flush_page(pv->pv_va, pm->pm_ctxnum);
+			}
 			pv = pv->pv_next;
 			if (pv == NULL)
 				break;
 			pm = pv->pv_pmap;
+		}
 		setcontext4(ctx);
+	}
 	splx(s);
+}
 #endif /* SUN4 || SUN4C */
 #if defined(SUN4M) || defined(SUN4D)
 static void
 pv_flushcache4m(struct vm_page *pg)
+{
 	struct pvlist *pv;
 	struct pmap *pm;
 	int s;
 	pv = VM_MDPAGE_PVHEAD(pg);
 	s = splvm();		/* XXX extreme paranoia */
 	if ((pm = pv->pv_pmap) != NULL) {
 		for (;;) {
 			if (pm->pm_ctx) {
 				cache_flush_page(pv->pv_va, pm->pm_ctxnum);
+			}
 			pv = pv->pv_next;
 			if (pv == NULL)
 				break;
 			pm = pv->pv_pmap;
+		}
+	}
 	splx(s);
+}
 #endif /* SUN4M || SUN4D */
 /*----------------------------------------------------------------*/
 /*
  * At last, pmap code.
  */
 #if defined(SUN4) && (defined(SUN4C) || defined(SUN4M) || defined(SUN4D))
 int nptesg;
 #endif
 #if defined(SUN4M) || defined(SUN4D)
 static void pmap_bootstrap4m(void *);
 #endif
 #if defined(SUN4) || defined(SUN4C)
 static void pmap_bootstrap4_4c(void *, int, int, int);
 #endif
 /*
  * Bootstrap the system enough to run with VM enabled.
+ *
  * nsegment is the number of mmu segment entries (``PMEGs'');
  * nregion is the number of mmu region entries (``SMEGs'');
  * nctx is the number of contexts.
  */
 void
 pmap_bootstrap(int nctx, int nregion, int nsegment)
+{
 	void *p;
 	extern char etext[], kernel_data_start[];
 	extern char *kernel_top;
 	uvmexp.pagesize = NBPG;
 	uvm_setpagesize();
 #if defined(SUN4) && (defined(SUN4C) || defined(SUN4M) || defined(SUN4D))
 	/* In this case NPTESG is a variable */
 	nptesg = (NBPSG >> pgshift);
 #endif
 	/*
 	 * Grab physical memory list.
 	 */
 	p = kernel_top;
 	get_phys_mem(&p);
 	/*
 	 * The data segment in sparc ELF images is aligned to a 64KB
 	 * (the maximum page size defined by the ELF/sparc ABI) boundary.
 	 * This results in a unused portion of physical memory in between
 	 * the text/rodata and the data segment. We pick up that gap
 	 * here to remove it from the kernel map and give it to the
 	 * VM manager later.
 	 */
 	etext_gap_start = (vaddr_t)(etext + NBPG - 1) & ~PGOFSET;
 	etext_gap_end = (vaddr_t)kernel_data_start & ~PGOFSET;
 	if (CPU_HAS_SRMMU) {
 #if defined(SUN4M) || defined(SUN4D)
 		pmap_bootstrap4m(p);
 #endif
 	} else if (CPU_HAS_SUNMMU) {
 #if defined(SUN4) || defined(SUN4C)
 		pmap_bootstrap4_4c(p, nctx, nregion, nsegment);
 #endif
+	}
 	pmap_page_upload();
 	mutex_init(&demap_lock, MUTEX_DEFAULT, IPL_VM);
 	mutex_init(&ctx_lock, MUTEX_DEFAULT, IPL_SCHED);
+}
 #if defined(SUN4) || defined(SUN4C)
 void
 pmap_bootstrap4_4c(void *top, int nctx, int nregion, int nsegment)
+{
 	union ctxinfo *ci;
 	struct mmuentry *mmuseg;
 #if defined(SUN4_MMU3L)
 	struct mmuentry *mmureg;
 #endif
 	struct regmap *rp;
 	struct segmap *sp;
 	int i, j;
 	int npte, zseg, vr, vs;
 	int startscookie, scookie;
 #if defined(SUN4_MMU3L)
 	int startrcookie = 0, rcookie = 0;
 #endif
 	int *kptes;
 	int lastpage;
 	vaddr_t va;
 	vaddr_t p;
 	extern char kernel_text[];
 	/*
 	 * Compute `va2pa_offset'.
 	 * Use `kernel_text' to probe the MMU translation since
 	 * the pages at KERNBASE might not be mapped.
 	 */
 	va2pa_offset = (vaddr_t)kernel_text -
 			((getpte4(kernel_text) & PG_PFNUM) << PGSHIFT);
 	ncontext = nctx;
 	switch (cputyp) {
 	case CPU_SUN4C:
 		mmu_has_hole = 1;
 		break;
 	case CPU_SUN4:
 		if (cpuinfo.cpu_type != CPUTYP_4_400) {
 			mmu_has_hole = 1;
 			break;
+		}
+	}
 #if defined(SUN4)
 	/*
 	 * set up the segfixmask to mask off invalid bits
 	 */
 	segfixmask =  nsegment - 1; /* assume nsegment is a power of 2 */
 #ifdef DIAGNOSTIC
 	if (((nsegment & segfixmask) | (nsegment & ~segfixmask)) != nsegment) {
 		printf("pmap_bootstrap: unsuitable number of segments (%d)\n",
 			nsegment);
 		callrom();
+	}
 #endif
 #endif
 #if defined(SUN4M) || defined(SUN4D) /* We're in a dual-arch kernel.
 					Setup 4/4c fn. ptrs */
 	pmap_clear_modify_p 	=	pmap_clear_modify4_4c;
 	pmap_clear_reference_p 	= 	pmap_clear_reference4_4c;
 	pmap_enter_p 		=	pmap_enter4_4c;
 	pmap_extract_p 		=	pmap_extract4_4c;
 	pmap_is_modified_p 	=	pmap_is_modified4_4c;
 	pmap_is_referenced_p	=	pmap_is_referenced4_4c;
 	pmap_kenter_pa_p 	=	pmap_kenter_pa4_4c;
 	pmap_kremove_p	 	=	pmap_kremove4_4c;
 	pmap_kprotect_p	 	=	pmap_kprotect4_4c;
 	pmap_page_protect_p	=	pmap_page_protect4_4c;
 	pmap_protect_p		=	pmap_protect4_4c;
 	pmap_rmk_p		=	pmap_rmk4_4c;
 	pmap_rmu_p		=	pmap_rmu4_4c;
 #endif /* defined SUN4M || defined SUN4D */
 	p = (vaddr_t)top;
 	/*
 	 * Last segment is the `invalid' one (one PMEG of pte's with !pg_v).
 	 * It will never be used for anything else.
 	 */
 	seginval = --nsegment;
 #if defined(SUN4_MMU3L)
 	if (HASSUN4_MMU3L)
 		reginval = --nregion;
 #endif
 	/*
 	 * Allocate and initialise mmu entries and context structures.
 	 */
 #if defined(SUN4_MMU3L)
 	mmuregions = mmureg = (struct mmuentry *)p;
 	p += nregion * sizeof(struct mmuentry);
 	memset(mmuregions, 0, nregion * sizeof(struct mmuentry));
 #endif
 	mmusegments = mmuseg = (struct mmuentry *)p;
 	p += nsegment * sizeof(struct mmuentry);
 	memset(mmusegments, 0, nsegment * sizeof(struct mmuentry));
 	pmap_kernel()->pm_ctx = ctxinfo = ci = (union ctxinfo *)p;
 	p += nctx * sizeof *ci;
 	/* Initialize MMU resource queues */
 #if defined(SUN4_MMU3L)
 	MMUQ_INIT(&region_freelist);
 	MMUQ_INIT(&region_lru);
 	MMUQ_INIT(&region_locked);
 #endif
 	MMUQ_INIT(&segm_freelist);
 	MMUQ_INIT(&segm_lru);
 	MMUQ_INIT(&segm_locked);
 	/*
 	 * Intialize the kernel pmap.
 	 */
 	/* kernel_pmap_store.pm_ctxnum = 0; */
 	kernel_pmap_store.pm_refcount = 1;
 #if defined(SUN4_MMU3L)
 	TAILQ_INIT(&kernel_pmap_store.pm_reglist);
 #endif
 	TAILQ_INIT(&kernel_pmap_store.pm_seglist);
 	/*
 	 * Allocate memory for kernel PTEs
 	 * XXX Consider allocating memory for only a few regions
 	 * and use growkernel() to allocate more as needed.
 	 */
 	kptes = (int *)p;
 	p += NKREG * NSEGRG * NPTESG * sizeof(int);
 	memset(kptes, 0, NKREG * NSEGRG * NPTESG * sizeof(int));
 	/*
 	 * Set up pm_regmap for kernel to point NUREG *below* the beginning
 	 * of kernel regmap storage. Since the kernel only uses regions
 	 * above NUREG, we save storage space and can index kernel and
 	 * user regions in the same way.
 	 */
 	kernel_pmap_store.pm_regmap = &kernel_regmap_store[-NUREG];
 	for (i = NKREG; --i >= 0;) {
 #if defined(SUN4_MMU3L)
 		kernel_regmap_store[i].rg_smeg = reginval;
 #endif
 		kernel_regmap_store[i].rg_segmap =
 			&kernel_segmap_store[i * NSEGRG];
 		for (j = NSEGRG; --j >= 0;) {
 			sp = &kernel_segmap_store[i * NSEGRG + j];
 			sp->sg_pmeg = seginval;
 			sp->sg_pte = &kptes[(i * NSEGRG + j) * NPTESG];
+		}
+	}
 	/*
 	 * Preserve the monitor ROM's reserved VM region, so that
 	 * we can use L1-A or the monitor's debugger.  As a side
 	 * effect we map the ROM's reserved VM into all contexts
 	 * (otherwise L1-A crashes the machine!).
 	 */
 	mmu_reservemon4_4c(&nregion, &nsegment);
 #if defined(SUN4_MMU3L)
 	/* Reserve one region for temporary mappings */
 	if (HASSUN4_MMU3L)
 		tregion = --nregion;
 #endif
 	/*
 	 * Set up the `constants' for the call to vm_init()
 	 * in main().  All pages beginning at p (rounded up to
 	 * the next whole page) and continuing through the number
 	 * of available pages are free, but they start at a higher
 	 * virtual address.  This gives us two mappable MD pages
 	 * for pmap_zero_page and pmap_copy_page, and one MI page
 	 * for /dev/mem, all with no associated physical memory.
 	 */
 	p = (p + NBPG - 1) & ~PGOFSET;
 	avail_start = PMAP_BOOTSTRAP_VA2PA(p);
 	i = p;
 	cpuinfo.vpage[0] = (void *)p, p += NBPG;
 	cpuinfo.vpage[1] = (void *)p, p += NBPG;
 	vmmap = (void *)p, p += NBPG;
 	p = (vaddr_t)reserve_dumppages((void *)p);
 	virtual_avail = p;
 	virtual_end = VM_MAX_KERNEL_ADDRESS;
 	p = i;			/* retract to first free phys */
 	/*
 	 * All contexts are free except the kernel's.
+	 *
 	 * XXX sun4c could use context 0 for users?
 	 */
 	ci->c_pmap = pmap_kernel();
 	ctx_freelist = ci + 1;
 	for (i = 1; i < ncontext; i++) {
 		ci++;
 		ci->c_nextfree = ci + 1;
+	}
 	ci->c_nextfree = NULL;
 	ctx_kick = 0;
 	ctx_kickdir = -1;
 	/*
 	 * Init mmu entries that map the kernel physical addresses.
+	 *
 	 * All the other MMU entries are free.
+	 *
 	 * THIS ASSUMES THE KERNEL IS MAPPED BY A CONTIGUOUS RANGE OF
 	 * MMU SEGMENTS/REGIONS DURING THE BOOT PROCESS
 	 */
 	/* Compute the number of segments used by the kernel */
 	zseg = (((p + NBPSG - 1) & ~SGOFSET) - KERNBASE) >> SGSHIFT;
 	lastpage = VA_VPG(p);
 	if (lastpage == 0)
 		/*
 		 * If the page bits in p are 0, we filled the last segment
 		 * exactly; if not, it is the last page filled in the
 		 * last segment.
 		 */
 		lastpage = NPTESG;
 	p = KERNBASE;			/* first va */
 	vs = VA_VSEG(KERNBASE);		/* first virtual segment */
 	vr = VA_VREG(KERNBASE);		/* first virtual region */
 	rp = &pmap_kernel()->pm_regmap[vr];
 	/* Get region/segment where kernel addresses start */
 #if defined(SUN4_MMU3L)
 	if (HASSUN4_MMU3L)
 		startrcookie = rcookie = getregmap(p);
 	mmureg = &mmuregions[rcookie];
 #endif
 	startscookie = scookie = getsegmap(p);
 	mmuseg = &mmusegments[scookie];
 	zseg += scookie;	/* First free segment */
 	for (;;) {
 		/*
 		 * Distribute each kernel region/segment into all contexts.
 		 * This is done through the monitor ROM, rather than
 		 * directly here: if we do a setcontext we will fault,
 		 * as we are not (yet) mapped in any other context.
 		 */
 		if ((vs % NSEGRG) == 0) {
 			/* Entering a new region */
 			if (VA_VREG(p) > vr) {
 #ifdef DEBUG
 				printf("note: giant kernel!\n");
 #endif
 				vr++, rp++;
+			}
 #if defined(SUN4_MMU3L)
 			if (HASSUN4_MMU3L) {
 				for (i = 1; i < nctx; i++)
 					prom_setcontext(i, (void *)p, rcookie);
 				MMUQ_INSERT_TAIL(&region_locked,
 						  mmureg, me_list);
 				TAILQ_INSERT_TAIL(&pmap_kernel()->pm_reglist,
 						  mmureg, me_pmchain);
 #ifdef DIAGNOSTIC
 				mmuseg->me_statp = NULL;
 #endif
 				mmureg->me_cookie = rcookie;
 				mmureg->me_pmap = pmap_kernel();
 				mmureg->me_vreg = vr;
 				rp->rg_smeg = rcookie;
 				mmureg++;
 				rcookie++;
+			}
 #endif /* SUN4_MMU3L */
+		}
 #if defined(SUN4_MMU3L)
 		if (!HASSUN4_MMU3L)
 #endif
 			for (i = 1; i < nctx; i++)
 				prom_setcontext(i, (void *)p, scookie);
 		/* set up the mmu entry */
 		MMUQ_INSERT_TAIL(&segm_locked, mmuseg, me_list);
 #ifdef DIAGNOSTIC
 		mmuseg->me_statp = &pmap_stats.ps_npmeg_locked;
 #endif
 		TAILQ_INSERT_TAIL(&pmap_kernel()->pm_seglist, mmuseg, me_pmchain);
 		pmap_stats.ps_npmeg_locked++;
 		mmuseg->me_cookie = scookie;
 		mmuseg->me_pmap = pmap_kernel();
 		mmuseg->me_vreg = vr;
 		mmuseg->me_vseg = vs % NSEGRG;
 		sp = &rp->rg_segmap[vs % NSEGRG];
 		sp->sg_pmeg = scookie;
 		npte = ++scookie < zseg ? NPTESG : lastpage;
 		sp->sg_npte = npte;
 		sp->sg_nwired = npte;
 		pmap_kernel()->pm_stats.resident_count += npte;
 		rp->rg_nsegmap += 1;
 		for (i = 0; i < npte; i++)
 			sp->sg_pte[i] = getpte4(p + i * NBPG) | PG_WIRED;
 		mmuseg++;
 		vs++;
 		if (scookie < zseg) {
 			p += NBPSG;
 			continue;
+		}
 		/*
 		 * Unmap the pages, if any, that are not part of
 		 * the final segment.
 		 */
 		for (p += npte << PGSHIFT; npte < NPTESG; npte++, p += NBPG)
 			setpte4(p, 0);
 #if defined(SUN4_MMU3L)
 		if (HASSUN4_MMU3L) {
 			/*
 			 * Unmap the segments, if any, that are not part of
 			 * the final region.
 			 */
 			for (i = rp->rg_nsegmap; i < NSEGRG; i++, p += NBPSG)
 				setsegmap(p, seginval);
 			/*
 			 * Unmap any kernel regions that we aren't using.
 			 */
 			for (i = 0; i < nctx; i++) {
 				setcontext4(i);
 				for (va = p;
 				     va < (OPENPROM_STARTVADDR & ~(NBPRG - 1));
 				     va += NBPRG)
 					setregmap(va, reginval);
+			}
 		} else
 #endif
+		{
 			/*
 			 * Unmap any kernel segments that we aren't using.
 			 */
 			for (i = 0; i < nctx; i++) {
 				setcontext4(i);
 				for (va = p;
 				     va < (OPENPROM_STARTVADDR & ~(NBPSG - 1));
 				     va += NBPSG)
 					setsegmap(va, seginval);
+			}
+		}
 		break;
+	}
 #if defined(SUN4_MMU3L)
 	if (HASSUN4_MMU3L)
 		for (rcookie = 0; rcookie < nregion; rcookie++) {
 			if (rcookie == startrcookie)
 				/* Kernel must fit in one region! */
 				rcookie++;
 			mmureg = &mmuregions[rcookie];
 			mmureg->me_cookie = rcookie;
 			MMUQ_INSERT_TAIL(&region_freelist, mmureg, me_list);
 #ifdef DIAGNOSTIC
 			mmuseg->me_statp = NULL;
 #endif
+		}
 #endif /* SUN4_MMU3L */
 	for (scookie = 0; scookie < nsegment; scookie++) {
 		if (scookie == startscookie)
 			/* Skip static kernel image */
 			scookie = zseg;
 		mmuseg = &mmusegments[scookie];
 		mmuseg->me_cookie = scookie;
 		MMUQ_INSERT_TAIL(&segm_freelist, mmuseg, me_list);
 		pmap_stats.ps_npmeg_free++;
 #ifdef DIAGNOSTIC
 		mmuseg->me_statp = NULL;
 #endif
+	}
 	/* Erase all spurious user-space segmaps */
 	for (i = 1; i < ncontext; i++) {
 		setcontext4(i);
 		if (HASSUN4_MMU3L)
 			for (p = 0, j = NUREG; --j >= 0; p += NBPRG)
 				setregmap(p, reginval);
 		else
 			for (p = 0, vr = 0; vr < NUREG; vr++) {
 				if (VA_INHOLE(p)) {
 					p = MMU_HOLE_END;
 					vr = VA_VREG(p);
+				}
 				for (j = NSEGRG; --j >= 0; p += NBPSG)
 					setsegmap(p, seginval);
+			}
+	}
 	setcontext4(0);
 	/*
 	 * write protect & encache kernel text;
 	 * set red zone at kernel base;
 	 * enable cache on message buffer and cpuinfo.
 	 */
+	{
 		extern char etext[];
 		/* Enable cache on message buffer and cpuinfo */
 		for (p = KERNBASE; p < (vaddr_t)trapbase; p += NBPG)
 			setpte4(p, getpte4(p) & ~PG_NC);
 		/* Enable cache and write protext kernel text */
 		for (p = (vaddr_t)trapbase; p < (vaddr_t)etext; p += NBPG)
 			setpte4(p, getpte4(p) & ~(PG_NC|PG_W));
 		/*
 		 * Unmap the `etext gap'; it'll be made available
 		 * to the VM manager.
 		 */
 		for (p = etext_gap_start; p < etext_gap_end; p += NBPG) {
 			rp = &pmap_kernel()->pm_regmap[VA_VREG(p)];
 			sp = &rp->rg_segmap[VA_VSEG(p)];
 			sp->sg_nwired--;
 			sp->sg_npte--;
 			pmap_kernel()->pm_stats.resident_count--;
 			sp->sg_pte[VA_VPG(p)] = 0;
 			setpte4(p, 0);
+		}
 		/* Enable cache on data & bss */
 		for (p = etext_gap_end; p < virtual_avail; p += NBPG)
 			setpte4(p, getpte4(p) & ~PG_NC);
+	}
+}
 #endif
 #if defined(SUN4M) || defined(SUN4D)	/* SRMMU version of pmap_bootstrap */
 /*
  * Bootstrap the system enough to run with VM enabled on a sun4m machine.
+ *
  * Switches from ROM to kernel page tables, and sets up initial mappings.
  */
 static void
 pmap_bootstrap4m(void *top)
+{
 	int i, j;
 	vaddr_t p, q;
 	union ctxinfo *ci;
 	int reg, seg;
 	unsigned int ctxtblsize;
 	vaddr_t pagetables_start, pagetables_end;
 	paddr_t pagetables_start_pa;
 	extern char etext[];
 	extern char kernel_text[];
 	vaddr_t va;
 #ifdef MULTIPROCESSOR
 	vsize_t off;
 	size_t cpuinfo_len;
 	uint8_t *cpuinfo_data;
 #endif
 	/*
 	 * Compute `va2pa_offset'.
 	 * Use `kernel_text' to probe the MMU translation since
 	 * the pages at KERNBASE might not be mapped.
 	 */
 	va2pa_offset = (vaddr_t)kernel_text - VA2PA(kernel_text);
 	ncontext = cpuinfo.mmu_ncontext;
 #if defined(SUN4) || defined(SUN4C) /* setup SRMMU fn. ptrs for dual-arch
 				       kernel */
 	pmap_clear_modify_p 	=	pmap_clear_modify4m;
 	pmap_clear_reference_p 	= 	pmap_clear_reference4m;
 	pmap_enter_p 		=	pmap_enter4m;
 	pmap_extract_p 		=	pmap_extract4m;
 	pmap_is_modified_p 	=	pmap_is_modified4m;
 	pmap_is_referenced_p	=	pmap_is_referenced4m;
 	pmap_kenter_pa_p 	=	pmap_kenter_pa4m;
 	pmap_kremove_p	 	=	pmap_kremove4m;
 	pmap_kprotect_p	 	=	pmap_kprotect4m;
 	pmap_page_protect_p	=	pmap_page_protect4m;
 	pmap_protect_p		=	pmap_protect4m;
 	pmap_rmk_p		=	pmap_rmk4m;
 	pmap_rmu_p		=	pmap_rmu4m;
 #endif /* defined SUN4/SUN4C */
 	/*
 	 * p points to top of kernel mem
 	 */
 	p = (vaddr_t)top;
 #if defined(MULTIPROCESSOR)
 	/*
 	 * allocate the rest of the cpu_info{} area.  note we waste the
 	 * first one to get a VA space.
 	 */
 	cpuinfo_len = ((sizeof(struct cpu_info) + NBPG - 1) & ~PGOFSET);
 	if (sparc_ncpus > 1) {
 		p = (p + NBPG - 1) & ~PGOFSET;
 		cpuinfo_data = (uint8_t *)p;
 		p += (cpuinfo_len * sparc_ncpus);
 		/* XXX we waste the first one */
 		memset(cpuinfo_data + cpuinfo_len, 0, cpuinfo_len * (sparc_ncpus - 1));
 	} else
 		cpuinfo_data = (uint8_t *)CPUINFO_VA;
 #endif
 	/*
 	 * Intialize the kernel pmap.
 	 */
 	/* kernel_pmap_store.pm_ctxnum = 0; */
 	kernel_pmap_store.pm_refcount = 1;
 	/*
 	 * Set up pm_regmap for kernel to point NUREG *below* the beginning
 	 * of kernel regmap storage. Since the kernel only uses regions
 	 * above NUREG, we save storage space and can index kernel and
 	 * user regions in the same way.
 	 */
 	kernel_pmap_store.pm_regmap = &kernel_regmap_store[-NUREG];
 	memset(kernel_regmap_store, 0, NKREG * sizeof(struct regmap));
 	memset(kernel_segmap_store, 0, NKREG * NSEGRG * sizeof(struct segmap));
 	for (i = NKREG; --i >= 0;) {
 		kernel_regmap_store[i].rg_segmap =
 			&kernel_segmap_store[i * NSEGRG];
 		kernel_regmap_store[i].rg_seg_ptps = NULL;
 		for (j = NSEGRG; --j >= 0;)
 			kernel_segmap_store[i * NSEGRG + j].sg_pte = NULL;
+	}
 	/* Allocate kernel region pointer tables */
 	pmap_kernel()->pm_reg_ptps = (int **)(q = p);
 	p += sparc_ncpus * sizeof(int **);
 	memset((void *)q, 0, (u_int)p - (u_int)q);
 	pmap_kernel()->pm_reg_ptps_pa = (int *)(q = p);
 	p += sparc_ncpus * sizeof(int *);
 	memset((void *)q, 0, (u_int)p - (u_int)q);
 	/* Allocate context administration */
 	pmap_kernel()->pm_ctx = ctxinfo = ci = (union ctxinfo *)p;
 	p += ncontext * sizeof *ci;
 	memset((void *)ci, 0, (u_int)p - (u_int)ci);
 #if defined(MULTIPROCESSOR)
 	/*
 	 * allocate the rest of the cpu_info{} area.  note we waste the
 	 * first one to get a VA space.
 	 */
 	p = (p + NBPG - 1) & ~PGOFSET;
 	cpuinfo_data = (uint8_t *)p;
 	cpuinfo_len = ((sizeof(struct cpu_info) + NBPG - 1) & ~PGOFSET);
 	p += (cpuinfo_len * sparc_ncpus);
 	prom_printf("extra cpus: %p, p: %p, gap start: %p, gap end: %p\n",
 	    cpuinfo_data, p, etext_gap_start, etext_gap_end);
 	/* XXX we waste the first one */
 	memset(cpuinfo_data + cpuinfo_len, 0, cpuinfo_len * (sparc_ncpus - 1));
 #endif
 	/*
 	 * Set up the `constants' for the call to vm_init()
 	 * in main().  All pages beginning at p (rounded up to
 	 * the next whole page) and continuing through the number
 	 * of available pages are free.
 	 */
 	p = (p + NBPG - 1) & ~PGOFSET;
 	/*
 	 * Reserve memory for MMU pagetables. Some of these have severe
 	 * alignment restrictions. We allocate in a sequence that
 	 * minimizes alignment gaps.
 	 */
 	pagetables_start = p;
 	pagetables_start_pa = PMAP_BOOTSTRAP_VA2PA(p);
 	/*
 	 * Allocate context table.
 	 * To keep supersparc happy, minimum aligment is on a 4K boundary.
 	 */
 	ctxtblsize = max(ncontext,1024) * sizeof(int);
 	cpuinfo.ctx_tbl = (int *)roundup((u_int)p, ctxtblsize);
 	cpuinfo.ctx_tbl_pa = PMAP_BOOTSTRAP_VA2PA(cpuinfo.ctx_tbl);
 	p = (u_int)cpuinfo.ctx_tbl + ctxtblsize;
 #if defined(MULTIPROCESSOR)
 	/*
 	 * Make sure all smp_tlb_flush*() routines for kernel pmap are
 	 * broadcast to all CPU's.
 	 */
 	pmap_kernel()->pm_cpuset = CPUSET_ALL;
 #endif
 	/*
 	 * Reserve memory for segment and page tables needed to map the entire
 	 * kernel. This takes (2K + NKREG * 16K) of space, but unfortunately
 	 * is necessary since pmap_enter() *must* be able to enter a kernel
 	 * mapping without delay.
 	 */
 	p = (vaddr_t) roundup(p, SRMMU_L1SIZE * sizeof(u_int));
 	qzero((void *)p, SRMMU_L1SIZE * sizeof(u_int));
 	kernel_regtable_store = (u_int *)p;
 	p += SRMMU_L1SIZE * sizeof(u_int);
 	p = (vaddr_t) roundup(p, SRMMU_L2SIZE * sizeof(u_int));
 	qzero((void *)p, (SRMMU_L2SIZE * sizeof(u_int)) * NKREG);
 	kernel_segtable_store = (u_int *)p;
 	p += (SRMMU_L2SIZE * sizeof(u_int)) * NKREG;
 	p = (vaddr_t) roundup(p, SRMMU_L3SIZE * sizeof(u_int));
 	/* zero it: all will be SRMMU_TEINVALID */
 	qzero((void *)p, ((SRMMU_L3SIZE * sizeof(u_int)) * NSEGRG) * NKREG);
 	kernel_pagtable_store = (u_int *)p;
 	p += ((SRMMU_L3SIZE * sizeof(u_int)) * NSEGRG) * NKREG;
 	/* Round to next page and mark end of pre-wired kernel space */
 	p = (p + NBPG - 1) & ~PGOFSET;
 	pagetables_end = p;
 	avail_start = PMAP_BOOTSTRAP_VA2PA(p);
 	/*
 	 * Now wire the region and segment tables of the kernel map.
 	 */
 	pmap_kernel()->pm_reg_ptps[0] = (int *) kernel_regtable_store;
 	pmap_kernel()->pm_reg_ptps_pa[0] =
 		 PMAP_BOOTSTRAP_VA2PA(kernel_regtable_store);
 	/* Install L1 table in context 0 */
 	setpgt4m(&cpuinfo.ctx_tbl[0],
 	    (pmap_kernel()->pm_reg_ptps_pa[0] >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD);
 	for (reg = 0; reg < NKREG; reg++) {
 		struct regmap *rp;
 		void *kphyssegtbl;
 		/*
 		 * Entering new region; install & build segtbl
 		 */
 		rp = &pmap_kernel()->pm_regmap[reg + VA_VREG(KERNBASE)];
 		kphyssegtbl = (void *)
 		    &kernel_segtable_store[reg * SRMMU_L2SIZE];
 		setpgt4m(&pmap_kernel()->pm_reg_ptps[0][reg + VA_VREG(KERNBASE)],
 		    (PMAP_BOOTSTRAP_VA2PA(kphyssegtbl) >> SRMMU_PPNPASHIFT) |
 		    SRMMU_TEPTD);
 		rp->rg_seg_ptps = (int *)kphyssegtbl;
 		for (seg = 0; seg < NSEGRG; seg++) {
 			struct segmap *sp;
 			void *kphyspagtbl;
 			rp->rg_nsegmap++;
 			sp = &rp->rg_segmap[seg];
 			kphyspagtbl = (void *)
 			    &kernel_pagtable_store
 				[((reg * NSEGRG) + seg) * SRMMU_L3SIZE];
 			setpgt4m(&rp->rg_seg_ptps[seg],
 				 (PMAP_BOOTSTRAP_VA2PA(kphyspagtbl) >> SRMMU_PPNPASHIFT) |
 				 SRMMU_TEPTD);
 			sp->sg_pte = (int *) kphyspagtbl;
+		}
+	}
 	/*
 	 * Preserve the monitor ROM's reserved VM region, so that
 	 * we can use L1-A or the monitor's debugger.
 	 */
 	mmu_reservemon4m(&kernel_pmap_store);
 	/*
 	 * Reserve virtual address space for two mappable MD pages
 	 * for pmap_zero_page and pmap_copy_page, one MI page
 	 * for /dev/mem, and some more for dumpsys().
 	 */
 	q = p;
 	cpuinfo.vpage[0] = (void *)p, p += NBPG;
 	cpuinfo.vpage[1] = (void *)p, p += NBPG;
 	vmmap = (void *)p, p += NBPG;
 	p = (vaddr_t)reserve_dumppages((void *)p);
 	/* Find PTE locations of vpage[] to optimize zero_fill() et.al. */
 	for (i = 0; i < 2; i++) {
 		struct regmap *rp;
 		struct segmap *sp;
 		rp = &pmap_kernel()->pm_regmap[VA_VREG(cpuinfo.vpage[i])];
 		sp = &rp->rg_segmap[VA_VSEG(cpuinfo.vpage[i])];
 		cpuinfo.vpage_pte[i] =
 			&sp->sg_pte[VA_SUN4M_VPG(cpuinfo.vpage[i])];
+	}
 #if !(defined(PROM_AT_F0) || defined(MSIIEP))
 	virtual_avail = p;
 #elif defined(MSIIEP)
 	virtual_avail = (vaddr_t)0xf0800000; /* Krups */
 #else
 	virtual_avail = (vaddr_t)0xf0080000; /* Mr.Coffee/OFW */
 #endif
 	virtual_end = VM_MAX_KERNEL_ADDRESS;
 	p = q;			/* retract to first free phys */
 	/*
 	 * Set up the ctxinfo structures (freelist of contexts)
 	 */
 	ci->c_pmap = pmap_kernel();
 	ctx_freelist = ci + 1;
 	for (i = 1; i < ncontext; i++) {
 		ci++;
 		ci->c_nextfree = ci + 1;
+	}
 	ci->c_nextfree = NULL;
 	ctx_kick = 0;
 	ctx_kickdir = -1;
 	/*
 	 * Now map the kernel into our new set of page tables, then
 	 * (finally) switch over to our running page tables.
 	 * We map from KERNBASE to p into context 0's page tables (and
 	 * the kernel pmap).
 	 */
 #ifdef DEBUG			/* Sanity checks */
 	if (p % NBPG != 0)
 		panic("pmap_bootstrap4m: p misaligned?!?");
 	if (KERNBASE % NBPRG != 0)
 		panic("pmap_bootstrap4m: KERNBASE not region-aligned");
 #endif
 	for (q = KERNBASE; q < p; q += NBPG) {
 		struct regmap *rp;
 		struct segmap *sp;
 		int pte, *ptep;
 		/*
 		 * Now install entry for current page.
 		 */
 		rp = &pmap_kernel()->pm_regmap[VA_VREG(q)];
 		sp = &rp->rg_segmap[VA_VSEG(q)];
 		ptep = &sp->sg_pte[VA_VPG(q)];
 		/*
 		 * Unmap the `etext gap'; it'll be made available
 		 * to the VM manager.
 		 */
 		if (q >= etext_gap_start && q < etext_gap_end) {
 			setpgt4m(ptep, 0);
 			continue;
+		}
 		pte = PMAP_BOOTSTRAP_VA2PA(q) >> SRMMU_PPNPASHIFT;
 		pte |= PPROT_N_RX | SRMMU_TEPTE;
 		/* Deal with the cacheable bit for pagetable memory */
 		if ((cpuinfo.flags & CPUFLG_CACHEPAGETABLES) != 0 ||
 		    q < pagetables_start || q >= pagetables_end)
 			pte |= SRMMU_PG_C;
 		/* write-protect kernel text */
 		if (q < (vaddr_t)trapbase || q >= (vaddr_t)etext)
 			pte |= PPROT_WRITE;
 		setpgt4m(ptep, pte);
 		pmap_kernel()->pm_stats.resident_count++;
+	}
 	if ((cpuinfo.flags & CPUFLG_CACHEPAGETABLES) == 0) {
 		/*
 		 * The page tables have been setup. Since we're still
 		 * running on the PROM's memory map, the memory we
 		 * allocated for our page tables might still be cached.
 		 * Flush it now, and don't touch it again until we
 		 * switch to our own tables (will be done immediately below).
 		 */
 		int size = pagetables_end - pagetables_start;
 		if (CACHEINFO.c_vactype != VAC_NONE) {
 			va = (vaddr_t)pagetables_start;
 			while (size > 0) {
 				cache_flush_page(va, 0);
 				va += NBPG;
 				size -= NBPG;
+			}
 		} else if (cpuinfo.pcache_flush_page != NULL) {
 			paddr_t pa = pagetables_start_pa;
 			while (size > 0) {
 				pcache_flush_page(pa, 0);
 				pa += NBPG;
 				size -= NBPG;
+			}
+		}
+	}
 	/*
 	 * Now switch to kernel pagetables (finally!)
 	 */
 	mmu_install_tables(&cpuinfo);
 #ifdef MULTIPROCESSOR
 	/*
 	 * Initialise any cpu-specific data now.
 	 */
 	cpu_init_system();
 	/*
 	 * Remap cpu0 from CPUINFO_VA to the new correct value, wasting the
-	 * backing pages we allocated above XXX.
+	 * backing page we allocated above XXX.
 	 */
 	for (off = 0, va = (vaddr_t)cpuinfo_data;
-	     off < sizeof(struct cpu_info);
+	     sparc_ncpus > 1 && off < sizeof(struct cpu_info);
 	     va += NBPG, off += NBPG) {
 		paddr_t pa = PMAP_BOOTSTRAP_VA2PA(CPUINFO_VA + off);
 		prom_printf("going to pmap_kenter_pa(va=%p, pa=%p)\n", va, pa);
 		pmap_kremove(va, NBPG);
 		pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
 		cache_flush_page(va, 0);
 		cache_flush_page(CPUINFO_VA, 0);
+	}
 	/*
 	 * Setup the cpus[] array and the ci_self links.
 	 */
 	prom_printf("setting cpus self reference\n");
 	for (i = 0; i < sparc_ncpus; i++) {
 		cpus[i] = (struct cpu_info *)(cpuinfo_data + (cpuinfo_len * i));
 		cpus[i]->ci_self = cpus[i];
 		prom_printf("set cpu%d ci_self address: %p\n", i, cpus[i]);
+	}
 #else
 	cpus[0] = (struct cpu_info *)CPUINFO_VA;
 #endif
 	pmap_update(pmap_kernel());
 	prom_printf("pmap_bootstrap4m done\n");
+}
 static u_long prom_ctxreg;
 void
 mmu_install_tables(struct cpu_info *sc)
+{
 #ifdef DEBUG
 	prom_printf("pmap_bootstrap: installing kernel page tables...");
 #endif
 	setcontext4m(0);	/* paranoia? %%%: Make 0x3 a define! below */
 	/* Enable MMU tablewalk caching, flush TLB */
 	if (sc->mmu_enable != 0)
 		sc->mmu_enable();
 	tlb_flush_all_real();
 	prom_ctxreg = lda(SRMMU_CXTPTR, ASI_SRMMU);
 	sta(SRMMU_CXTPTR, ASI_SRMMU,
 		(sc->ctx_tbl_pa >> SRMMU_PPNPASHIFT) & ~0x3);
 	tlb_flush_all_real();
 #ifdef DEBUG
 	prom_printf("done.\n");
 #endif
+}
 void srmmu_restore_prom_ctx(void);
 void
 srmmu_restore_prom_ctx(void)
+{
 	tlb_flush_all();
 	sta(SRMMU_CXTPTR, ASI_SRMMU, prom_ctxreg);
 	tlb_flush_all();
+}
 #endif /* SUN4M || SUN4D */
 #if defined(MULTIPROCESSOR)
 /*
  * Allocate per-CPU page tables. One region, segment and page table
  * is needed to map CPUINFO_VA to different physical addresses on
  * each CPU. Since the kernel region and segment tables are all
  * pre-wired (in bootstrap() above) and we also assume that the
  * first segment (256K) of kernel space is fully populated with
  * pages from the start, these per-CPU tables will never need
  * to be updated when mapping kernel virtual memory.
+ *
  * Note: this routine is called in the context of the boot CPU
  * during autoconfig.
  */
 void
 pmap_alloc_cpu(struct cpu_info *sc)
+{
 #if defined(SUN4M) || defined(SUN4D)	/* Only implemented for SUN4M/D */
 	vaddr_t va;
 	paddr_t pa;
 	paddr_t alignment;
 	u_int *ctxtable, *regtable, *segtable, *pagtable;
 	u_int *ctxtable_pa, *regtable_pa, *segtable_pa, *pagtable_pa;
 	psize_t ctxsize, size;
 	int vr, vs, vpg;
 	struct regmap *rp;
 	struct segmap *sp;
 	struct pglist mlist;
 	int cachebit;
 	int pagesz = NBPG;
 	int i;
 	cachebit = (cpuinfo.flags & CPUFLG_CACHEPAGETABLES) != 0;
 	/*
 	 * Allocate properly aligned and contiguous physically memory
 	 * for the PTE tables.
 	 */
 	ctxsize = (sc->mmu_ncontext * sizeof(int) + pagesz - 1) & -pagesz;
 	alignment = ctxsize;
 	/* The region, segment and page table we need fit in one page */
 	size = ctxsize + pagesz;
 	if (uvm_pglistalloc(size, vm_first_phys, vm_first_phys+vm_num_phys,
 			    alignment, 0, &mlist, 1, 0) != 0)
 		panic("pmap_alloc_cpu: no memory");
 	pa = VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist));
 	/* Allocate virtual memory */
 	va = uvm_km_alloc(kernel_map, size, 0, UVM_KMF_VAONLY);
 	if (va == 0)
 		panic("pmap_alloc_cpu: no memory");
 	/*
 	 * Layout the page tables in our chunk of memory
 	 */
 	ctxtable = (u_int *)va;
 	regtable = (u_int *)(va + ctxsize);
 	segtable = regtable + SRMMU_L1SIZE;
 	pagtable = segtable + SRMMU_L2SIZE;
 	ctxtable_pa = (u_int *)pa;
 	regtable_pa = (u_int *)(pa + ctxsize);
 	segtable_pa = regtable_pa + SRMMU_L1SIZE;
 	pagtable_pa = segtable_pa + SRMMU_L2SIZE;
 	/* Map the pages */
 	while (size != 0) {
 		pmap_kenter_pa(va, pa | (cachebit ? 0 : PMAP_NC),
 		    VM_PROT_READ | VM_PROT_WRITE);
 		va += pagesz;
 		pa += pagesz;
 		size -= pagesz;
+	}
 	pmap_update(pmap_kernel());
 	/*
 	 * Store the region table pointer (and its corresponding physical
 	 * address) in the CPU's slot in the kernel pmap region table
 	 * pointer table.
 	 */
 	pmap_kernel()->pm_reg_ptps[sc->ci_cpuid] = regtable;
 	pmap_kernel()->pm_reg_ptps_pa[sc->ci_cpuid] = (paddr_t)regtable_pa;
 	vr = VA_VREG(CPUINFO_VA);
 	vs = VA_VSEG(CPUINFO_VA);
 	vpg = VA_VPG(CPUINFO_VA);
 	rp = &pmap_kernel()->pm_regmap[vr];
 	sp = &rp->rg_segmap[vs];
 	/*
 	 * Copy page tables from CPU #0, then modify entry for CPUINFO_VA
 	 * so that it points at the per-CPU pages.
 	 */
 	qcopy(pmap_kernel()->pm_reg_ptps[0], regtable,
 		SRMMU_L1SIZE * sizeof(int));
 	qcopy(rp->rg_seg_ptps, segtable, SRMMU_L2SIZE * sizeof(int));
 	qcopy(sp->sg_pte, pagtable, SRMMU_L3SIZE * sizeof(int));
 	setpgt4m(&ctxtable[0],
 		 ((u_long)regtable_pa >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD);
 	setpgt4m(&regtable[vr],
 		 ((u_long)segtable_pa >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD);
 	setpgt4m(&segtable[vs],
 		 ((u_long)pagtable_pa >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD);
 	setpgt4m(&pagtable[vpg],
 		(VA2PA((void *)sc) >> SRMMU_PPNPASHIFT) |
 		(SRMMU_TEPTE | PPROT_N_RWX | SRMMU_PG_C));
 	/* Install this CPU's context table */
 	sc->ctx_tbl = ctxtable;
 	sc->ctx_tbl_pa = (paddr_t)ctxtable_pa;
 	/* Pre-compute this CPU's vpage[] PTEs */
 	for (i = 0; i < 2; i++) {
 		rp = &pmap_kernel()->pm_regmap[VA_VREG(sc->vpage[i])];
 		sp = &rp->rg_segmap[VA_VSEG(sc->vpage[i])];
 		sc->vpage_pte[i] = &sp->sg_pte[VA_SUN4M_VPG(sc->vpage[i])];
+	}
 #endif /* SUN4M || SUN4D */
+}
 #endif /* MULTIPROCESSOR */
 void
 pmap_init(void)
+{
 	u_int sz;
 	if (PAGE_SIZE != NBPG)
 		panic("pmap_init: PAGE_SIZE!=NBPG");
 	vm_num_phys = vm_last_phys - vm_first_phys;
 	/* Setup a pool for additional pvlist structures */
 	pool_init(&pv_pool, sizeof(struct pvlist), 0, 0, 0, "pvtable", NULL,
 	    IPL_NONE);
 	/*
 	 * Setup a pool for pmap structures.
 	 * The pool size includes space for an array of per-CPU
 	 * region table pointers & physical addresses
 	 */
 	sz = ALIGN(sizeof(struct pmap)) +
 	     ALIGN(NUREG * sizeof(struct regmap)) +
 	     sparc_ncpus * sizeof(int *) +	/* pm_reg_ptps */
 	     sparc_ncpus * sizeof(int);		/* pm_reg_ptps_pa */
 	pool_cache_bootstrap(&pmap_cache, sz, 0, 0, 0, "pmappl", NULL,
 	    IPL_NONE, pmap_pmap_pool_ctor, pmap_pmap_pool_dtor, NULL);
 	sz = NSEGRG * sizeof (struct segmap);
 	pool_init(&segmap_pool, sz, 0, 0, 0, "segmap", NULL, IPL_NONE);
 #if defined(SUN4M) || defined(SUN4D)
 	if (CPU_HAS_SRMMU) {
 		/*
 		 * The SRMMU only ever needs chunks in one of two sizes:
 		 * 1024 (for region level tables) and 256 (for segment
 		 * and page level tables).
 		 */
 		sz = SRMMU_L1SIZE * sizeof(int);
 		pool_init(&L1_pool, sz, sz, 0, 0, "L1 pagetable",
 			  &pgt_page_allocator, IPL_NONE);
 		sz = SRMMU_L2SIZE * sizeof(int);
 		pool_init(&L23_pool, sz, sz, 0, 0, "L2/L3 pagetable",
 			  &pgt_page_allocator, IPL_NONE);
+	}
 #endif /* SUN4M || SUN4D */
 #if defined(SUN4) || defined(SUN4C)
 	if (CPU_HAS_SUNMMU) {
 		sz = NPTESG * sizeof(int);
 		pool_init(&pte_pool, sz, 0, 0, 0, "ptemap", NULL,
 		    IPL_NONE);
+	}
 #endif /* SUN4 || SUN4C */
+}
 /*
  * Map physical addresses into kernel VM.
  */
 vaddr_t
 pmap_map(vaddr_t va, paddr_t pa, paddr_t endpa, int prot)
+{
 	int pgsize = PAGE_SIZE;
 	while (pa < endpa) {
 		pmap_kenter_pa(va, pa, prot);
 		va += pgsize;
 		pa += pgsize;
+	}
 	pmap_update(pmap_kernel());
 	return (va);
+}
 #ifdef DEBUG
 /*
  * Check a pmap for spuriously lingering mappings
  */
 static inline void
 pmap_quiet_check(struct pmap *pm)
+{
 	int vs, vr;
 	if (CPU_HAS_SUNMMU) {
 #if defined(SUN4_MMU3L)
 		if (TAILQ_FIRST(&pm->pm_reglist))
 			panic("pmap_destroy: region list not empty");
 #endif
 		if (TAILQ_FIRST(&pm->pm_seglist))
 			panic("pmap_destroy: segment list not empty");
+	}
 	for (vr = 0; vr < NUREG; vr++) {
 		struct regmap *rp = &pm->pm_regmap[vr];
 		if (HASSUN4_MMU3L) {
 			if (rp->rg_smeg != reginval)
 				printf("pmap_chk: spurious smeg in "
 				       "user region %d\n", vr);
+		}
 		if (CPU_HAS_SRMMU) {
 			int n;
 #if defined(MULTIPROCESSOR)
 			for (n = 0; n < sparc_ncpus; n++)
 #else
 			n = 0;
 #endif
+			{
 				if (pm->pm_reg_ptps[n][vr] != SRMMU_TEINVALID)
 					printf("pmap_chk: spurious PTP in user "
 						"region %d on CPU %d\n", vr, n);
+			}
+		}
 		if (rp->rg_nsegmap != 0)
 			printf("pmap_chk: %d segments remain in "
 				"region %d\n", rp->rg_nsegmap, vr);
 		if (rp->rg_segmap != NULL) {
 			printf("pmap_chk: segments still "
 				"allocated in region %d\n", vr);
 			for (vs = 0; vs < NSEGRG; vs++) {
 				struct segmap *sp = &rp->rg_segmap[vs];
 				if (sp->sg_npte != 0)
 					printf("pmap_chk: %d ptes "
 					     "remain in segment %d\n",
 						sp->sg_npte, vs);
 				if (sp->sg_pte != NULL) {
 					printf("pmap_chk: ptes still "
 					     "allocated in segment %d\n", vs);
+				}
 				if (CPU_HAS_SUNMMU) {
 					if (sp->sg_pmeg != seginval)
 						printf("pmap_chk: pm %p(%d,%d) "
 						  "spurious soft pmeg %d\n",
 						  pm, vr, vs, sp->sg_pmeg);
+				}
+			}
+		}
 		/* Check for spurious pmeg entries in the MMU */
 		if (pm->pm_ctx == NULL)
 			continue;
 		if (CPU_HAS_SUNMMU) {
 			int ctx;
 			if (mmu_has_hole && (vr >= 32 || vr < (256 - 32)))
 				continue;
 			ctx = getcontext4();
 			setcontext4(pm->pm_ctxnum);
 			for (vs = 0; vs < NSEGRG; vs++) {
 				vaddr_t va = VSTOVA(vr,vs);
 				int pmeg = getsegmap(va);
 				if (pmeg != seginval)
 					printf("pmap_chk: pm %p(%d,%d:%x): "
 						"spurious pmeg %d\n",
 						pm, vr, vs, (u_int)va, pmeg);
+			}
 			setcontext4(ctx);
+		}
+	}
 	if (pm->pm_stats.resident_count) {
 		printf("pmap_chk: res count %ld\n",
 		       pm->pm_stats.resident_count);
+	}
 	if (pm->pm_stats.wired_count) {
 		printf("pmap_chk: wired count %ld\n",
 		       pm->pm_stats.wired_count);
+	}
+}
 #endif /* DEBUG */
 int
 pmap_pmap_pool_ctor(void *arg, void *object, int flags)
+{
 	struct pmap *pm = object;
 	u_long addr;
 	memset(pm, 0, sizeof *pm);
 	/*
 	 * `pmap_pool' entries include space for the per-CPU
 	 * region table pointer arrays.
 	 */
 	addr = (u_long)pm + ALIGN(sizeof(struct pmap));
 	pm->pm_regmap = (void *)addr;
 	addr += ALIGN(NUREG * sizeof(struct regmap));
 	pm->pm_reg_ptps = (int **)addr;
 	addr += sparc_ncpus * sizeof(int *);
 	pm->pm_reg_ptps_pa = (int *)addr;
 	qzero((void *)pm->pm_regmap, NUREG * sizeof(struct regmap));
 	/* pm->pm_ctx = NULL; // already done */
 	if (CPU_HAS_SUNMMU) {
 		TAILQ_INIT(&pm->pm_seglist);
 #if defined(SUN4_MMU3L)
 		TAILQ_INIT(&pm->pm_reglist);
 		if (HASSUN4_MMU3L) {
 			int i;
 			for (i = NUREG; --i >= 0;)
 				pm->pm_regmap[i].rg_smeg = reginval;
+		}
 #endif
+	}
 #if defined(SUN4M) || defined(SUN4D)
 	else {
 		int i, n;
 		/*
 		 * We must allocate and initialize hardware-readable (MMU)
 		 * pagetables. We must also map the kernel regions into this
 		 * pmap's pagetables, so that we can access the kernel from
 		 * this user context.
 		 */
 #if defined(MULTIPROCESSOR)
 		for (n = 0; n < sparc_ncpus; n++)
 #else
 		n = 0;
 #endif
+		{
 			int *upt, *kpt;
 			upt = pool_get(&L1_pool, flags);
 			pm->pm_reg_ptps[n] = upt;
 			pm->pm_reg_ptps_pa[n] = VA2PA((char *)upt);
 			/* Invalidate user space regions */
 			for (i = 0; i < NUREG; i++)
 				setpgt4m(upt++, SRMMU_TEINVALID);
 			/* Copy kernel regions */
 			kpt = &pmap_kernel()->pm_reg_ptps[n][VA_VREG(KERNBASE)];
 			for (i = 0; i < NKREG; i++)
 				setpgt4m(upt++, kpt[i]);
+		}
+	}
 #endif /* SUN4M || SUN4D */
 	/* XXX - a peculiar place to do this, but we can't do it in pmap_init
 	 * and here at least it's off the beaten code track.
 	 */
 {static int x; if (x == 0) pool_setlowat(&pv_pool, 512), x = 1; }
 	return (0);
+}
 void
 pmap_pmap_pool_dtor(void *arg, void *object)
+{
 	struct pmap *pm = object;
 	union ctxinfo *c;
 	int s = splvm();	/* paranoia */
 #ifdef DEBUG
 	if (pmapdebug & PDB_DESTROY)
 		printf("pmap_pmap_pool_dtor(%p)\n", pm);
 #endif
 	if ((c = pm->pm_ctx) != NULL) {
 		ctx_free(pm);
+	}
 #if defined(SUN4M) || defined(SUN4D)
 	if (CPU_HAS_SRMMU) {
 		int n;
 #if defined(MULTIPROCESSOR)
 		for (n = 0; n < sparc_ncpus; n++)
 #else
 		n = 0;
 #endif
+		{
 			int *pt = pm->pm_reg_ptps[n];
 			pm->pm_reg_ptps[n] = NULL;
 			pm->pm_reg_ptps_pa[n] = 0;
 			pool_put(&L1_pool, pt);
+		}
+	}
 #endif /* SUN4M || SUN4D */
 	splx(s);
+}
 /*
  * Create and return a physical map.
  */
 struct pmap *
 pmap_create(void)
+{
 	struct pmap *pm;
 	pm = pool_cache_get(&pmap_cache, PR_WAITOK);
 	/*
 	 * Reset fields that are not preserved in the pmap cache pool.
 	 */
 	pm->pm_refcount = 1;
 #if defined(MULTIPROCESSOR)
 	/* reset active CPU set */
 	pm->pm_cpuset = 0;
 #endif
 	if (CPU_HAS_SUNMMU) {
 		/* reset the region gap */
 		pm->pm_gap_start = 0;
 		pm->pm_gap_end = VA_VREG(VM_MAXUSER_ADDRESS);
+	}
 #ifdef DEBUG
 	if (pmapdebug & PDB_CREATE)
 		printf("pmap_create[%d]: created %p\n", cpu_number(), pm);
 	pmap_quiet_check(pm);
 #endif
 	return (pm);
+}
 /*
  * Retire the given pmap from service.
  * Should only be called if the map contains no valid mappings.
  */
 void
 pmap_destroy(struct pmap *pm)
+{
 #ifdef DEBUG
 	if (pmapdebug & PDB_DESTROY)
 		printf("pmap_destroy[%d](%p)\n", cpu_number(), pm);
 #endif
 	if (atomic_dec_uint_nv(&pm->pm_refcount) == 0) {
 #ifdef DEBUG
 		pmap_quiet_check(pm);
 #endif
 		pool_cache_put(&pmap_cache, pm);
+	}
+}
 /*
  * Add a reference to the given pmap.
  */
 void
 pmap_reference(struct pmap *pm)
+{
 	atomic_inc_uint(&pm->pm_refcount);
+}
 #if defined(SUN4) || defined(SUN4C)
 /*
  * helper to deallocate level 2 & 3 page tables.
  */
 static void
 pgt_lvl23_remove4_4c(struct pmap *pm, struct regmap *rp, struct segmap *sp,
 		     int vr, int vs)
+{
 	vaddr_t va, tva;
 	int i, pmeg;
 	va = VSTOVA(vr,vs);
 	if ((pmeg = sp->sg_pmeg) != seginval) {
 		if (CTX_USABLE(pm,rp)) {
 			setcontext4(pm->pm_ctxnum);
 			setsegmap(va, seginval);
 		} else {
 			/* no context, use context 0 */
 			setcontext4(0);
 			if (HASSUN4_MMU3L && rp->rg_smeg != reginval) {
 				setregmap(0, rp->rg_smeg);
 				tva = vs << SGSHIFT;
 				setsegmap(tva, seginval);
+			}
+		}
 		if (!HASSUN4_MMU3L) {
 			if (pm == pmap_kernel()) {
 				/* Unmap segment from all contexts */
 				for (i = ncontext; --i >= 0;) {
 					setcontext4(i);
 					setsegmap(va, seginval);
+				}
+			}
+		}
 		me_free(pm, pmeg);
 		sp->sg_pmeg = seginval;
+	}
 	/* Free software tables for non-kernel maps */
 	if (pm != pmap_kernel()) {
 		pool_put(&pte_pool, sp->sg_pte);
 		sp->sg_pte = NULL;
+	}
 	if (rp->rg_nsegmap <= 0)
 		panic("pgt_rm: pm %p: nsegmap = %d\n", pm, rp->rg_nsegmap);
 	if (--rp->rg_nsegmap == 0) {
 #if defined(SUN4_MMU3L)
 		if (HASSUN4_MMU3L) {
 			if (rp->rg_smeg != reginval) {
 				if (pm == pmap_kernel()) {
 					/* Unmap from all contexts */
 					for (i = ncontext; --i >= 0;) {
 						setcontext4(i);
 						setregmap(va, reginval);
+					}
 				} else if (pm->pm_ctx) {
 					setcontext4(pm->pm_ctxnum);
 					setregmap(va, reginval);
+				}
 				/* Release MMU resource */
 				region_free(pm, rp->rg_smeg);
 				rp->rg_smeg = reginval;
+			}
+		}
 #endif /* SUN4_MMU3L */
 		/* Free software tables for non-kernel maps */
 		if (pm != pmap_kernel()) {
 			GAP_WIDEN(pm,vr);
 			pool_put(&segmap_pool, rp->rg_segmap);
 			rp->rg_segmap = NULL;
+		}
+	}
+}
 #endif /* SUN4 || SUN4C */
 #if defined(SUN4M) || defined(SUN4D)
 /*
  * SRMMU helper to deallocate level 2 & 3 page tables.
  */
 static void
 pgt_lvl23_remove4m(struct pmap *pm, struct regmap *rp, struct segmap *sp,
     int vr, int vs)
+{
 	/* Invalidate level 2 PTP entry */
 	if (pm->pm_ctx)
 		tlb_flush_segment(VSTOVA(vr,vs), pm->pm_ctxnum,
 				  PMAP_CPUSET(pm));
 	setpgt4m(&rp->rg_seg_ptps[vs], SRMMU_TEINVALID);
 	pool_put(&L23_pool, sp->sg_pte);
 	sp->sg_pte = NULL;
 	/* If region is now empty, remove level 2 pagetable as well */
 	if (--rp->rg_nsegmap == 0) {
 		int n = 0;
 		if (pm->pm_ctx)
 			tlb_flush_region(VRTOVA(vr), pm->pm_ctxnum,
 					 PMAP_CPUSET(pm));
 #ifdef MULTIPROCESSOR
 		/* Invalidate level 1 PTP entries on all CPUs */
 		for (; n < sparc_ncpus; n++) {
 			if ((cpus[n]->flags & CPUFLG_HATCHED) == 0)
 				continue;
 #endif
 			setpgt4m(&pm->pm_reg_ptps[n][vr], SRMMU_TEINVALID);
 #ifdef MULTIPROCESSOR
+		}
 #endif
 		pool_put(&segmap_pool, rp->rg_segmap);
 		rp->rg_segmap = NULL;
 		pool_put(&L23_pool, rp->rg_seg_ptps);
+	}
+}
 #endif /* SUN4M || SUN4D */
 void
 pmap_remove_all(struct pmap *pm)
+{
 	if (pm->pm_ctx == NULL)
 		return;
 #if defined(SUN4) || defined(SUN4C)
 	if (CPU_HAS_SUNMMU) {
 		int ctx = getcontext4();
 		setcontext4(pm->pm_ctxnum);
 		cache_flush_context(pm->pm_ctxnum);
 		setcontext4(ctx);
+	}
 #endif
 #if defined(SUN4M) || defined(SUN4D)
 	if (CPU_HAS_SRMMU) {
 		cache_flush_context(pm->pm_ctxnum);
+	}
 #endif
 	pm->pm_flags |= PMAP_USERCACHECLEAN;
+}
 /*
  * Remove the given range of mapping entries.
  * The starting and ending addresses are already rounded to pages.
  * Sheer lunacy: pmap_remove is often asked to remove nonexistent
  * mappings.
  */
 void
 pmap_remove(struct pmap *pm, vaddr_t va, vaddr_t endva)
+{
 	vaddr_t nva;
 	int vr, vs, s, ctx;
 	void (*rm)(struct pmap *, vaddr_t, vaddr_t, int, int);
 #ifdef DEBUG
 	if (pmapdebug & PDB_REMOVE)
 		printf("pmap_remove[%d](%p, 0x%lx, 0x%lx)\n",
 			cpu_number(), pm, va, endva);
 #endif
 	if (!CPU_HAS_SRMMU)
 		write_user_windows();
 	if (pm == pmap_kernel()) {
 		/*
 		 * Removing from kernel address space.
 		 */
 		rm = pmap_rmk;
 	} else {
 		/*
 		 * Removing from user address space.
 		 */
 		rm = pmap_rmu;
+	}
 	ctx = getcontext();
 	s = splvm();		/* XXX conservative */
 	PMAP_LOCK();
 	for (; va < endva; va = nva) {
 		/* do one virtual segment at a time */
 		vr = VA_VREG(va);
 		vs = VA_VSEG(va);
 		nva = VSTOVA(vr, vs + 1);
 		if (nva == 0 || nva > endva)
 			nva = endva;
 		if (pm->pm_regmap[vr].rg_nsegmap != 0)
 			(*rm)(pm, va, nva, vr, vs);
+	}
 	PMAP_UNLOCK();
 	splx(s);
 	setcontext(ctx);
+}
 /*
  * It is the same amount of work to cache_flush_page 16 pages
  * as to cache_flush_segment 1 segment, assuming a 64K cache size
  * and a 4K page size or a 128K cache size and 8K page size.
  */
 #define	PMAP_SFL_THRESHOLD	16	/* if > magic, use cache_flush_segment */
 /*
  * Remove a range contained within a single segment.
  * These are egregiously complicated routines.
  */
 #if defined(SUN4) || defined(SUN4C)
 /* remove from kernel */
 /*static*/ void
 pmap_rmk4_4c(struct pmap *pm, vaddr_t va, vaddr_t endva, int vr, int vs)
+{
 	int pte, mmupte, *ptep, perpage, npg;
 	struct vm_page *pg;
 	int nleft, pmeg, inmmu;
 	struct regmap *rp;
 	struct segmap *sp;
 	rp = &pm->pm_regmap[vr];
 	sp = &rp->rg_segmap[vs];
 	if (rp->rg_nsegmap == 0)
 		return;
 	if ((nleft = sp->sg_npte) == 0)
 		return;
 	pmeg = sp->sg_pmeg;
 	inmmu = pmeg != seginval;
 	ptep = &sp->sg_pte[VA_VPG(va)];
 	/* decide how to flush cache */
 	npg = (endva - va) >> PGSHIFT;
 	if (!inmmu) {
 		perpage = 0;
 	} else if (npg > PMAP_SFL_THRESHOLD) {
 		/* flush the whole segment */
 		perpage = 0;
 		cache_flush_segment(vr, vs, 0);
 	} else {
 		/* flush each page individually; some never need flushing */
 		perpage = (CACHEINFO.c_vactype != VAC_NONE);
+	}
 	for (; va < endva; va += NBPG, ptep++) {
 		pte = *ptep;
 		mmupte = inmmu ? getpte4(va) : 0;
 		if ((pte & PG_V) == 0) {
 #ifdef DIAGNOSTIC
 			if (inmmu && (mmupte & PG_V) != 0)
 				printf("rmk: inconsistent ptes va=%lx\n", va);
 #endif
 			continue;
+		}
 		if ((pte & PG_TYPE) == PG_OBMEM) {
 			/* if cacheable, flush page as needed */
 			if (perpage && (mmupte & PG_NC) == 0)
 				cache_flush_page(va, 0);
 			if ((pg = pvhead4_4c(pte)) != NULL) {
 				if (inmmu)
 					VM_MDPAGE_PVHEAD(pg)->pv_flags |= MR4_4C(mmupte);
 				pv_unlink4_4c(pg, pm, va);
+			}
+		}
 		nleft--;
 #ifdef DIAGNOSTIC
 		if (nleft < 0)
 			panic("pmap_rmk: too many PTEs in segment; "
 			      "va 0x%lx; endva 0x%lx", va, endva);
 #endif
 		if (pte & PG_WIRED) {
 			sp->sg_nwired--;
 			pm->pm_stats.wired_count--;
+		}
 		if (inmmu)
 			setpte4(va, 0);
 		*ptep = 0;
 		pm->pm_stats.resident_count--;
+	}
 #ifdef DIAGNOSTIC
 	if (sp->sg_nwired > nleft || sp->sg_nwired < 0)
 		panic("pmap_rmk: pm %p, va %lx: nleft=%d, nwired=%d",
 			pm, va, nleft, sp->sg_nwired);
 #endif
 	if ((sp->sg_npte = nleft) == 0)
 		pgt_lvl23_remove4_4c(pm, rp, sp, vr, vs);
 	else if (sp->sg_nwired == 0) {
 		if (sp->sg_pmeg != seginval)
 			mmu_pmeg_unlock(sp->sg_pmeg);
+	}
+}
 #endif /* SUN4 || SUN4C */
 #if defined(SUN4M) || defined(SUN4D)	/* SRMMU version of pmap_rmk */
 /* remove from kernel (4m)*/
 /* pm is already locked */
 /*static*/ void
 pmap_rmk4m(struct pmap *pm, vaddr_t va, vaddr_t endva, int vr, int vs)
+{
 	int tpte, perpage, npg;
 	struct vm_page *pg;
 	struct regmap *rp;
 	struct segmap *sp;
 	rp = &pm->pm_regmap[vr];
 	sp = &rp->rg_segmap[vs];
 	if (rp->rg_nsegmap == 0)
 		return;
 	/* decide how to flush cache */
 	npg = (endva - va) >> PGSHIFT;
 	if (npg > PMAP_SFL_THRESHOLD) {
 		/* flush the whole segment */
 		perpage = 0;
 		if (CACHEINFO.c_vactype != VAC_NONE)
 			cache_flush_segment(vr, vs, 0);
 	} else {
 		/* flush each page individually; some never need flushing */
 		perpage = (CACHEINFO.c_vactype != VAC_NONE);
+	}
 	while (va < endva) {
 		tpte = sp->sg_pte[VA_SUN4M_VPG(va)];
 		if ((tpte & SRMMU_TETYPE) != SRMMU_TEPTE) {
 #ifdef DEBUG
 			if ((pmapdebug & PDB_SANITYCHK) &&
 			    (getpte4m(va) & SRMMU_TETYPE) == SRMMU_TEPTE)
 				panic("pmap_rmk: Spurious kTLB entry for 0x%lx",
 				      va);
 #endif
 			va += NBPG;
 			continue;
+		}
 		if ((tpte & SRMMU_PGTYPE) == PG_SUN4M_OBMEM) {
 			/* if cacheable, flush page as needed */
 			if (perpage && (tpte & SRMMU_PG_C))
 				cache_flush_page(va, 0);
 			if ((pg = pvhead4m(tpte)) != NULL) {
 				VM_MDPAGE_PVHEAD(pg)->pv_flags |= MR4M(tpte);
 				pv_unlink4m(pg, pm, va);
+			}
+		}
 		setpgt4m_va(va, &sp->sg_pte[VA_SUN4M_VPG(va)],
 		    SRMMU_TEINVALID, 1, 0, CPUSET_ALL);
 		pm->pm_stats.resident_count--;
 		va += NBPG;
+	}
+}
 #endif /* SUN4M || SUN4D */
 #if defined(SUN4) || defined(SUN4C)
 /* remove from user */
 /*static*/ void
 pmap_rmu4_4c(struct pmap *pm, vaddr_t va, vaddr_t endva, int vr, int vs)
+{
 	int *ptep, pteva, pte, perpage, npg;
 	struct vm_page *pg;
 	int nleft, pmeg, inmmu;
 	struct regmap *rp;
 	struct segmap *sp;
 	rp = &pm->pm_regmap[vr];
 	if (rp->rg_nsegmap == 0)
 		return;
 	sp = &rp->rg_segmap[vs];
 	if ((nleft = sp->sg_npte) == 0)
 		return;
 	pmeg = sp->sg_pmeg;
 	inmmu = pmeg != seginval;
 	/*
 	 * PTEs are in MMU.  Invalidate in hardware, update ref &
 	 * mod bits, and flush cache if required.
 	 */
 	if (!inmmu) {
 		perpage = 0;
 		pteva = 0;
 	} else if (CTX_USABLE(pm,rp)) {
 		/* process has a context, must flush cache */
 		npg = (endva - va) >> PGSHIFT;
 		setcontext4(pm->pm_ctxnum);
 		if ((pm->pm_flags & PMAP_USERCACHECLEAN) != 0)
 			perpage = 0;
 		else if (npg > PMAP_SFL_THRESHOLD) {
 			perpage = 0; /* flush the whole segment */
 			cache_flush_segment(vr, vs, pm->pm_ctxnum);
 		} else
 			perpage = (CACHEINFO.c_vactype != VAC_NONE);
 		pteva = va;
 	} else {
 		/* no context, use context 0; cache flush unnecessary */
 		setcontext4(0);
 		if (HASSUN4_MMU3L)
 			setregmap(0, tregion);
 		/* XXX use per-CPU pteva? */
 		setsegmap(0, pmeg);
 		pteva = VA_VPG(va) << PGSHIFT;
 		perpage = 0;
+	}
 	ptep = sp->sg_pte + VA_VPG(va);
 	for (; va < endva; ptep++, pteva += NBPG, va += NBPG) {
 		int mmupte;
 		pte = *ptep;
 		mmupte = inmmu ? getpte4(pteva) : 0;
 		if ((pte & PG_V) == 0) {
 #ifdef DIAGNOSTIC
 			if (inmmu && (mmupte & PG_V) != 0)
 				printf("pmap_rmu: pte=%x, mmupte=%x\n",
 					pte, getpte4(pteva));
 #endif
 			continue;
+		}
 		if ((pte & PG_TYPE) == PG_OBMEM) {
 			/* if cacheable, flush page as needed */
 			if (perpage && (mmupte & PG_NC) == 0)
 				cache_flush_page(va, pm->pm_ctxnum);
 			if ((pg = pvhead4_4c(pte)) != NULL) {
 				if (inmmu)
 					VM_MDPAGE_PVHEAD(pg)->pv_flags |= MR4_4C(mmupte);
 				pv_unlink4_4c(pg, pm, va);
+			}
+		}
 		nleft--;
 #ifdef DIAGNOSTIC
 		if (nleft < 0)
 			panic("pmap_rmu: too many PTEs in segment; "
 			     "va 0x%lx; endva 0x%lx", va, endva);
 #endif
 		if (inmmu)
 			setpte4(pteva, 0);
 		if (pte & PG_WIRED) {
 			sp->sg_nwired--;
 			pm->pm_stats.wired_count--;
+		}
 		*ptep = 0;
 		pm->pm_stats.resident_count--;
+	}
 #ifdef DIAGNOSTIC
 	if (sp->sg_nwired > nleft || sp->sg_nwired < 0)
 		panic("pmap_rmu: pm %p, va %lx: nleft=%d, nwired=%d",
 			pm, va, nleft, sp->sg_nwired);
 #endif
 	if ((sp->sg_npte = nleft) == 0)
 		pgt_lvl23_remove4_4c(pm, rp, sp, vr, vs);
 	else if (sp->sg_nwired == 0) {
 		if (sp->sg_pmeg != seginval)
 			mmu_pmeg_unlock(sp->sg_pmeg);
+	}
+}
 #endif /* SUN4 || SUN4C */
 #if defined(SUN4M) || defined(SUN4D)	/* SRMMU version of pmap_rmu */
 /* remove from user */
 /* Note: pm is already locked */
 /*static*/ void
 pmap_rmu4m(struct pmap *pm, vaddr_t va, vaddr_t endva, int vr, int vs)
+{
 	int *pte0, perpage, npg;
 	struct vm_page *pg;
 	int nleft;
 	struct regmap *rp;
 	struct segmap *sp;
 	rp = &pm->pm_regmap[vr];
 	if (rp->rg_nsegmap == 0)
 		return;
 	sp = &rp->rg_segmap[vs];
 	if ((nleft = sp->sg_npte) == 0)
 		return;
 	pte0 = sp->sg_pte;
 	/*
 	 * Invalidate PTE in MMU pagetables. Flush cache if necessary.
 	 */
 	if (pm->pm_ctx && (pm->pm_flags & PMAP_USERCACHECLEAN) == 0) {
 		/* process has a context, must flush cache */
 		if (CACHEINFO.c_vactype != VAC_NONE) {
 			npg = (endva - va) >> PGSHIFT;
 			if (npg > PMAP_SFL_THRESHOLD) {
 				perpage = 0; /* flush the whole segment */

 @@ -1,483 +1,481 @@
-/*	$NetBSD: cpuvar.h,v 1.77 2009/05/18 01:36:11 mrg Exp $ */
+/*	$NetBSD: cpuvar.h,v 1.78 2009/05/27 02:19:49 mrg Exp $ */
 /*
  *  Copyright (c) 1996 The NetBSD Foundation, Inc.
  *  All rights reserved.
+ *
  *  This code is derived from software contributed to The NetBSD Foundation
  *  by Paul Kranenburg.
+ *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions
  *  are met:
  *  1. Redistributions of source code must retain the above copyright
  *     notice, this list of conditions and the following disclaimer.
  *  2. Redistributions in binary form must reproduce the above copyright
  *     notice, this list of conditions and the following disclaimer in the
  *     documentation and/or other materials provided with the distribution.
+ *
  *  THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  *  ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  *  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  *  PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  *  BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  *  POSSIBILITY OF SUCH DAMAGE.
  */
 #ifndef _sparc_cpuvar_h
 #define _sparc_cpuvar_h
 #if defined(_KERNEL_OPT)
 #include "opt_multiprocessor.h"
 #include "opt_lockdebug.h"
 #include "opt_ddb.h"
 #include "opt_sparc_arch.h"
 #include "opt_modular.h"
 #endif
 #include <sys/device.h>
 #include <sys/lock.h>
 #include <sys/cpu_data.h>
 #include <sparc/include/reg.h>
 #include <sparc/sparc/cache.h>	/* for cacheinfo */
 /*
  * CPU/MMU module information.
  * There is one of these for each "mainline" CPU module we support.
  * The information contained in the structure is used only during
  * auto-configuration of the CPUs; some fields are copied into the
  * per-cpu data structure (cpu_info) for easy access during normal
  * operation.
  */
 struct cpu_info;
 struct module_info {
 	int  cpu_type;
 	enum vactype vactype;
 	void (*cpu_match)(struct cpu_info *, struct module_info *, int);
 	void (*getcacheinfo)(struct cpu_info *sc, int node);
 	void (*hotfix)(struct cpu_info *);
 	void (*mmu_enable)(void);
 	void (*cache_enable)(void);
 	int  (*getmid)(void);		/* Get MID of current CPU */
 	int  ncontext;			/* max. # of contexts (that we use) */
 	void (*get_syncflt)(void);
 	int  (*get_asyncflt)(u_int *, u_int *);
 	void (*cache_flush)(void *, u_int);
 	void (*sp_vcache_flush_page)(int, int);
 	void (*ft_vcache_flush_page)(int, int);
 	void (*sp_vcache_flush_segment)(int, int, int);
 	void (*ft_vcache_flush_segment)(int, int, int);
 	void (*sp_vcache_flush_region)(int, int);
 	void (*ft_vcache_flush_region)(int, int);
 	void (*sp_vcache_flush_context)(int);
 	void (*ft_vcache_flush_context)(int);
 	void (*sp_vcache_flush_range)(int, int, int);
 	void (*ft_vcache_flush_range)(int, int, int);
 	void (*pcache_flush_page)(paddr_t, int);
 	void (*pure_vcache_flush)(void);
 	void (*cache_flush_all)(void);
 	void (*memerr)(unsigned, u_int, u_int, struct trapframe *);
 	void (*zero_page)(paddr_t);
 	void (*copy_page)(paddr_t, paddr_t);
 };
 /*
  * Message structure for Inter Processor Communication in MP systems
  */
 struct xpmsg {
 	volatile int tag;
 #define	XPMSG15_PAUSECPU	1
 #define	XPMSG_FUNC		4
 #define	XPMSG_FTRP		5
 	volatile union {
 		/*
 		 * Cross call: ask to run (*func)(arg0,arg1,arg2)
 		 * or (*trap)(arg0,arg1,arg2). `trap' should be the
 		 * address of a `fast trap' handler that executes in
 		 * the trap window (see locore.s).
 		 */
 		struct xpmsg_func {
-			int	(*func)(int, int, int);
+			void	(*func)(int, int, int);
 			void	(*trap)(int, int, int);
 			int	arg0;
 			int	arg1;
 			int	arg2;
 			int	retval;
 		} xpmsg_func;
 	} u;
 	volatile int	received;
 	volatile int	complete;
 };
 /*
  * This must be locked around all message transactions to ensure only
  * one CPU is generating them.
  */
 extern struct simplelock xpmsg_lock;
 #define LOCK_XPMSG()	simple_lock(&xpmsg_lock);
 #define UNLOCK_XPMSG()	simple_unlock(&xpmsg_lock);
 /*
  * The cpuinfo structure. This structure maintains information about one
  * currently installed CPU (there may be several of these if the machine
  * supports multiple CPUs, as on some Sun4m architectures). The information
  * in this structure supersedes the old "cpumod", "mmumod", and similar
  * fields.
  */
 struct cpu_info {
 	struct cpu_data ci_data;	/* MI per-cpu data */
 	/* Scheduler flags */
 	int	ci_want_ast;
 	int	ci_want_resched;
 	/*
 	 * SPARC cpu_info structures live at two VAs: one global
 	 * VA (so each CPU can access any other CPU's cpu_info)
 	 * and an alias VA CPUINFO_VA which is the same on each
 	 * CPU and maps to that CPU's cpu_info.  Since the alias
 	 * CPUINFO_VA is how we locate our cpu_info, we have to
 	 * self-reference the global VA so that we can return it
 	 * in the curcpu() macro.
 	 */
 	struct cpu_info * volatile ci_self;
 	/* Primary Inter-processor message area */
 	struct xpmsg	msg;
 	int		ci_cpuid;	/* CPU index (see cpus[] array) */
 	/* Context administration */
 	int		*ctx_tbl;	/* [4m] SRMMU-edible context table */
 	paddr_t		ctx_tbl_pa;	/* [4m] ctx table physical address */
 	/* Cache information */
 	struct cacheinfo	cacheinfo;	/* see cache.h */
 	/* various flags to workaround anomalies in chips */
 	volatile int	flags;		/* see CPUFLG_xxx, below */
 	/* Per processor counter register (sun4m only) */
 	volatile struct counter_4m	*counterreg_4m;
 	/* Per processor interrupt mask register (sun4m only) */
 	volatile struct icr_pi	*intreg_4m;
 	/*
 	 * Send a IPI to (cpi).  For Ross cpus we need to read
 	 * the pending register to avoid a hardware bug.
 	 */
 #define raise_ipi(cpi,lvl)	do {			\
 	volatile int x;					\
 	(cpi)->intreg_4m->pi_set = PINTR_SINTRLEV(lvl);	\
 	x = (cpi)->intreg_4m->pi_pend;			\
 } while (0)
 	int		sun4_mmu3l;	/* [4]: 3-level MMU present */
 #if defined(SUN4_MMU3L)
 #define HASSUN4_MMU3L	(cpuinfo.sun4_mmu3l)
 #else
 #define HASSUN4_MMU3L	(0)
 #endif
 	int		ci_idepth;		/* Interrupt depth */
 	/*
 	 * The following pointers point to processes that are somehow
 	 * associated with this CPU--running on it, using its FPU,
 	 * etc.
 	 */
 	struct	lwp	*ci_curlwp;		/* CPU owner */
 	struct	lwp 	*fplwp;			/* FPU owner */
 	int		ci_mtx_count;
 	int		ci_mtx_oldspl;
 	/*
 	 * Idle PCB and Interrupt stack;
 	 */
 	void		*eintstack;		/* End of interrupt stack */
 #define INT_STACK_SIZE	(128 * 128)		/* 128 128-byte stack frames */
 	void		*redzone;		/* DEBUG: stack red zone */
 #define REDSIZE		(8*96)			/* some room for bouncing */
 	struct	pcb	*curpcb;		/* CPU's PCB & kernel stack */
 	/* locore defined: */
 	void	(*get_syncflt)(void);		/* Not C-callable */
 	int	(*get_asyncflt)(u_int *, u_int *);
 	/* Synchronous Fault Status; temporary storage */
 	struct {
 		int	sfsr;
 		int	sfva;
 	} syncfltdump;
 	/*
 	 * Cache handling functions.
 	 * Most cache flush function come in two flavours: one that
 	 * acts only on the CPU it executes on, and another that
 	 * uses inter-processor signals to flush the cache on
 	 * all processor modules.
 	 * The `ft_' versions are fast trap cache flush handlers.
 	 */
 	void	(*cache_flush)(void *, u_int);
 	void	(*vcache_flush_page)(int, int);
 	void	(*sp_vcache_flush_page)(int, int);
 	void	(*ft_vcache_flush_page)(int, int);
 	void	(*vcache_flush_segment)(int, int, int);
 	void	(*sp_vcache_flush_segment)(int, int, int);
 	void	(*ft_vcache_flush_segment)(int, int, int);
 	void	(*vcache_flush_region)(int, int);
 	void	(*sp_vcache_flush_region)(int, int);
 	void	(*ft_vcache_flush_region)(int, int);
 	void	(*vcache_flush_context)(int);
 	void	(*sp_vcache_flush_context)(int);
 	void	(*ft_vcache_flush_context)(int);
 	/* The are helpers for (*cache_flush)() */
 	void	(*sp_vcache_flush_range)(int, int, int);
 	void	(*ft_vcache_flush_range)(int, int, int);
 	void	(*pcache_flush_page)(paddr_t, int);
 	void	(*pure_vcache_flush)(void);
 	void	(*cache_flush_all)(void);
 	/* Support for hardware-assisted page clear/copy */
 	void	(*zero_page)(paddr_t);
 	void	(*copy_page)(paddr_t, paddr_t);
 	/* Virtual addresses for use in pmap copy_page/zero_page */
 	void *	vpage[2];
 	int	*vpage_pte[2];		/* pte location of vpage[] */
 	void	(*cache_enable)(void);
 	int	cpu_type;	/* Type: see CPUTYP_xxx below */
 	/* Inter-processor message area (high priority but used infrequently) */
 	struct xpmsg	msg_lev15;
 	/* CPU information */
 	int		node;		/* PROM node for this CPU */
 	int		mid;		/* Module ID for MP systems */
 	int		mbus;		/* 1 if CPU is on MBus */
 	int		mxcc;		/* 1 if a MBus-level MXCC is present */
 	const char	*cpu_name;	/* CPU model */
 	int		cpu_impl;	/* CPU implementation code */
 	int		cpu_vers;	/* CPU version code */
 	int		mmu_impl;	/* MMU implementation code */
 	int		mmu_vers;	/* MMU version code */
 	int		master;		/* 1 if this is bootup CPU */
 	vaddr_t		mailbox;	/* VA of CPU's mailbox */
 	int		mmu_ncontext;	/* Number of contexts supported */
 	int		mmu_nregion; 	/* Number of regions supported */
 	int		mmu_nsegment;	/* [4/4c] Segments */
 	int		mmu_npmeg;	/* [4/4c] Pmegs */
 /* XXX - we currently don't actually use the following */
 	int		arch;		/* Architecture: CPU_SUN4x */
 	int		class;		/* Class: SuperSPARC, microSPARC... */
 	int		classlvl;	/* Iteration in class: 1, 2, etc. */
 	int		classsublvl;	/* stepping in class (version) */
 	int		hz;		/* Clock speed */
 	/* FPU information */
 	int		fpupresent;	/* true if FPU is present */
 	int		fpuvers;	/* FPU revision */
 	const char	*fpu_name;	/* FPU model */
 	char		fpu_namebuf[32];/* Buffer for FPU name, if necessary */
 	/* XXX */
 	volatile void	*ci_ddb_regs;		/* DDB regs */
 	/*
 	 * The following are function pointers to do interesting CPU-dependent
 	 * things without having to do type-tests all the time
 	 */
 	/* bootup things: access to physical memory */
 	u_int	(*read_physmem)(u_int addr, int space);
 	void	(*write_physmem)(u_int addr, u_int data);
 	void	(*cache_tablewalks)(void);
 	void	(*mmu_enable)(void);
 	void	(*hotfix)(struct cpu_info *);
 #if 0
 	/* hardware-assisted block operation routines */
 	void		(*hwbcopy)(const void *from, void *to, size_t len);
 	void		(*hwbzero)(void *buf, size_t len);
 	/* routine to clear mbus-sbus buffers */
 	void		(*mbusflush)(void);
 #endif
 	/*
 	 * Memory error handler; parity errors, unhandled NMIs and other
 	 * unrecoverable faults end up here.
 	 */
 	void		(*memerr)(unsigned, u_int, u_int, struct trapframe *);
 	void		(*idlespin)(struct cpu_info *);
 	/* Module Control Registers */
 	/*bus_space_handle_t*/ long ci_mbusport;
 	/*bus_space_handle_t*/ long ci_mxccregs;
 	u_int	ci_tt;			/* Last trap (if tracing) */
 };
 /*
  * CPU architectures
  */
 #define CPUARCH_UNKNOWN		0
 #define CPUARCH_SUN4		1
 #define CPUARCH_SUN4C		2
 #define CPUARCH_SUN4M		3
 #define	CPUARCH_SUN4D		4
 #define CPUARCH_SUN4U		5
 /*
  * CPU classes
  */
 #define CPUCLS_UNKNOWN		0
 #if defined(SUN4)
 #define CPUCLS_SUN4		1
 #endif
 #if defined(SUN4C)
 #define CPUCLS_SUN4C		5
 #endif
 #if defined(SUN4M) || defined(SUN4D)
 #define CPUCLS_MICROSPARC	10	/* MicroSPARC-II */
 #define CPUCLS_SUPERSPARC	11	/* Generic SuperSPARC */
 #define CPUCLS_HYPERSPARC	12	/* Ross HyperSPARC RT620 */
 #endif
 /*
  * CPU types. Each of these should uniquely identify one platform/type of
  * system, i.e. "MBus-based 75 MHz SuperSPARC-II with ECache" is
  * CPUTYP_SS2_MBUS_MXCC. The general form is
  * 	CPUTYP_proctype_bustype_cachetype_etc_etc
+ *
  * XXX: This is far from complete/comprehensive
  * XXX: ADD SUN4, SUN4C TYPES
  */
 #define CPUTYP_UNKNOWN		0
 #define CPUTYP_4_100		1 	/* Sun4/100 */
 #define CPUTYP_4_200		2	/* Sun4/200 */
 #define CPUTYP_4_300		3	/* Sun4/300 */
 #define CPUTYP_4_400		4	/* Sun4/400 */
 #define CPUTYP_SLC		10	/* SPARCstation SLC */
 #define CPUTYP_ELC		11	/* SPARCstation ELC */
 #define CPUTYP_IPX		12	/* SPARCstation IPX */
 #define CPUTYP_IPC		13	/* SPARCstation IPC */
 #define CPUTYP_1		14	/* SPARCstation 1 */
 #define CPUTYP_1P		15	/* SPARCstation 1+ */
 #define CPUTYP_2		16	/* SPARCstation 2 */
 /* We classify the Sun4m's by feature, not by model (XXX: do same for 4/4c) */
 #define	CPUTYP_SS2_MBUS_MXCC	20 	/* SuperSPARC-II, Mbus, MXCC (SS20) */
 #define CPUTYP_SS1_MBUS_MXCC	21	/* SuperSPARC-I, Mbus, MXCC (SS10) */
 #define CPUTYP_SS2_MBUS_NOMXCC	22	/* SuperSPARC-II, on MBus w/o MXCC */
 #define CPUTYP_SS1_MBUS_NOMXCC	23	/* SuperSPARC-I, on MBus w/o MXCC */
 #define CPUTYP_MS2		24	/* MicroSPARC-2 */
 #define CPUTYP_MS1		25 	/* MicroSPARC-1 */
 #define CPUTYP_HS_MBUS		26	/* MBus-based HyperSPARC */
 #define CPUTYP_CYPRESS		27	/* MBus-based Cypress */
 /*
  * CPU flags
  */
 #define CPUFLG_CACHEPAGETABLES	0x1	/* caching pagetables OK on Sun4m */
 #define CPUFLG_CACHEIOMMUTABLES	0x2	/* caching IOMMU translations OK */
 #define CPUFLG_CACHEDVMA	0x4	/* DVMA goes through cache */
 #define CPUFLG_SUN4CACHEBUG	0x8	/* trap page can't be cached */
 #define CPUFLG_CACHE_MANDATORY	0x10	/* if cache is on, don't use
 					   uncached access */
 #define CPUFLG_HATCHED		0x1000	/* CPU is alive */
 #define CPUFLG_PAUSED		0x2000	/* CPU is paused */
 #define CPUFLG_GOTMSG		0x4000	/* CPU got an lev13 IPI */
 #define CPUFLG_READY		0x8000	/* CPU available for IPI */
 #define CPU_INFO_ITERATOR		int
-#ifdef MULTIPROCESSOR
+/*
-#define CPU_INFO_FOREACH(cii, cp)	cii = 0; cp = cpus[cii], cii < sparc_ncpus; cii++
+ * Provide two forms of CPU_INFO_FOREACH.  One fast one for non-modular
  * non-SMP kernels, and the other for everyone else.  Both work in the
  * non-SMP case, just involving an extra indirection through cpus[0] for
  * the portable version.
  */
 #if defined(MULTIPROCESSOR) || defined(MODULAR) || defined(_MODULE)
 #define	CPU_INFO_FOREACH(cii, cp)	cii = 0; (cp = cpus[cii]) && cp->eintstack && cii < sparc_ncpus; cii++
 #else
-#define	CPU_INFO_FOREACH(cii, cp)	(void)cii, cp = curcpu(); cp != NULL; cp = NULL
+#define CPU_INFO_FOREACH(cii, cp)	(void)cii, cp = curcpu(); cp != NULL; cp = NULL
 #endif
 /*
  * Useful macros.
  */
 #define CPU_NOTREADY(cpi)	((cpi) == NULL || cpuinfo.mid == (cpi)->mid || \
 				    ((cpi)->flags & CPUFLG_READY) == 0)
 /*
  * Related function prototypes
  */
 void getcpuinfo (struct cpu_info *sc, int node);
 void mmu_install_tables (struct cpu_info *);
 void pmap_alloc_cpu (struct cpu_info *);
 #define	CPUSET_ALL	0xffffffffU	/* xcall to all configured CPUs */
 #if defined(MULTIPROCESSOR)
-typedef int (*xcall_func_t)(int, int, int);
+void cpu_init_system(void);
 typedef void (*xcall_func_t)(int, int, int);
 typedef void (*xcall_trap_t)(int, int, int);
 void xcall(xcall_func_t, xcall_trap_t, int, int, int, u_int);
 /* Shorthand */
 #define XCALL0(f,cpuset)		\
 	xcall((xcall_func_t)f, NULL, 0, 0, 0, cpuset)
 #define XCALL1(f,a1,cpuset)		\
 	xcall((xcall_func_t)f, NULL, (int)a1, 0, 0, cpuset)
 #define XCALL2(f,a1,a2,cpuset)		\
 	xcall((xcall_func_t)f, NULL, (int)a1, (int)a2, 0, cpuset)
 #define XCALL3(f,a1,a2,a3,cpuset)	\
 	xcall((xcall_func_t)f, NULL, (int)a1, (int)a2, (int)a3, cpuset)
 #define FXCALL0(f,tf,cpuset)		\
 	xcall((xcall_func_t)f, (xcall_trap_t)tf, 0, 0, 0, cpuset)
 #define FXCALL1(f,tf,a1,cpuset)		\
 	xcall((xcall_func_t)f, (xcall_trap_t)tf, (int)a1, 0, 0, cpuset)
 #define FXCALL2(f,tf,a1,a2,cpuset)	\
 	xcall((xcall_func_t)f, (xcall_trap_t)tf, (int)a1, (int)a2, 0, cpuset)
 #define FXCALL3(f,tf,a1,a2,a3,cpuset)	\
 	xcall((xcall_func_t)f, (xcall_trap_t)tf, (int)a1, (int)a2, (int)a3, cpuset)
 #else
 #define XCALL0(f,cpuset)		/**/
 #define XCALL1(f,a1,cpuset)		/**/
 #define XCALL2(f,a1,a2,cpuset)		/**/
 #define XCALL3(f,a1,a2,a3,cpuset)	/**/
 #define FXCALL0(f,tf,cpuset)		/**/
 #define FXCALL1(f,tf,a1,cpuset)		/**/
 #define FXCALL2(f,tf,a1,a2,cpuset)	/**/
 #define FXCALL3(f,tf,a1,a2,a3,cpuset)	/**/
 #endif /* MULTIPROCESSOR */
 extern int bootmid;			/* Module ID of boot CPU */
 #define CPU_MID2CPUNO(mid)		((mid) != 0 ? (mid) - 8 : 0)
 #ifdef MULTIPROCESSOR
 extern struct cpu_info *cpus[];
 #ifdef MULTIPROCESSOR
 extern u_int cpu_ready_mask;		/* the set of CPUs marked as READY */
 #endif
 #define cpuinfo	(*(struct cpu_info *)CPUINFO_VA)
 #endif	/* _sparc_cpuvar_h */