 @@ -1,14 +1,14 @@
-/*	$NetBSD: rtl8169.c,v 1.105.4.7 2009/05/01 02:11:15 snj Exp $	*/
+/*	$NetBSD: rtl8169.c,v 1.105.4.8 2009/06/19 21:51:43 snj Exp $	*/
 /*
  * Copyright (c) 1997, 1998-2003
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -23,27 +23,27 @@
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.105.4.7 2009/05/01 02:11:15 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.105.4.8 2009/06/19 21:51:43 snj Exp $");
 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */
 /*
  * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
+ *
  * Written by Bill Paul <wpaul@windriver.com>
  * Senior Networking Software Engineer
  * Wind River Systems
  */
 /*
  * This driver is designed to support RealTek's next generation of
  * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
 @@ -557,94 +557,79 @@ re_diag(struct rtk_softc *sc)
 void
 re_attach(struct rtk_softc *sc)
+{
 	uint8_t eaddr[ETHER_ADDR_LEN];
 	uint16_t val;
 	struct ifnet *ifp;
 	int error = 0, i, addr_len;
 	if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
 		uint32_t hwrev;
 		/* Revision of 8169/8169S/8110s in bits 30..26, 23 */
 		hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV;
 		/* These rev numbers are taken from Realtek's driver */
 		switch (hwrev) {
 		case RTK_HWREV_8169:
 			/* XXX not in the Realtek driver */
 			sc->sc_rev = 1;
 			sc->sc_quirk |= RTKQ_8169NONS;
 			break;
 		case RTK_HWREV_8169S:
 		case RTK_HWREV_8110S:
 			sc->sc_rev = 3;
 			sc->sc_quirk |= RTKQ_MACLDPS;
 			break;
 		case RTK_HWREV_8169_8110SB:
 			sc->sc_rev = 4;
 			sc->sc_quirk |= RTKQ_MACLDPS;
 			break;
 		case RTK_HWREV_8169_8110SC:
 			sc->sc_rev = 5;
 			sc->sc_quirk |= RTKQ_MACLDPS;
 			break;
 		case RTK_HWREV_8101E:
 			sc->sc_rev = 11;
 			sc->sc_quirk |= RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8168_SPIN1:
 			sc->sc_rev = 21;
 			break;
 		case RTK_HWREV_8168_SPIN2:
 			sc->sc_rev = 22;
 			break;
 		case RTK_HWREV_8168_SPIN3:
-			sc->sc_rev = 23;
+			sc->sc_quirk |= RTKQ_MACSTAT;
 			break;
 		case RTK_HWREV_8168C:
 		case RTK_HWREV_8168C_SPIN2:
-			sc->sc_rev = 24;
+		case RTK_HWREV_8168CP:
-			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD;
+		case RTK_HWREV_8168D:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP;
 			/*
 			 * From FreeBSD driver:
+			 *
 			 * These (8168/8111) controllers support jumbo frame
 			 * but it seems that enabling it requires touching
 			 * additional magic registers. Depending on MAC
 			 * revisions some controllers need to disable
 			 * checksum offload. So disable jumbo frame until
 			 * I have better idea what it really requires to
 			 * make it support.
 			 * RTL8168C/CP : supports up to 6KB jumbo frame.
 			 * RTL8111C/CP : supports up to 9KB jumbo frame.
 			 */
 			sc->sc_quirk |= RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8102E:
 		case RTK_HWREV_8102EL:
 			sc->sc_rev = 25;
 			sc->sc_quirk |=
 			    RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8100E:
 		case RTK_HWREV_8100E_SPIN2:
-			/* XXX not in the Realtek driver */
+		case RTK_HWREV_8101E:
 			sc->sc_rev = 0;
 			sc->sc_quirk |= RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8102E:
 		case RTK_HWREV_8102EL:
 		case RTK_HWREV_8103E:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
 			break;
 		default:
 			aprint_normal_dev(sc->sc_dev,
 			    "Unknown revision (0x%08x)\n", hwrev);
-			sc->sc_rev = 0;
+			/* assume the latest features */
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD;
 			sc->sc_quirk |= RTKQ_NOJUMBO;
+		}
 		/* Set RX length mask */
 		sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
 		sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169;
 	} else {
 		sc->sc_quirk |= RTKQ_NOJUMBO;
 		/* Set RX length mask */
 		sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
 		sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139;
+	}
 @@ -1256,45 +1241,69 @@ re_rxeof(struct rtk_softc *sc)
 				sc->re_tail->m_next = m;
+			}
 			m = sc->re_head;
 			sc->re_head = sc->re_tail = NULL;
 			m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
 		} else
 			m->m_pkthdr.len = m->m_len =
 			    (total_len - ETHER_CRC_LEN);
 		ifp->if_ipackets++;
 		m->m_pkthdr.rcvif = ifp;
 		/* Do RX checksumming */
 		if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
-		/* Check IP header checksum */
+			/* Check IP header checksum */
-		if ((rxstat & RE_RDESC_STAT_PROTOID) != 0 &&
+			if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) {
-		    ((sc->sc_quirk & RTKQ_DESCV2) == 0 ||
+				m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
-		     (rxvlan & RE_RDESC_VLANCTL_IPV4) != 0)) {
+				if (rxstat & RE_RDESC_STAT_IPSUMBAD)
-			m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
+					m->m_pkthdr.csum_flags |=
-			if (rxstat & RE_RDESC_STAT_IPSUMBAD)
+					    M_CSUM_IPv4_BAD;
 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
 				/* Check TCP/UDP checksum */
 				if (RE_TCPPKT(rxstat)) {
-		/* Check TCP/UDP checksum */
+					m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
-		if (RE_TCPPKT(rxstat)) {
+					if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
-			m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
+						m->m_pkthdr.csum_flags |=
-			if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
+						    M_CSUM_TCP_UDP_BAD;
-				m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD;
+				} else if (RE_UDPPKT(rxstat)) {
-		} else if (RE_UDPPKT(rxstat)) {
+					m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
-			m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
+					if (rxstat & RE_RDESC_STAT_UDPSUMBAD)
-			if (rxstat & RE_RDESC_STAT_UDPSUMBAD)
+						m->m_pkthdr.csum_flags |=
-				m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD;
+						    M_CSUM_TCP_UDP_BAD;
+				}
+			}
 		} else {
 			/* Check IPv4 header checksum */
 			if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) {
 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
 				if (rxstat & RE_RDESC_STAT_IPSUMBAD)
 					m->m_pkthdr.csum_flags |=
 					    M_CSUM_IPv4_BAD;
 				/* Check TCPv4/UDPv4 checksum */
 				if (RE_TCPPKT(rxstat)) {
 					m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
 					if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
 						m->m_pkthdr.csum_flags |=
 						    M_CSUM_TCP_UDP_BAD;
 				} else if (RE_UDPPKT(rxstat)) {
 					m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
 					if (rxstat & RE_RDESC_STAT_UDPSUMBAD)
 						m->m_pkthdr.csum_flags |=
 						    M_CSUM_TCP_UDP_BAD;
+				}
+			}
 			/* XXX Check TCPv6/UDPv6 checksum? */
+		}
 		if (rxvlan & RE_RDESC_VLANCTL_TAG) {
 			VLAN_INPUT_TAG(ifp, m,
 			     bswap16(rxvlan & RE_RDESC_VLANCTL_DATA),
 			     continue);
+		}
 #if NBPFILTER > 0
 		if (ifp->if_bpf)
 			bpf_mtap(ifp->if_bpf, m);
 #endif
 		(*ifp->if_input)(ifp, m);
+	}
 @@ -1703,69 +1712,65 @@ re_start(struct ifnet *ifp)
 		 * Set a timeout in case the chip goes out to lunch.
 		 */
 		ifp->if_timer = 5;
+	}
+}
 static int
 re_init(struct ifnet *ifp)
+{
 	struct rtk_softc *sc = ifp->if_softc;
 	const uint8_t *enaddr;
 	uint32_t rxcfg = 0;
 	uint32_t reg;
 	uint16_t cfg;
 	int error;
 	if ((error = re_enable(sc)) != 0)
 		goto out;
 	/*
 	 * Cancel pending I/O and free all RX/TX buffers.
 	 */
 	re_stop(ifp, 0);
 	re_reset(sc);
 	/*
 	 * Enable C+ RX and TX mode, as well as VLAN stripping and
 	 * RX checksum offload. We must configure the C+ register
 	 * before all others.
 	 */
-	reg = 0;
+	cfg = RE_CPLUSCMD_PCI_MRW;
 	/*
 	 * XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S.
 	 * FreeBSD  drivers set these bits anyway (for 8139C+?).
 	 * So far, it works.
 	 */
 	/*
 	 * XXX: For old 8169 set bit 14.
 	 *      For 8169S/8110S and above, do not set bit 14.
 	 */
 	if ((sc->sc_quirk & RTKQ_8169NONS) != 0)
-		reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW;;
+		cfg |= (0x1 << 14);
-	if (1)  {/* not for 8169S ? */
+	if ((ifp->if_capenable & ETHERCAP_VLAN_HWTAGGING) != 0)
-		reg |=
+		cfg |= RE_CPLUSCMD_VLANSTRIP;
-		    RTK_CPLUSCMD_VLANSTRIP |
+	if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx |
-		    (ifp->if_capenable &
+	     IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0)
-		    (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx |
+		cfg |= RE_CPLUSCMD_RXCSUM_ENB;
-		     IFCAP_CSUM_UDPv4_Rx) ?
+	if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) {
-		    RTK_CPLUSCMD_RXCSUM_ENB : 0);
+		cfg |= RE_CPLUSCMD_MACSTAT_DIS;
 		cfg |= RE_CPLUSCMD_TXENB;
 	} else
 		cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB;
-	CSR_WRITE_2(sc, RTK_CPLUS_CMD,
+	CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg);
 	    reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB);
 	/* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */
 	if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0)
 		CSR_WRITE_2(sc, RTK_IM, 0x0000);
 	DELAY(10000);
 	/*
 	 * Init our MAC address.  Even though the chipset
 	 * documentation doesn't mention it, we need to enter "Config
 	 * register write enable" mode to modify the ID registers.
 	 */
 	CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG);
 @@ -1965,28 +1970,34 @@ re_watchdog(struct ifnet *ifp)
  * Stop the adapter and free any mbufs allocated to the
  * RX and TX lists.
  */
 static void
 re_stop(struct ifnet *ifp, int disable)
+{
 	int i;
 	struct rtk_softc *sc = ifp->if_softc;
 	callout_stop(&sc->rtk_tick_ch);
 	mii_down(&sc->mii);
-	CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
+	if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0)
 		CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB |
 		    RTK_CMD_RX_ENB);
 	else
 		CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
 	DELAY(1000);
 	CSR_WRITE_2(sc, RTK_IMR, 0x0000);
 	CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
 	if (sc->re_head != NULL) {
 		m_freem(sc->re_head);
 		sc->re_head = sc->re_tail = NULL;
+	}
 	/* Free the TX list buffers. */
 	for (i = 0; i < RE_TX_QLEN; i++) {
 		if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) {
 			bus_dmamap_unload(sc->sc_dmat,
 			    sc->re_ldata.re_txq[i].txq_dmamap);
 			m_freem(sc->re_ldata.re_txq[i].txq_mbuf);
 			sc->re_ldata.re_txq[i].txq_mbuf = NULL;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: rtl81x9reg.h,v 1.32.4.3 2009/05/01 02:10:03 snj Exp $	*/
+/*	$NetBSD: rtl81x9reg.h,v 1.32.4.4 2009/06/19 21:51:43 snj Exp $	*/
 /*
  * Copyright (c) 1997, 1998
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -148,35 +148,39 @@
 #define RTK_TXCFG_HWREV		0x7CC00000
 #define RTK_LOOPTEST_OFF		0x00000000
 #define RTK_LOOPTEST_ON		0x00020000
 #define RTK_LOOPTEST_ON_CPLUS	0x00060000
 /* Known revision codes. */
 #define RTK_HWREV_8169		0x00000000
 #define RTK_HWREV_8110S		0x00800000
 #define RTK_HWREV_8169S		0x04000000
 #define RTK_HWREV_8169_8110SB	0x10000000
 #define RTK_HWREV_8169_8110SC	0x18000000
 #define RTK_HWREV_8102EL	0x24800000
 #define RTK_HWREV_8103E		0x24C00000
 #define RTK_HWREV_8168D		0x28000000
 #define RTK_HWREV_8168DP	0x28800000
 #define RTK_HWREV_8168_SPIN1	0x30000000
 #define RTK_HWREV_8100E		0x30800000
 #define RTK_HWREV_8101E		0x34000000
 #define RTK_HWREV_8102E		0x34800000
 #define RTK_HWREV_8168_SPIN2	0x38000000
 #define RTK_HWREV_8168_SPIN3	0x38400000
 #define RTK_HWREV_8100E_SPIN2	0x38800000
 #define RTK_HWREV_8168C		0x3C000000
 #define RTK_HWREV_8168C_SPIN2	0x3C400000
 #define RTK_HWREV_8168CP	0x3C800000
 #define RTK_HWREV_8139		0x60000000
 #define RTK_HWREV_8139A		0x70000000
 #define RTK_HWREV_8139AG	0x70800000
 #define RTK_HWREV_8139B		0x78000000
 #define RTK_HWREV_8130		0x7C000000
 #define RTK_HWREV_8139C		0x74000000
 #define RTK_HWREV_8139D		0x74400000
 #define RTK_HWREV_8139CPLUS	0x74800000
 #define RTK_HWREV_8101		0x74c00000
 #define RTK_HWREV_8100		0x78800000
 #define RTK_TXDMA_16BYTES	0x00000000
 #define RTK_TXDMA_32BYTES	0x00000100
 @@ -296,26 +300,27 @@
 #define RTK_RXSTAT_BROAD	0x00002000
 #define RTK_RXSTAT_INDIV	0x00004000
 #define RTK_RXSTAT_MULTI	0x00008000
 #define RTK_RXSTAT_LENMASK	0xFFFF0000
 #define RTK_RXSTAT_UNFINISHED	0xFFF0		/* DMA still in progress */
 /*
  * Command register.
  */
 #define RTK_CMD_EMPTY_RXBUF	0x0001
 #define RTK_CMD_TX_ENB		0x0004
 #define RTK_CMD_RX_ENB		0x0008
 #define RTK_CMD_RESET		0x0010
 #define RTK_CMD_STOPREQ		0x0080
 /*
  * EEPROM control register
  */
 #define RTK_EE_DATAOUT		0x01	/* Data out */
 #define RTK_EE_DATAIN		0x02	/* Data in */
 #define RTK_EE_CLK		0x04	/* clock */
 #define RTK_EE_SEL		0x08	/* chip select */
 #define RTK_EE_MODE		(0x40|0x80)
 #define RTK_EEMODE_OFF		0x00
 #define RTK_EEMODE_AUTOLOAD	0x40
 #define RTK_EEMODE_PROGRAM	0x80
 @@ -390,32 +395,41 @@
  */
 #define RTK_CFG2_BUSFREQ		0x07
 #define RTK_CFG2_BUSWIDTH	0x08
 #define RTK_CFG2_AUXPWRSTS	0x10
 #define RTK_BUSFREQ_33MHZ	0x00
 #define RTK_BUSFREQ_66MHZ	0x01
 #define RTK_BUSWIDTH_32BITS	0x00
 #define RTK_BUSWIDTH_64BITS	0x08
 /* C+ mode command register */
-#define RTK_CPLUSCMD_TXENB	0x0001	/* enable C+ transmit mode */
+#define RE_CPLUSCMD_TXENB	0x0001	/* enable C+ transmit mode */
-#define RTK_CPLUSCMD_RXENB	0x0002	/* enable C+ receive mode */
+#define RE_CPLUSCMD_RXENB	0x0002	/* enable C+ receive mode */
-#define RTK_CPLUSCMD_PCI_MRW	0x0008	/* enable PCI multi-read/write */
+#define RE_CPLUSCMD_PCI_MRW	0x0008	/* enable PCI multi-read/write */
-#define RTK_CPLUSCMD_PCI_DAC	0x0010	/* PCI dual-address cycle only */
+#define RE_CPLUSCMD_PCI_DAC	0x0010	/* PCI dual-address cycle only */
-#define RTK_CPLUSCMD_RXCSUM_ENB	0x0020	/* enable RX checksum offload */
+#define RE_CPLUSCMD_RXCSUM_ENB	0x0020	/* enable RX checksum offload */
-#define RTK_CPLUSCMD_VLANSTRIP	0x0040	/* enable VLAN tag stripping */
+#define RE_CPLUSCMD_VLANSTRIP	0x0040	/* enable VLAN tag stripping */
 #define RE_CPLUSCMD_MACSTAT_DIS	0x0080	/* 8168B/C/CP */
 #define RE_CPLUSCMD_ASF		0x0100	/* 8168C/CP */
 #define RE_CPLUSCMD_DBG_SEL	0x0200	/* 8168C/CP */
 #define RE_CPLUSCMD_FORCE_TXFC	0x0400	/* 8168C/CP */
 #define RE_CPLUSCMD_FORCE_RXFC	0x0800	/* 8168C/CP */
 #define RE_CPLUSCMD_FORCE_HDPX	0x1000	/* 8168C/CP */
 #define RE_CPLUSCMD_NORMAL_MODE	0x2000	/* 8168C/CP */
 #define RE_CPLUSCMD_DBG_ENB	0x4000	/* 8168C/CP */
 #define RE_CPLUSCMD_BIST_ENB	0x8000	/* 8168C/CP */
 /* C+ early transmit threshold */
 #define RTK_EARLYTXTHRESH_CNT	0x003F	/* byte count times 8 */
 /*
  * Gigabit PHY access register (8169 only)
  */
 #define RTK_PHYAR_PHYDATA	0x0000FFFF
 #define RTK_PHYAR_PHYREG		0x001F0000
 #define RTK_PHYAR_BUSY		0x80000000

 @@ -1,14 +1,14 @@
-/*	$NetBSD: rtl81x9var.h,v 1.41.12.4 2009/05/01 02:08:29 snj Exp $	*/
+/*	$NetBSD: rtl81x9var.h,v 1.41.12.5 2009/06/19 21:51:43 snj Exp $	*/
 /*
  * Copyright (c) 1997, 1998
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -182,26 +182,28 @@ struct rtk_softc {
 	struct mii_data		mii;
 	struct callout		rtk_tick_ch;	/* tick callout */
 	bus_space_handle_t	rtk_bhandle;	/* bus space handle */
 	bus_space_tag_t		rtk_btag;	/* bus space tag */
 	u_int			sc_quirk;	/* chip quirks */
 #define RTKQ_8129		0x00000001	/* 8129 */
 #define RTKQ_8139CPLUS		0x00000002	/* 8139C+ */
 #define RTKQ_8169NONS		0x00000004	/* old non-single 8169 */
 #define RTKQ_PCIE		0x00000008	/* PCIe variants */
 #define RTKQ_MACLDPS		0x00000010	/* has LDPS register */
 #define RTKQ_DESCV2		0x00000020	/* has V2 TX/RX descriptor */
 #define RTKQ_NOJUMBO		0x00000040	/* no jumbo MTU support */
 #define RTKQ_NOEECMD		0x00000080	/* unusable EEPROM command */
 #define RTKQ_MACSTAT		0x00000100	/* set MACSTAT_DIS on init */
 #define RTKQ_CMDSTOP		0x00000200	/* set STOPREQ on stop */
 	bus_dma_tag_t 		sc_dmat;
 	bus_dma_segment_t 	sc_dmaseg;	/* for rtk(4) */
 	int			sc_dmanseg;	/* for rtk(4) */
 	bus_dmamap_t 		recv_dmamap;	/* for rtk(4) */
 	void *			rtk_rx_buf;
 	struct rtk_tx_desc	rtk_tx_descs[RTK_TX_LIST_CNT];
 	SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_free;
 	SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_dirty;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: rgephy.c,v 1.21 2008/05/04 17:06:10 xtraeme Exp $	*/
+/*	$NetBSD: rgephy.c,v 1.21.10.1 2009/06/19 21:51:43 snj Exp $	*/
 /*
  * Copyright (c) 2003
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -23,27 +23,27 @@
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.21 2008/05/04 17:06:10 xtraeme Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.21.10.1 2009/06/19 21:51:43 snj Exp $");
 /*
  * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
  */
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/socket.h>
 @@ -579,33 +579,26 @@ rgephy_load_dspcode(struct mii_softc *sc
 static void
 rgephy_reset(struct mii_softc *sc)
+{
 	struct rgephy_softc *rsc;
 	mii_phy_reset(sc);
 	DELAY(1000);
 	rsc = (struct rgephy_softc *)sc;
 	if (rsc->mii_revision < 2)
 		rgephy_load_dspcode(sc);
 	else {
 		PHY_WRITE(sc, 0x1F, 0x0001);
 		PHY_WRITE(sc, 0x09, 0x273a);
 		PHY_WRITE(sc, 0x0e, 0x7bfb);
 		PHY_WRITE(sc, 0x1b, 0x841e);
 		PHY_WRITE(sc, 0x1F, 0x0002);
 		PHY_WRITE(sc, 0x01, 0x90D0);
 		PHY_WRITE(sc, 0x1F, 0x0000);
 		PHY_WRITE(sc, 0x0e, 0x0000);
+	}
 	/* Reset capabilities */
 	/* Step1: write our capability */
 	/* 10/100 capability */
 	PHY_WRITE(sc, RGEPHY_MII_ANAR,
 	    RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
 	    RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10 | ANAR_CSMA);
 	/* 1000 capability */
 	PHY_WRITE(sc, RGEPHY_MII_1000CTL,
 	    RGEPHY_1000CTL_AFD | RGEPHY_1000CTL_AHD);

 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_re_pci.c,v 1.35 2008/08/23 14:27:45 tnn Exp $	*/
+/*	$NetBSD: if_re_pci.c,v 1.35.4.1 2009/06/19 21:51:44 snj Exp $	*/
 /*
  * Copyright (c) 1997, 1998-2003
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -36,27 +36,27 @@
 /*
  * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
+ *
  * Written by Bill Paul <wpaul@windriver.com>
  * Senior Networking Software Engineer
  * Wind River Systems
+ *
  * NetBSD bus-specific frontends for written by
  * Jonathan Stone <jonathan@netbsd.org>
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_re_pci.c,v 1.35 2008/08/23 14:27:45 tnn Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_re_pci.c,v 1.35.4.1 2009/06/19 21:51:44 snj Exp $");
 #include "bpfilter.h"
 #include "vlan.h"
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/endian.h>
 #include <sys/systm.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 @@ -99,27 +99,27 @@ CFATTACH_DECL_NEW(re_pci, sizeof(struct
 /*
  * Various supported device vendors/types and their names.
  */
 static const struct rtk_type re_devs[] = {
 	{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
 	    RTK_8139CPLUS,
 	    "RealTek 8139C+ 10/100BaseTX" },
 	{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E,
 	    RTK_8101E,
 	    "RealTek 8100E/8101E/8102E/8102EL PCIe 10/100BaseTX" },
 	{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168,
 	    RTK_8168,
-	    "RealTek 8168B/8111B PCIe Gigabit Ethernet" },
+	    "RealTek 8168/8111 PCIe Gigabit Ethernet" },
 	{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169,
 	    RTK_8169,
 	    "RealTek 8169/8110 Gigabit Ethernet" },
 	{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC,
 	    RTK_8169,
 	    "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
 	{ PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_LAPCIGT,
 	    RTK_8169,
 	    "Corega CG-LAPCIGT Gigabit Ethernet" },
 	{ PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T,
 	    RTK_8169,
 	    "D-Link DGE-528T Gigabit Ethernet" },
 	{ PCI_VENDOR_USR2, PCI_PRODUCT_USR2_USR997902,