Mon Jul 20 16:45:50 2009 UTC ()
Sprinkle keyword volatile around device register accesses.


(tsutsui)
diff -r1.10 -r1.11 src/sys/arch/pmax/pmax/memc_3min.c
cvs diff -r1.10 -r1.11 src/sys/arch/pmax/pmax/memc_3min.c (expand / switch to unified diff)

--- src/sys/arch/pmax/pmax/memc_3min.c 2005/12/11 12:18:39 1.10
+++ src/sys/arch/pmax/pmax/memc_3min.c 2009/07/20 16:45:50 1.11
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: memc_3min.c,v 1.10 2005/12/11 12:18:39 christos Exp $ */ 1/* $NetBSD: memc_3min.c,v 1.11 2009/07/20 16:45:50 tsutsui Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1992, 1993 4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved. 5 * The Regents of the University of California. All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to Berkeley by 7 * This code is derived from software contributed to Berkeley by
8 * the Systems Programming Group of the University of Utah Computer 8 * the Systems Programming Group of the University of Utah Computer
9 * Science Department and Ralph Campbell. 9 * Science Department and Ralph Campbell.
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -69,58 +69,58 @@ @@ -69,58 +69,58 @@
69 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
70 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
71 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
72 * SUCH DAMAGE. 72 * SUCH DAMAGE.
73 * 73 *
74 * from: Utah Hdr: trap.c 1.32 91/04/06 74 * from: Utah Hdr: trap.c 1.32 91/04/06
75 * 75 *
76 * @(#)trap.c 8.5 (Berkeley) 1/11/94 76 * @(#)trap.c 8.5 (Berkeley) 1/11/94
77 */ 77 */
78 78
79 79
80#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 80#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
81 81
82__KERNEL_RCSID(0, "$NetBSD: memc_3min.c,v 1.10 2005/12/11 12:18:39 christos Exp $"); 82__KERNEL_RCSID(0, "$NetBSD: memc_3min.c,v 1.11 2009/07/20 16:45:50 tsutsui Exp $");
83 83
84/* 84/*
85 * Motherboard memory error contoller used in both 85 * Motherboard memory error contoller used in both
86 * 3min (kn02ba) and maxine (kn02ca). 86 * 3min (kn02ba) and maxine (kn02ca).
87 */ 87 */
88 88
89#include <sys/types.h> 89#include <sys/types.h>
90#include <sys/systm.h> 90#include <sys/systm.h>
91 91
92#include <mips/cpuregs.h> 92#include <mips/cpuregs.h>
93 93
94#include <pmax/pmax/kmin.h> 94#include <pmax/pmax/kmin.h>
95#include <pmax/pmax/memc.h> 95#include <pmax/pmax/memc.h>
96 96
97/* 97/*
98 * Handle error 98 * Handle error
99 * All we can do with parity is panic. 99 * All we can do with parity is panic.
100 * XXX check for clean user pages, replace frame, and reload ? 100 * XXX check for clean user pages, replace frame, and reload ?
101 */ 101 */
102void 102void
103kn02ba_errintr() 103kn02ba_errintr()
104{ 104{
105 int mer, adr, siz, err; 105 int mer, adr, siz, err;
106 static int errintr_cnt = 0; 106 static int errintr_cnt = 0;
107 107
108 siz = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR); 108 siz = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR);
109 mer = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MER); 109 mer = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MER);
110 adr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_AER); 110 adr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_AER);
111 111
112 /* clear interrupt bit */ 112 /* clear interrupt bit */
113 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 113 *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
114 114
115 err = 0; /* XXX gcc */ 115 err = 0; /* XXX gcc */
116 switch (mer & KMIN_MER_LASTBYTE) { 116 switch (mer & KMIN_MER_LASTBYTE) {
117 case KMIN_LASTB31: 117 case KMIN_LASTB31:
118 err = 3; break; 118 err = 3; break;
119 case KMIN_LASTB23: 119 case KMIN_LASTB23:
120 err = 2; break; 120 err = 2; break;
121 case KMIN_LASTB15: 121 case KMIN_LASTB15:
122 err = 1; break; 122 err = 1; break;
123 case KMIN_LASTB07: 123 case KMIN_LASTB07:
124 err = 0; break; 124 err = 0; break;
125 } 125 }
126 err |= (adr & KMIN_AER_ADDR_MASK); 126 err |= (adr & KMIN_AER_ADDR_MASK);