 @@ -1,14 +1,14 @@
-/*	$NetBSD: ifpga.c,v 1.22 2008/04/27 18:58:46 matt Exp $ */
+/*	$NetBSD: ifpga.c,v 1.23 2009/07/21 16:04:16 dyoung Exp $ */
 /*
  * Copyright (c) 2001 ARM Ltd
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -28,27 +28,27 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /*
  * Integrator FPGA core logic support.
+ *
  * The integrator board supports the core logic in an FPGA which is loaded
  * at POR with a custom design.  This code supports the default logic as the
  * board is shipped.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ifpga.c,v 1.22 2008/04/27 18:58:46 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ifpga.c,v 1.23 2009/07/21 16:04:16 dyoung Exp $");
 #include <sys/param.h>
 #include <sys/types.h>
 #include <sys/device.h>
 #include <sys/systm.h>
 #include <sys/extent.h>
 #include <sys/malloc.h>
 #include <sys/null.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pciconf.h>
 #include <arm/cpufunc.h>
 @@ -56,143 +56,145 @@ __KERNEL_RCSID(0, "$NetBSD: ifpga.c,v 1.
 #include "opt_pci.h"
 #include "pci.h"
 #include <evbarm/ifpga/ifpgamem.h>
 #include <evbarm/ifpga/ifpgavar.h>
 #include <evbarm/ifpga/ifpgareg.h>
 #include <evbarm/ifpga/ifpga_pcivar.h>
 #include <evbarm/dev/v360reg.h>
 #include <evbarm/integrator/int_bus_dma.h>
 #include "locators.h"
 /* Prototypes */
-static int  ifpga_match		(struct device *, struct cfdata *, void *);
+static int  ifpga_match		(device_t, cfdata_t, void *);
-static void ifpga_attach	(struct device *, struct device *, void *);
+static void ifpga_attach	(device_t, device_t, void *);
 static int  ifpga_print		(void *, const char *);
 /* Drive and attach structures */
-CFATTACH_DECL(ifpga, sizeof(struct ifpga_softc),
+CFATTACH_DECL_NEW(ifpga, sizeof(struct ifpga_softc),
     ifpga_match, ifpga_attach, NULL, NULL);
 int ifpga_found;
 /* Default UART clock speed (we should make this a boot option).  */
 int ifpga_uart_clk = IFPGA_UART_CLK;
 #if NPCI > 0
 /* PCI handles */
 extern struct arm32_pci_chipset ifpga_pci_chipset;
 extern struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag;
 static struct bus_space ifpga_pci_io_tag;
 static struct bus_space ifpga_pci_mem_tag;
 #endif /* NPCI > 0 */
 static struct bus_space ifpga_bs_tag;
 struct ifpga_softc *ifpga_sc;
 device_t ifpga_dev;
 /*
  * Print the configuration information for children
  */
 static int
 ifpga_print(void *aux, const char *pnp)
+{
 	struct ifpga_attach_args *ifa = aux;
 	if (ifa->ifa_addr != -1)
 		aprint_normal(" addr 0x%lx", (unsigned long)ifa->ifa_addr);
 	if (ifa->ifa_irq != -1)
 		aprint_normal(" irq %d", ifa->ifa_irq);
 	return UNCONF;
+}
 static int
-ifpga_search(struct device *parent, struct cfdata *cf,
+ifpga_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
 	     const int *ldesc, void *aux)
+{
-	struct ifpga_softc *sc = (struct ifpga_softc *)parent;
+	struct ifpga_softc *sc = device_private(parent);
 	struct ifpga_attach_args ifa;
 	int tryagain;
 	do {
 		ifa.ifa_iot = sc->sc_iot;
 		ifa.ifa_addr = cf->cf_iobase;
 		ifa.ifa_irq = cf->cf_irq;
 		ifa.ifa_sc_ioh = sc->sc_sc_ioh;
 		tryagain = 0;
 		if (config_match(parent, cf, &ifa) > 0) {
 			config_attach(parent, cf, &ifa, ifpga_print);
 			tryagain = (cf->cf_fstate == FSTATE_STAR);
+		}
 	} while (tryagain);
 	return 0;
+}
 static int
-ifpga_match(struct device *parent, struct cfdata *cf, void *aux)
+ifpga_match(device_t parent, cfdata_t cf, void *aux)
+{
 #if 0
 	struct mainbus_attach_args *ma = aux;
 	/* Make sure that we're looking for the IFPGA.  */
 	if (strcmp(ma->ma_name, ifpga_md.md_name))
 		return 0;
 #endif
 	/* We can only have one instance of the IFPGA.  */
 	if (ifpga_found)
 		return 0;
 	return 1;
+}
 static void
-ifpga_attach(struct device *parent, struct device *self, void *aux)
+ifpga_attach(device_t parent, device_t self, void *aux)
+{
-	struct ifpga_softc *sc = (struct ifpga_softc *)self;
+	struct ifpga_softc *sc = device_private(self);
 	u_int id, sysclk;
 #if defined(PCI_NETBSD_CONFIGURE) && NPCI > 0
 	struct extent *ioext, *memext, *pmemext;
 	struct ifpga_pci_softc *pci_sc;
 	struct pcibus_attach_args pci_pba;
 #endif
 	ifpga_found = 1;
 	/* We want a memory-mapped bus space, since the I/O space is sparse. */
 	ifpga_create_mem_bs_tag(&ifpga_bs_tag, (void *)IFPGA_IO_BASE);
 #if NPCI > 0
 	/* But the PCI config space is quite large, so we have a linear region
 	   for that pre-allocated.  */
 	ifpga_create_io_bs_tag(&ifpga_pci_io_tag, (void *)IFPGA_PCI_IO_VBASE);
 	ifpga_create_mem_bs_tag(&ifpga_pci_mem_tag, (void *)0);
 #endif
 	sc->sc_iot = &ifpga_bs_tag;
 	ifpga_dev = self;
 	ifpga_sc = sc;
 	/* Now map in the IFPGA motherboard registers.  */
 	if (bus_space_map(sc->sc_iot, IFPGA_IO_SC_BASE, IFPGA_IO_SC_SIZE, 0,
 	    &sc->sc_sc_ioh))
 		panic("%s: Cannot map system controller registers",
-		    self->dv_xname);
+		    device_xname(self));
 	id = bus_space_read_4(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_ID);
 	printf(": Build %d, ", (id & IFPGA_SC_ID_BUILD_MASK) >>
 	    IFPGA_SC_ID_BUILD_SHIFT);
 	switch (id & IFPGA_SC_ID_REV_MASK)
+	{
 	case IFPGA_SC_ID_REV_A:
 		printf("Rev A, ");
 		break;
 	case IFPGA_SC_ID_REV_B:
 		printf("Rev B, ");
 		break;
 @@ -211,93 +213,95 @@ ifpga_attach(struct device *parent, stru
 	switch (id & IFPGA_SC_ID_ARCH_MASK)
+	{
 	case IFPGA_SC_ID_ARCH_ASBLE:
 		printf(" ASB, Little-endian,");
 		break;
 	case IFPGA_SC_ID_ARCH_AHBLE:
 		printf(" AHB, Little-endian,");
 		break;
 	default:
 		panic(" Unsupported bus");
+	}
-	printf("\n%s: FPGA ", self->dv_xname);
+	printf("\n%s: FPGA ", device_xname(self));
 	switch (id & IFPGA_SC_ID_FPGA_MASK)
+	{
 	case IFPGA_SC_ID_FPGA_XC4062:
 		printf("XC4062");
 		break;
 	case IFPGA_SC_ID_FPGA_XC4085:
 		printf("XC4085");
 		break;
 	default:
 		printf("unknown");
 		break;
+	}
 	sysclk = bus_space_read_1(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_OSC);
 	sysclk &= IFPGA_SC_OSC_S_VDW;
 	sysclk += 8;
 	printf(", SYSCLK %d.%02dMHz", sysclk >> 2, (sysclk & 3) * 25);
 	/* Map the Interrupt controller */
 	if (bus_space_map(sc->sc_iot, IFPGA_IO_IRQ_BASE, IFPGA_IO_IRQ_SIZE,
 	    BUS_SPACE_MAP_LINEAR, &sc->sc_irq_ioh))
 		panic("%s: Cannot map irq controller registers",
-		    self->dv_xname);
+		    device_xname(self));
 	/* We can write to the IRQ/FIQ controller now.  */
 	ifpga_intr_postinit();
 	/* Map the core module */
 	if (bus_space_map(sc->sc_iot, IFPGA_IO_CM_BASE, IFPGA_IO_CM_SIZE, 0,
-	    &sc->sc_cm_ioh))
+	    &sc->sc_cm_ioh)) {
-		panic("%s: Cannot map core module registers", self->dv_xname);
+		panic("%s: Cannot map core module registers",
 		    device_xname(self));
+	}
 	/* Map the timers */
 	if (bus_space_map(sc->sc_iot, IFPGA_IO_TMR_BASE, IFPGA_IO_TMR_SIZE, 0,
 	    &sc->sc_tmr_ioh))
-		panic("%s: Cannot map timer registers", self->dv_xname);
+		panic("%s: Cannot map timer registers", device_xname(self));
 	printf("\n");
 #if NPCI > 0
 	pci_sc = malloc(sizeof(struct ifpga_pci_softc), M_DEVBUF, M_WAITOK);
 	pci_sc->sc_iot = &ifpga_pci_io_tag;
 	pci_sc->sc_memt = &ifpga_pci_mem_tag;
 	if (bus_space_map(pci_sc->sc_iot, 0, IFPGA_PCI_IO_VSIZE, 0,
 	    &pci_sc->sc_io_ioh)
 	    || bus_space_map(pci_sc->sc_iot,
 	    IFPGA_PCI_CONF_VBASE - IFPGA_PCI_IO_VBASE, IFPGA_PCI_CONF_VSIZE, 0,
 	    &pci_sc->sc_conf_ioh)
 	    || bus_space_map(pci_sc->sc_memt, IFPGA_V360_REG_BASE,
 	    IFPGA_V360_REG_SIZE, 0, &pci_sc->sc_reg_ioh))
-		panic("%s: Cannot map pci memory", self->dv_xname);
+		panic("%s: Cannot map pci memory", device_xname(self));
+	{
 		pcireg_t id_reg, class_reg;
 		char buf[1000];
 		id_reg = bus_space_read_4(pci_sc->sc_memt, pci_sc->sc_reg_ioh,
 		    V360_PCI_VENDOR);
 		class_reg = bus_space_read_4(pci_sc->sc_memt,
 		    pci_sc->sc_reg_ioh, V360_PCI_CC_REV);
 		pci_devinfo(id_reg, class_reg, 1, buf, sizeof(buf));
-		printf("%s: %s\n", self->dv_xname, buf);
+		printf("%s: %s\n", device_xname(self), buf);
+	}
 #if defined(PCI_NETBSD_CONFIGURE)
 	ioext = extent_create("pciio", 0x00000000,
 x00000000 + IFPGA_PCI_IO_VSIZE, M_DEVBUF, NULL, 0, EX_NOWAIT);
 	memext = extent_create("pcimem", IFPGA_PCI_APP0_BASE,
 	    IFPGA_PCI_APP0_BASE + IFPGA_PCI_APP0_SIZE,
 	    M_DEVBUF, NULL, 0, EX_NOWAIT);
 	pmemext = extent_create("pcipmem", IFPGA_PCI_APP1_BASE,
 	    IFPGA_PCI_APP1_BASE + IFPGA_PCI_APP1_SIZE,
 	    M_DEVBUF, NULL, 0, EX_NOWAIT);
 	ifpga_pci_chipset.pc_conf_v = (void *)pci_sc;
 	pci_configure_bus(&ifpga_pci_chipset, ioext, memext, pmemext, 0,

 @@ -1,14 +1,14 @@
-/*	$NetBSD: ifpga_clock.c,v 1.13 2009/03/18 10:22:27 cegger Exp $ */
+/*	$NetBSD: ifpga_clock.c,v 1.14 2009/07/21 16:04:16 dyoung Exp $ */
 /*
  * Copyright (c) 2001 ARM Ltd
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -29,27 +29,27 @@
  * SUCH DAMAGE.
  */
 /*
  * The IFPGA has three timers.  Timer 0 is clocked by the system bus clock,
  * while timers 1 and 2 are clocked at 24MHz.  To keep things simple here,
  * we use timers 1 and 2 only.  All three timers are 16-bit counters that
  * are programmable in either periodic mode or in one-shot mode.
  */
 /* Include header files */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ifpga_clock.c,v 1.13 2009/03/18 10:22:27 cegger Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ifpga_clock.c,v 1.14 2009/07/21 16:04:16 dyoung Exp $");
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/atomic.h>
 #include <sys/time.h>
 #include <sys/timetc.h>
 #include <sys/device.h>
 #include <arm/cpufunc.h>
 #include <machine/intr.h>
 @@ -89,26 +89,27 @@ static struct timecounter ifpga_timecoun
 	ifpga_get_timecount,	/* get_timecount */
 ,			/* no poll_pps */
 xffffffff,		/* counter_mask */
 	COUNTS_PER_SEC,		/* frequency */
 	"ifpga",		/* name */
 ,			/* quality */
 	NULL,			/* prev */
 	NULL,			/* next */
 };
 static volatile uint32_t ifpga_base;
 extern struct ifpga_softc *ifpga_sc;
 extern device_t ifpga_dev;
 static int clock_started = 0;
 static int load_timer(int, int);
 static inline u_int
 getclock(void)
+{
 	return bus_space_read_4(ifpga_sc->sc_iot, ifpga_sc->sc_tmr_ioh,
 	    TIMER_1_VALUE);
+}
 static inline u_int
 @@ -277,46 +278,46 @@ cpu_initclocks(void)
 	statmin = statint - (statvar >> 1);
 	profmin = profint - (statvar >> 1);
 	timer2min = statmin;
 	statprev = statint;
 	/* Report the clock frequencies */
 	printf("clock: hz=%d stathz = %d profhz = %d\n", hz, stathz, profhz);
 	/* Setup timer 1 and claim interrupt */
 	ifpga_sc->sc_clockintr = ifpga_intr_establish(IFPGA_TIMER1_IRQ,
 	    IPL_CLOCK, clockhandler, 0);
 	if (ifpga_sc->sc_clockintr == NULL)
 		panic("%s: Cannot install timer 1 interrupt handler",
-		    ifpga_sc->sc_dev.dv_xname);
+		    device_xname(ifpga_dev));
 	ifpga_sc->sc_clock_count
 	    = load_timer(IFPGA_TIMER1_BASE, intvl);
 	/*
 	 * Use ticks per 256us for accuracy since ticks per us is often
 	 * fractional e.g. @ 66MHz
 	 */
 	ifpga_sc->sc_clock_ticks_per_256us =
 	    ((((ifpga_sc->sc_clock_count * hz) / 1000) * 256) / 1000);
 	clock_started = 1;
 	/* Set up timer 2 as statclk/profclk. */
 	ifpga_sc->sc_statclockintr = ifpga_intr_establish(IFPGA_TIMER2_IRQ,
 	    IPL_HIGH, statclockhandler, 0);
 	if (ifpga_sc->sc_statclockintr == NULL)
 		panic("%s: Cannot install timer 2 interrupt handler",
-		    ifpga_sc->sc_dev.dv_xname);
+		    device_xname(ifpga_dev));
 	load_timer(IFPGA_TIMER2_BASE, statint);
 	tc_init(&ifpga_timecounter);
+}
 static u_int
 ifpga_get_timecount(struct timecounter *tc)
+{
 	u_int base, counter;
 	do {
 		base = ifpga_base;
 		counter = getclock();

 @@ -1,14 +1,14 @@
-/*	$NetBSD: ifpga_pci.c,v 1.12 2005/12/11 12:17:09 christos Exp $	*/
+/*	$NetBSD: ifpga_pci.c,v 1.13 2009/07/21 16:04:16 dyoung Exp $	*/
 /*
  * Copyright (c) 2001 ARM Ltd
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -54,48 +54,48 @@
  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #define _ARM32_BUS_DMA_PRIVATE
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ifpga_pci.c,v 1.12 2005/12/11 12:17:09 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ifpga_pci.c,v 1.13 2009/07/21 16:04:16 dyoung Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/conf.h>
 #include <sys/malloc.h>
 #include <sys/device.h>
 #include <evbarm/integrator/int_bus_dma.h>
 #include <machine/intr.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <evbarm/ifpga/ifpgareg.h>
 #include <evbarm/ifpga/ifpgamem.h>
 #include <evbarm/ifpga/ifpga_pcivar.h>
 #include <evbarm/dev/v360reg.h>
-void		ifpga_pci_attach_hook (struct device *, struct device *,
+void		ifpga_pci_attach_hook (device_t, device_t,
 		    struct pcibus_attach_args *);
 int		ifpga_pci_bus_maxdevs (void *, int);
 pcitag_t	ifpga_pci_make_tag (void *, int, int, int);
 void		ifpga_pci_decompose_tag (void *, pcitag_t, int *, int *,
 		    int *);
 pcireg_t	ifpga_pci_conf_read (void *, pcitag_t, int);
 void		ifpga_pci_conf_write (void *, pcitag_t, int, pcireg_t);
 int		ifpga_pci_intr_map (struct pci_attach_args *,
 		    pci_intr_handle_t *);
 const char	*ifpga_pci_intr_string (void *, pci_intr_handle_t);
 const struct evcnt *ifpga_pci_intr_evcnt (void *, pci_intr_handle_t);
 void		*ifpga_pci_intr_establish (void *, pci_intr_handle_t, int,
 		    int (*)(void *), void *);
 @@ -146,27 +146,27 @@ struct arm32_bus_dma_tag ifpga_pci_bus_d
  * (See conf_{read,write} for more detail
  */
 #define MAX_PCI_DEVICES	21
 /*static int
 pci_intr(void *arg)
+{
 	printf("pci int %x\n", (int)arg);
 	return 0;
 }*/
 void
-ifpga_pci_attach_hook(struct device *parent, struct device *self,
+ifpga_pci_attach_hook(device_t parent, device_t self,
     struct pcibus_attach_args *pba)
+{
 #ifdef PCI_DEBUG
 	printf("ifpga_pci_attach_hook()\n");
 #endif
+}
 int
 ifpga_pci_bus_maxdevs(void *pcv, int busno)
+{
 #ifdef PCI_DEBUG
 	printf("ifpga_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno);
 #endif

 @@ -1,14 +1,14 @@
-/*	$NetBSD: ifpga_pcivar.h,v 1.1 2001/10/27 16:19:09 rearnsha Exp $ */
+/*	$NetBSD: ifpga_pcivar.h,v 1.2 2009/07/21 16:04:16 dyoung Exp $ */
 /*
  * Copyright (c) 2001 ARM Ltd
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -20,28 +20,26 @@
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 struct ifpga_pci_softc {
 	struct device		sc_dev;
 	bus_space_tag_t		sc_iot;
 	bus_space_handle_t	sc_io_ioh;
 	bus_space_handle_t	sc_conf_ioh;
 	bus_space_tag_t		sc_memt;
 	bus_space_handle_t	sc_app0_ioh;
 	bus_space_handle_t	sc_app1_ioh;
 	bus_space_handle_t	sc_reg_ioh;
 };
 /* Apperture 0, 256MB normal cycles.  */
 #define IFPGA_PCI_APP0_256MB_BASE	0x40000081
 #define IFPGA_PCI_APP0_512MB_BASE	0x40000091

 @@ -1,14 +1,14 @@
-/*	$NetBSD: pl030_rtc.c,v 1.8 2007/02/19 02:08:12 briggs Exp $ */
+/*	$NetBSD: pl030_rtc.c,v 1.9 2009/07/21 16:04:16 dyoung Exp $ */
 /*
  * Copyright (c) 2001 ARM Ltd
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -22,94 +22,93 @@
  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /* Include header files */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pl030_rtc.c,v 1.8 2007/02/19 02:08:12 briggs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pl030_rtc.c,v 1.9 2009/07/21 16:04:16 dyoung Exp $");
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/time.h>
 #include <sys/device.h>
 #include <dev/clock_subr.h>
 #include <arm/cpufunc.h>
 #include <machine/intr.h>
 #include <evbarm/ifpga/ifpgavar.h>
 #include <evbarm/ifpga/ifpgamem.h>
 #include <evbarm/ifpga/ifpgareg.h>
 #define PL030_RTC_SIZE	0x14
 struct plrtc_softc {
 	struct device		    sc_dev;
 	bus_space_tag_t		    sc_iot;
 	bus_space_handle_t	    sc_ioh;
 	struct todr_chip_handle     sc_todr;
 };
-static int  plrtc_probe  (struct device *, struct cfdata *, void *);
+static int  plrtc_probe  (device_t, cfdata_t, void *);
-static void plrtc_attach (struct device *, struct device *, void *);
+static void plrtc_attach (device_t, device_t, void *);
-CFATTACH_DECL(plrtc, sizeof(struct plrtc_softc),
+CFATTACH_DECL_NEW(plrtc, sizeof(struct plrtc_softc),
     plrtc_probe, plrtc_attach, NULL, NULL);
 static int
 plrtc_gettime(todr_chip_handle_t todr, volatile struct timeval *tv)
+{
 	struct plrtc_softc *sc;
  	sc = (struct plrtc_softc *)todr->cookie;
 	tv->tv_sec = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IFPGA_RTC_DR);
 	/* initialize tv_usec? */
 	return 0;
+}
 static int
 plrtc_settime(todr_chip_handle_t todr, volatile struct timeval *tv)
+{
 	struct plrtc_softc *sc;
  	sc = (struct plrtc_softc *)todr->cookie;
 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, IFPGA_RTC_LR, tv->tv_sec);
 	return 0;
+}
 static int
-plrtc_probe(struct device *parent, struct cfdata *cf, void *aux)
+plrtc_probe(device_t parent, cfdata_t cf, void *aux)
+{
 	return 1;
+}
 static void
-plrtc_attach(struct device *parent, struct device *self, void *aux)
+plrtc_attach(device_t parent, device_t self, void *aux)
+{
 	struct ifpga_attach_args *ifa = aux;
-	struct plrtc_softc *sc = (struct plrtc_softc *)self;
+	struct plrtc_softc *sc = device_private(self);
 	sc->sc_iot = ifa->ifa_iot;
 	if (bus_space_map(ifa->ifa_iot, ifa->ifa_addr, PL030_RTC_SIZE, 0,
 	    &sc->sc_ioh)) {
-		printf("%s: unable to map device\n", sc->sc_dev.dv_xname);
+		printf("%s: unable to map device\n", device_xname(self));
 		return;
+	}
 	memset(&sc->sc_todr, 0, sizeof(struct todr_chip_handle));
 	sc->sc_todr.cookie = sc;
 	sc->sc_todr.todr_gettime = plrtc_gettime;
 	sc->sc_todr.todr_settime = plrtc_settime;
 	todr_attach( &sc->sc_todr );
 	printf("\n");
+}

 @@ -1,14 +1,14 @@
-/*	$NetBSD: ifpgavar.h,v 1.4 2005/12/11 12:17:09 christos Exp $ */
+/*	$NetBSD: ifpgavar.h,v 1.5 2009/07/21 16:04:16 dyoung Exp $ */
 /*
  * Copyright (c) 2001 ARM Ltd
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -35,27 +35,26 @@
 #include <machine/bus.h>
 /* We statically map the UARTS at boot so that we can access the console
    before we've probed for the IFPGA. */
 #define UART0_BOOT_BASE		0xfde00000
 #define UART1_BOOT_BASE		0xfdf00000
 #define IFPGA_UART0		0x06000000	/* Uart 0 */
 #define IFPGA_UART1		0x07000000	/* Uart 1 */
 typedef paddr_t ifpga_addr_t;
 struct ifpga_softc {
 	struct device		sc_dev;		/* Device node */
 	bus_space_tag_t		sc_iot;		/* Bus tag */
 	bus_space_handle_t	sc_sc_ioh;	/* System Controller handle */
 	bus_space_handle_t	sc_cm_ioh;	/* Core Module handle */
 	bus_space_handle_t	sc_tmr_ioh;	/* Timers handle */
 	bus_space_handle_t	sc_irq_ioh;	/* IRQ controller handle */
 	/* Clock variables.  */
 	int			sc_statclock_count;
 	int			sc_clock_count;
 	int			sc_clock_ticks_per_256us;
 	void *			sc_clockintr;
 	void *			sc_statclockintr;
 };