| @@ -1,14 +1,14 @@ | | | @@ -1,14 +1,14 @@ |
1 | /* $NetBSD: ichlpcib.c,v 1.14.4.1 2009/04/07 23:28:30 snj Exp $ */ | | 1 | /* $NetBSD: ichlpcib.c,v 1.14.4.2 2009/08/16 00:16:28 snj Exp $ */ |
2 | | | 2 | |
3 | /*- | | 3 | /*- |
4 | * Copyright (c) 2004 The NetBSD Foundation, Inc. | | 4 | * Copyright (c) 2004 The NetBSD Foundation, Inc. |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation | | 7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Minoura Makoto and Matthew R. Green. | | 8 | * by Minoura Makoto and Matthew R. Green. |
9 | * | | 9 | * |
10 | * Redistribution and use in source and binary forms, with or without | | 10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions | | 11 | * modification, are permitted provided that the following conditions |
12 | * are met: | | 12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright | | 13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. | | 14 | * notice, this list of conditions and the following disclaimer. |
| @@ -29,27 +29,27 @@ | | | @@ -29,27 +29,27 @@ |
29 | * POSSIBILITY OF SUCH DAMAGE. | | 29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ | | 30 | */ |
31 | | | 31 | |
32 | /* | | 32 | /* |
33 | * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver | | 33 | * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver |
34 | * | | 34 | * |
35 | * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has | | 35 | * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has |
36 | * some power management and monitoring functions. | | 36 | * some power management and monitoring functions. |
37 | * Currently we support the watchdog timer, SpeedStep (on some systems) | | 37 | * Currently we support the watchdog timer, SpeedStep (on some systems) |
38 | * and the power management timer. | | 38 | * and the power management timer. |
39 | */ | | 39 | */ |
40 | | | 40 | |
41 | #include <sys/cdefs.h> | | 41 | #include <sys/cdefs.h> |
42 | __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.14.4.1 2009/04/07 23:28:30 snj Exp $"); | | 42 | __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.14.4.2 2009/08/16 00:16:28 snj Exp $"); |
43 | | | 43 | |
44 | #include <sys/types.h> | | 44 | #include <sys/types.h> |
45 | #include <sys/param.h> | | 45 | #include <sys/param.h> |
46 | #include <sys/systm.h> | | 46 | #include <sys/systm.h> |
47 | #include <sys/device.h> | | 47 | #include <sys/device.h> |
48 | #include <sys/sysctl.h> | | 48 | #include <sys/sysctl.h> |
49 | #include <sys/timetc.h> | | 49 | #include <sys/timetc.h> |
50 | #include <machine/bus.h> | | 50 | #include <machine/bus.h> |
51 | | | 51 | |
52 | #include <dev/pci/pcivar.h> | | 52 | #include <dev/pci/pcivar.h> |
53 | #include <dev/pci/pcireg.h> | | 53 | #include <dev/pci/pcireg.h> |
54 | #include <dev/pci/pcidevs.h> | | 54 | #include <dev/pci/pcidevs.h> |
55 | | | 55 | |
| @@ -403,64 +403,65 @@ tcotimer_configure(device_t self) | | | @@ -403,64 +403,65 @@ tcotimer_configure(device_t self) |
403 | | | 403 | |
404 | aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); | | 404 | aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); |
405 | } | | 405 | } |
406 | | | 406 | |
407 | /* | | 407 | /* |
408 | * Sysmon watchdog callbacks. | | 408 | * Sysmon watchdog callbacks. |
409 | */ | | 409 | */ |
410 | static int | | 410 | static int |
411 | tcotimer_setmode(struct sysmon_wdog *smw) | | 411 | tcotimer_setmode(struct sysmon_wdog *smw) |
412 | { | | 412 | { |
413 | struct lpcib_softc *sc = smw->smw_cookie; | | 413 | struct lpcib_softc *sc = smw->smw_cookie; |
414 | unsigned int period; | | 414 | unsigned int period; |
415 | uint16_t ich6period = 0; | | 415 | uint16_t ich6period = 0; |
| | | 416 | uint8_t ich5period = 0; |
416 | | | 417 | |
417 | if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { | | 418 | if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { |
418 | /* Stop the TCO timer. */ | | 419 | /* Stop the TCO timer. */ |
419 | tcotimer_stop(sc); | | 420 | tcotimer_stop(sc); |
420 | } else { | | 421 | } else { |
421 | /* | | 422 | /* |
422 | * ICH6 or newer are limited to 2s min and 613s max. | | 423 | * ICH6 or newer are limited to 2s min and 613s max. |
423 | * ICH5 or older are limited to 4s min and 39s max. | | 424 | * ICH5 or older are limited to 4s min and 39s max. |
424 | */ | | 425 | */ |
| | | 426 | period = lpcib_tcotimer_second_to_tick(smw->smw_period); |
425 | if (sc->sc_has_rcba) { | | 427 | if (sc->sc_has_rcba) { |
426 | if (smw->smw_period < LPCIB_TCOTIMER2_MIN_TICK || | | 428 | if (period < LPCIB_TCOTIMER2_MIN_TICK || |
427 | smw->smw_period > LPCIB_TCOTIMER2_MAX_TICK) | | 429 | period > LPCIB_TCOTIMER2_MAX_TICK) |
428 | return EINVAL; | | 430 | return EINVAL; |
429 | } else { | | 431 | } else { |
430 | if (smw->smw_period < LPCIB_TCOTIMER_MIN_TICK || | | 432 | if (period < LPCIB_TCOTIMER_MIN_TICK || |
431 | smw->smw_period > LPCIB_TCOTIMER_MAX_TICK) | | 433 | period > LPCIB_TCOTIMER_MAX_TICK) |
432 | return EINVAL; | | 434 | return EINVAL; |
433 | } | | 435 | } |
434 | period = lpcib_tcotimer_second_to_tick(smw->smw_period); | | | |
435 | | | 436 | |
436 | /* Stop the TCO timer, */ | | 437 | /* Stop the TCO timer, */ |
437 | tcotimer_stop(sc); | | 438 | tcotimer_stop(sc); |
438 | | | 439 | |
439 | /* set the timeout, */ | | 440 | /* set the timeout, */ |
440 | if (sc->sc_has_rcba) { | | 441 | if (sc->sc_has_rcba) { |
441 | /* ICH6 or newer */ | | 442 | /* ICH6 or newer */ |
442 | ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, | | 443 | ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, |
443 | LPCIB_TCO_TMR2); | | 444 | LPCIB_TCO_TMR2); |
444 | ich6period &= 0xfc00; | | 445 | ich6period &= 0xfc00; |
445 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, | | 446 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, |
446 | LPCIB_TCO_TMR2, ich6period | period); | | 447 | LPCIB_TCO_TMR2, ich6period | period); |
447 | } else { | | 448 | } else { |
448 | /* ICH5 or older */ | | 449 | /* ICH5 or older */ |
449 | period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, | | 450 | ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, |
450 | LPCIB_TCO_TMR); | | 451 | LPCIB_TCO_TMR); |
451 | period &= 0xc0; | | 452 | ich5period &= 0xc0; |
452 | bus_space_write_1(sc->sc_iot, sc->sc_ioh, | | 453 | bus_space_write_1(sc->sc_iot, sc->sc_ioh, |
453 | LPCIB_TCO_TMR, period); | | 454 | LPCIB_TCO_TMR, ich5period | period); |
454 | } | | 455 | } |
455 | | | 456 | |
456 | /* and start/reload the timer. */ | | 457 | /* and start/reload the timer. */ |
457 | tcotimer_start(sc); | | 458 | tcotimer_start(sc); |
458 | tcotimer_tickle(smw); | | 459 | tcotimer_tickle(smw); |
459 | } | | 460 | } |
460 | | | 461 | |
461 | return 0; | | 462 | return 0; |
462 | } | | 463 | } |
463 | | | 464 | |
464 | static int | | 465 | static int |
465 | tcotimer_tickle(struct sysmon_wdog *smw) | | 466 | tcotimer_tickle(struct sysmon_wdog *smw) |
466 | { | | 467 | { |