Thu Aug 20 07:44:50 2009 UTC ()
Add a MIPS3_PG_TO_CCA() macro to get the CCA out of the saved page attributes.


(matt)
diff -r1.23 -r1.23.38.1 src/sys/arch/mips/include/mips3_pte.h
cvs diff -r1.23 -r1.23.38.1 src/sys/arch/mips/include/mips3_pte.h (expand / switch to unified diff)

--- src/sys/arch/mips/include/mips3_pte.h 2007/10/17 19:55:37 1.23
+++ src/sys/arch/mips/include/mips3_pte.h 2009/08/20 07:44:50 1.23.38.1
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: mips3_pte.h,v 1.23 2007/10/17 19:55:37 garbled Exp $ */ 1/* $NetBSD: mips3_pte.h,v 1.23.38.1 2009/08/20 07:44:50 matt Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1992, 1993 4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved. 5 * The Regents of the University of California. All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to Berkeley by 7 * This code is derived from software contributed to Berkeley by
8 * the Systems Programming Group of the University of Utah Computer 8 * the Systems Programming Group of the University of Utah Computer
9 * Science Department and Ralph Campbell. 9 * Science Department and Ralph Campbell.
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -116,26 +116,27 @@ struct tlb { @@ -116,26 +116,27 @@ struct tlb {
116#define MIPS3_PG_RO 0x40000000 /* SW */ 116#define MIPS3_PG_RO 0x40000000 /* SW */
117 117
118#define MIPS3_PG_SVPN 0xfffff000 /* Software page no mask */ 118#define MIPS3_PG_SVPN 0xfffff000 /* Software page no mask */
119#define MIPS3_PG_HVPN 0xffffe000 /* Hardware page no mask */ 119#define MIPS3_PG_HVPN 0xffffe000 /* Hardware page no mask */
120#define MIPS3_PG_ODDPG 0x00001000 /* Odd even pte entry */ 120#define MIPS3_PG_ODDPG 0x00001000 /* Odd even pte entry */
121#define MIPS3_PG_ASID 0x000000ff /* Address space ID */ 121#define MIPS3_PG_ASID 0x000000ff /* Address space ID */
122#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */ 122#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
123#define MIPS3_PG_V 0x00000002 /* Valid */ 123#define MIPS3_PG_V 0x00000002 /* Valid */
124#define MIPS3_PG_NV 0x00000000 124#define MIPS3_PG_NV 0x00000000
125#define MIPS3_PG_D 0x00000004 /* Dirty */ 125#define MIPS3_PG_D 0x00000004 /* Dirty */
126#define MIPS3_PG_ATTR 0x0000003f 126#define MIPS3_PG_ATTR 0x0000003f
127 127
128#define MIPS3_CCA_TO_PG(cca) ((cca) << 3) 128#define MIPS3_CCA_TO_PG(cca) ((cca) << 3)
 129#define MIPS3_PG_TO_CCA(cca) (((cca) >> 3) & 7)
129 130
130#define MIPS3_PG_UNCACHED MIPS3_CCA_TO_PG(2) 131#define MIPS3_PG_UNCACHED MIPS3_CCA_TO_PG(2)
131#ifdef HPCMIPS_L1CACHE_DISABLE /* MIPS3_L1CACHE_DISABLE */ 132#ifdef HPCMIPS_L1CACHE_DISABLE /* MIPS3_L1CACHE_DISABLE */
132#define MIPS3_PG_CACHED MIPS3_PG_UNCACHED /* XXX: brain damaged!!! */ 133#define MIPS3_PG_CACHED MIPS3_PG_UNCACHED /* XXX: brain damaged!!! */
133#else /* HPCMIPS_L1CACHE_DISABLE */ 134#else /* HPCMIPS_L1CACHE_DISABLE */
134#define MIPS3_PG_CACHED mips3_pg_cached 135#define MIPS3_PG_CACHED mips3_pg_cached
135#define MIPS3_DEFAULT_PG_CACHED MIPS3_CCA_TO_PG(3) 136#define MIPS3_DEFAULT_PG_CACHED MIPS3_CCA_TO_PG(3)
136#endif /* ! HPCMIPS_L1CACHE_DISABLE */ 137#endif /* ! HPCMIPS_L1CACHE_DISABLE */
137#define MIPS3_PG_CACHEMODE MIPS3_CCA_TO_PG(7) 138#define MIPS3_PG_CACHEMODE MIPS3_CCA_TO_PG(7)
138 139
139/* Write protected */ 140/* Write protected */
140#define MIPS3_PG_ROPAGE (MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED) 141#define MIPS3_PG_ROPAGE (MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED)
141 142