Mon Sep 7 21:34:47 2009 UTC ()
Use intptr_t in MIPS_KSEGx_P()
Use uintptr_t in MIPS_XKPHYS*


(matt)
diff -r1.74.28.6 -r1.74.28.7 src/sys/arch/mips/include/cpuregs.h
cvs diff -r1.74.28.6 -r1.74.28.7 src/sys/arch/mips/include/cpuregs.h (expand / switch to unified diff)

--- src/sys/arch/mips/include/cpuregs.h 2009/09/06 22:36:16 1.74.28.6
+++ src/sys/arch/mips/include/cpuregs.h 2009/09/07 21:34:47 1.74.28.7
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpuregs.h,v 1.74.28.6 2009/09/06 22:36:16 matt Exp $ */ 1/* $NetBSD: cpuregs.h,v 1.74.28.7 2009/09/07 21:34:47 matt Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1992, 1993 4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved. 5 * The Regents of the University of California. All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to Berkeley by 7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem. 8 * Ralph Campbell and Rick Macklem.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -93,43 +93,43 @@ @@ -93,43 +93,43 @@
93#define MIPS_KSEG1_START -0x60000000L /* 0xa0000000 */ 93#define MIPS_KSEG1_START -0x60000000L /* 0xa0000000 */
94#define MIPS_KSEG2_START -0x40000000L /* 0xc0000000 */ 94#define MIPS_KSEG2_START -0x40000000L /* 0xc0000000 */
95#define MIPS_MAX_MEM_ADDR -0x42000000L /* 0xbe000000 */ 95#define MIPS_MAX_MEM_ADDR -0x42000000L /* 0xbe000000 */
96#define MIPS_RESERVED_ADDR -0x40380000L /* 0xbfc80000 */ 96#define MIPS_RESERVED_ADDR -0x40380000L /* 0xbfc80000 */
97#endif 97#endif
98 98
99#define MIPS_PHYS_MASK 0x1fffffff 99#define MIPS_PHYS_MASK 0x1fffffff
100 100
101#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 101#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
102#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG0_START) 102#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG0_START)
103#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 103#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
104#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG1_START) 104#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG1_START)
105 105
106#define MIPS_KSEG0_P(x) (((uintptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG0_START) 106#define MIPS_KSEG0_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG0_START)
107#define MIPS_KSEG1_P(x) (((uintptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG1_START) 107#define MIPS_KSEG1_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG1_START)
108#define MIPS_KSEG2_P(x) ((uintptr_t)MIPS_KSEG2_START <= (uintptr_t)(x)) 108#define MIPS_KSEG2_P(x) ((uintptr_t)MIPS_KSEG2_START <= (uintptr_t)(x))
109 109
110/* Map virtual address to index in mips3 r4k virtually-indexed cache */ 110/* Map virtual address to index in mips3 r4k virtually-indexed cache */
111#define MIPS3_VA_TO_CINDEX(x) \ 111#define MIPS3_VA_TO_CINDEX(x) \
112 (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START)  112 (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START)
113 113
114#define MIPS_XSEG_MASK (0x3fffffffffffffffLL) 114#define MIPS_XSEG_MASK (0x3fffffffffffffffLL)
115#define MIPS_XKSEG_START (0x3ULL << 62) 115#define MIPS_XKSEG_START (0x3ULL << 62)
116#define MIPS_XKSEG_P(x) (((uint64_t)(x) >> 62) == 3) 116#define MIPS_XKSEG_P(x) (((uint64_t)(x) >> 62) == 3)
117 117
118#define MIPS_XKPHYS_START (0x2ULL << 62) 118#define MIPS_XKPHYS_START (0x2ULL << 62)
119#define MIPS_PHYS_TO_XKPHYS(cca,x) \ 119#define MIPS_PHYS_TO_XKPHYS(cca,x) \
120 (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x)) 120 (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x))
121#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffLL) 121#define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & 0x0effffffffffffffLL)
122#define MIPS_XKPHYS_TO_CCA(x) (((x) >> 59) & 7) 122#define MIPS_XKPHYS_TO_CCA(x) (((uintptr_t)(x) >> 59) & 7)
123#define MIPS_XKPHYS_P(x) (((uint64_t)(x) >> 62) == 2) 123#define MIPS_XKPHYS_P(x) (((uint64_t)(x) >> 62) == 2)
124 124
125#define CCA_UNCACHED 2 125#define CCA_UNCACHED 2
126#define CCA_CACHEABLE 3 /* cacheable non-coherent */ 126#define CCA_CACHEABLE 3 /* cacheable non-coherent */
127 127
128/* CPU dependent mtc0 hazard hook */ 128/* CPU dependent mtc0 hazard hook */
129#define COP0_SYNC /* nothing */ 129#define COP0_SYNC /* nothing */
130#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 130#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
131 131
132/* 132/*
133 * The bits in the cause register. 133 * The bits in the cause register.
134 * 134 *
135 * Bits common to r3000 and r4000: 135 * Bits common to r3000 and r4000: