Thu Sep 17 16:13:32 2009 UTC ()
fix a typo of register bit name.


(bsh)
diff -r1.2 -r1.3 src/sys/arch/arm/imx/imxuartreg.h
cvs diff -r1.2 -r1.3 src/sys/arch/arm/imx/imxuartreg.h (expand / switch to unified diff)

--- src/sys/arch/arm/imx/imxuartreg.h 2008/04/27 18:58:44 1.2
+++ src/sys/arch/arm/imx/imxuartreg.h 2009/09/17 16:13:32 1.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $Id: imxuartreg.h,v 1.2 2008/04/27 18:58:44 matt Exp $ */ 1/* $Id: imxuartreg.h,v 1.3 2009/09/17 16:13:32 bsh Exp $ */
2/* 2/*
3 * register definitions for Freescale i.MX31 and i.MX31L UARTs 3 * register definitions for Freescale i.MX31 and i.MX31L UARTs
4 * 4 *
5 * UART specification obtained from: 5 * UART specification obtained from:
6 * MCIMX31 and MCIMX31L Application Processors 6 * MCIMX31 and MCIMX31L Application Processors
7 * Reference Manual 7 * Reference Manual
8 * MCIMC31RM 8 * MCIMC31RM
9 * Rev. 2.3 9 * Rev. 2.3
10 * 1/2007 10 * 1/2007
11 */ 11 */
12 12
13 13
14/* 14/*
@@ -98,27 +98,27 @@ @@ -98,27 +98,27 @@
98#define IMX_UCR1_ADBR BIT(14) /* rw */ 98#define IMX_UCR1_ADBR BIT(14) /* rw */
99#define IMX_UCR1_ADEN BIT(15) /* rw */ 99#define IMX_UCR1_ADEN BIT(15) /* rw */
100 100
101/* 101/*
102 * IMX_UCR2 bits 102 * IMX_UCR2 bits
103 */ 103 */
104#define IMX_UCR2_SRST BIT(0) /* rw */ 104#define IMX_UCR2_SRST BIT(0) /* rw */
105#define IMX_UCR2_RXEN BIT(1) /* rw */ 105#define IMX_UCR2_RXEN BIT(1) /* rw */
106#define IMX_UCR2_TXEN BIT(2) /* rw */ 106#define IMX_UCR2_TXEN BIT(2) /* rw */
107#define IMX_UCR2_ATEN BIT(3) /* rw */ 107#define IMX_UCR2_ATEN BIT(3) /* rw */
108#define IMX_UCR2_RTSEN BIT(4) /* rw */ 108#define IMX_UCR2_RTSEN BIT(4) /* rw */
109#define IMX_UCR2_WS BIT(5) /* rw */ 109#define IMX_UCR2_WS BIT(5) /* rw */
110#define IMX_UCR2_STPB BIT(6) /* rw */ 110#define IMX_UCR2_STPB BIT(6) /* rw */
111#define IMX_UCR2_PRDE BIT(7) /* rw */ 111#define IMX_UCR2_PROE BIT(7) /* rw */
112#define IMX_UCR2_PREN BIT(8) /* rw */ 112#define IMX_UCR2_PREN BIT(8) /* rw */
113#define IMX_UCR2_RTEC BITS(10,9) /* rw */ 113#define IMX_UCR2_RTEC BITS(10,9) /* rw */
114#define IMX_UCR2_ESCEN BIT(11) /* rw */ 114#define IMX_UCR2_ESCEN BIT(11) /* rw */
115#define IMX_UCR2_CTS BIT(12) /* rw */ 115#define IMX_UCR2_CTS BIT(12) /* rw */
116#define IMX_UCR2_CTSC BIT(13) /* rw */ 116#define IMX_UCR2_CTSC BIT(13) /* rw */
117#define IMX_UCR2_IRTS BIT(14) /* rw */ 117#define IMX_UCR2_IRTS BIT(14) /* rw */
118#define IMX_UCR2_ESCI BIT(15) /* rw */ 118#define IMX_UCR2_ESCI BIT(15) /* rw */
119 119
120/* 120/*
121 * IMX_UCR3 bits 121 * IMX_UCR3 bits
122 */ 122 */
123#define IMX_UCR3_ACIEN BIT(0) /* rw */ 123#define IMX_UCR3_ACIEN BIT(0) /* rw */
124#define IMX_UCR3_INVT BIT(1) /* rw */ 124#define IMX_UCR3_INVT BIT(1) /* rw */