Sat Nov 14 21:49:05 2009 UTC ()
Add MIPS_SR_PX


(matt)
diff -r1.74.28.11 -r1.74.28.12 src/sys/arch/mips/include/cpuregs.h
cvs diff -r1.74.28.11 -r1.74.28.12 src/sys/arch/mips/include/cpuregs.h (expand / switch to unified diff)

--- src/sys/arch/mips/include/cpuregs.h 2009/11/13 05:23:23 1.74.28.11
+++ src/sys/arch/mips/include/cpuregs.h 2009/11/14 21:49:05 1.74.28.12
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpuregs.h,v 1.74.28.11 2009/11/13 05:23:23 cliff Exp $ */ 1/* $NetBSD: cpuregs.h,v 1.74.28.12 2009/11/14 21:49:05 matt Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1992, 1993 4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved. 5 * The Regents of the University of California. All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to Berkeley by 7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem. 8 * Ralph Campbell and Rick Macklem.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -232,26 +232,27 @@ @@ -232,26 +232,27 @@
232#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 232#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
233 233
234/* 234/*
235 * R4000 status register bit definitons, 235 * R4000 status register bit definitons,
236 * where different from r2000/r3000. 236 * where different from r2000/r3000.
237 */ 237 */
238#define MIPS3_SR_XX 0x80000000 238#define MIPS3_SR_XX 0x80000000
239#define MIPS3_SR_RP 0x08000000 239#define MIPS3_SR_RP 0x08000000
240#define MIPS3_SR_FR 0x04000000 240#define MIPS3_SR_FR 0x04000000
241#define MIPS3_SR_RE 0x02000000 241#define MIPS3_SR_RE 0x02000000
242 242
243#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 243#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
244#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 244#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
 245#define MIPS3_SR_PX 0x00800000 /* MIPS64 */
245#define MIPS3_SR_SR 0x00100000 246#define MIPS3_SR_SR 0x00100000
246#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ 247#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
247#define MIPS3_SR_DIAG_CH 0x00040000 248#define MIPS3_SR_DIAG_CH 0x00040000
248#define MIPS3_SR_DIAG_CE 0x00020000 249#define MIPS3_SR_DIAG_CE 0x00020000
249#define MIPS3_SR_DIAG_PE 0x00010000 250#define MIPS3_SR_DIAG_PE 0x00010000
250#define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */ 251#define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */
251#define MIPS3_SR_KX 0x00000080 252#define MIPS3_SR_KX 0x00000080
252#define MIPS3_SR_SX 0x00000040 253#define MIPS3_SR_SX 0x00000040
253#define MIPS3_SR_UX 0x00000020 254#define MIPS3_SR_UX 0x00000020
254#define MIPS3_SR_KSU_MASK 0x00000018 255#define MIPS3_SR_KSU_MASK 0x00000018
255#define MIPS3_SR_KSU_USER 0x00000010 256#define MIPS3_SR_KSU_USER 0x00000010
256#define MIPS3_SR_KSU_SUPER 0x00000008 257#define MIPS3_SR_KSU_SUPER 0x00000008
257#define MIPS3_SR_KSU_KERNEL 0x00000000 258#define MIPS3_SR_KSU_KERNEL 0x00000000