Mon Nov 30 01:58:49 2009 UTC ()
stablize UP USIII support by blocking interrupts around sp_tlb_flush_pte()
i was seeing stack corruption while taking an interrupt in this function.

get USIII SMP mostly working by implementing the cheetah version of
sparc64_ipi_flush_pte().

SMP support is still not entirely stable.  i can reproducably get a:

	panic: fpusave_lwp ipi didn't

while running build.sh, when an awk process is exiting.  other simple
heavy work loads do not crash for me right now.


(mrg)
diff -r1.297 -r1.298 src/sys/arch/sparc64/sparc64/locore.s
cvs diff -r1.297 -r1.298 src/sys/arch/sparc64/sparc64/locore.s (expand / switch to unified diff)

--- src/sys/arch/sparc64/sparc64/locore.s 2009/11/30 01:45:04 1.297
+++ src/sys/arch/sparc64/sparc64/locore.s 2009/11/30 01:58:49 1.298
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: locore.s,v 1.297 2009/11/30 01:45:04 mrg Exp $ */ 1/* $NetBSD: locore.s,v 1.298 2009/11/30 01:58:49 mrg Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1996-2002 Eduardo Horvath 4 * Copyright (c) 1996-2002 Eduardo Horvath
5 * Copyright (c) 1996 Paul Kranenburg 5 * Copyright (c) 1996 Paul Kranenburg
6 * Copyright (c) 1996 6 * Copyright (c) 1996
7 * The President and Fellows of Harvard College. 7 * The President and Fellows of Harvard College.
8 * All rights reserved. 8 * All rights reserved.
9 * Copyright (c) 1992, 1993 9 * Copyright (c) 1992, 1993
10 * The Regents of the University of California. 10 * The Regents of the University of California.
11 * All rights reserved. 11 * All rights reserved.
12 * 12 *
13 * This software was developed by the Computer Systems Engineering group 13 * This software was developed by the Computer Systems Engineering group
14 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 14 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
@@ -3807,27 +3807,46 @@ ENTRY(sparc64_ipi_flush_pte) @@ -3807,27 +3807,46 @@ ENTRY(sparc64_ipi_flush_pte)
3807 or %g2, DEMAP_PAGE_SECONDARY, %g2 ! Demap page from secondary context only 3807 or %g2, DEMAP_PAGE_SECONDARY, %g2 ! Demap page from secondary context only
3808 stxa %g2, [%g2] ASI_DMMU_DEMAP ! Do the demap 3808 stxa %g2, [%g2] ASI_DMMU_DEMAP ! Do the demap
3809 stxa %g2, [%g2] ASI_IMMU_DEMAP ! to both TLBs 3809 stxa %g2, [%g2] ASI_IMMU_DEMAP ! to both TLBs
3810#ifdef _LP64 3810#ifdef _LP64
3811 srl %g2, 0, %g2 ! and make sure it's both 32- and 64-bit entries 3811 srl %g2, 0, %g2 ! and make sure it's both 32- and 64-bit entries
3812 stxa %g2, [%g2] ASI_DMMU_DEMAP ! Do the demap 3812 stxa %g2, [%g2] ASI_DMMU_DEMAP ! Do the demap
3813 stxa %g2, [%g2] ASI_IMMU_DEMAP ! Do the demap 3813 stxa %g2, [%g2] ASI_IMMU_DEMAP ! Do the demap
3814#endif 3814#endif
3815 flush %g7 3815 flush %g7
3816 stxa %g6, [%g5] ASI_DMMU ! Restore secondary context 3816 stxa %g6, [%g5] ASI_DMMU ! Restore secondary context
3817 membar #Sync 3817 membar #Sync
3818 IPIEVC_INC(IPI_EVCNT_TLB_PTE,%g2,%g3) 3818 IPIEVC_INC(IPI_EVCNT_TLB_PTE,%g2,%g3)
3819#else 3819#else
3820 WRITEME 3820
 3821 andn %g2, 0xfff, %g2 ! drop unused va bits
 3822 mov CTX_PRIMARY, %g5
 3823 ldxa [%g5] ASI_DMMU, %g6 ! Save secondary context
 3824 sethi %hi(KERNBASE), %g7
 3825 membar #LoadStore
 3826 stxa %g3, [%g5] ASI_DMMU ! Insert context to demap
 3827 membar #Sync
 3828 or %g2, DEMAP_PAGE_PRIMARY, %g2
 3829 stxa %g2, [%g2] ASI_DMMU_DEMAP ! Do the demap
 3830 stxa %g2, [%g2] ASI_IMMU_DEMAP ! to both TLBs
 3831#ifdef _LP64
 3832 srl %g2, 0, %g2 ! and make sure it's both 32- and 64-bit entries
 3833 stxa %g2, [%g2] ASI_DMMU_DEMAP ! Do the demap
 3834 stxa %g2, [%g2] ASI_IMMU_DEMAP ! Do the demap
 3835#endif
 3836 flush %g7
 3837 stxa %g6, [%g5] ASI_DMMU ! Restore primary context
 3838 membar #Sync
 3839 IPIEVC_INC(IPI_EVCNT_TLB_PTE,%g2,%g3)
3821#endif 3840#endif
3822  3841
3823 ba,a ret_from_intr_vector 3842 ba,a ret_from_intr_vector
3824 nop 3843 nop
3825 3844
3826 3845
3827/* 3846/*
3828 * Secondary CPU bootstrap code. 3847 * Secondary CPU bootstrap code.
3829 */ 3848 */
3830 .text 3849 .text
3831 .align 32 3850 .align 32
38321: rd %pc, %l0 38511: rd %pc, %l0
3833 LDULNG [%l0 + (4f-1b)], %l1 3852 LDULNG [%l0 + (4f-1b)], %l1
@@ -5398,56 +5417,69 @@ ENTRY(sp_tlb_flush_pte) @@ -5398,56 +5417,69 @@ ENTRY(sp_tlb_flush_pte)
5398 stxa %o0, [%o0] ASI_DMMU_DEMAP ! Do the demap 5417 stxa %o0, [%o0] ASI_DMMU_DEMAP ! Do the demap
5399 stxa %o0, [%o0] ASI_IMMU_DEMAP ! Do the demap 5418 stxa %o0, [%o0] ASI_IMMU_DEMAP ! Do the demap
5400#endif 5419#endif
5401 flush %o4 5420 flush %o4
5402 stxa %o5, [%o2] ASI_DMMU ! Restore secondary context 5421 stxa %o5, [%o2] ASI_DMMU ! Restore secondary context
5403 membar #Sync 5422 membar #Sync
5404 retl 5423 retl
5405#ifdef MULTIPROCESSOR 5424#ifdef MULTIPROCESSOR
5406 wrpr %o3, %pstate ! restore interrupts 5425 wrpr %o3, %pstate ! restore interrupts
5407#else 5426#else
5408 nop 5427 nop
5409#endif 5428#endif
5410#else 5429#else
5411#ifdef MULTIPROCESSOR 5430
5412 WRITEME 5431 ! %o0 = VA [in]
5413#endif 5432 ! %o1 = ctx value [in] / KERNBASE
 5433 ! %o2 = CTX_PRIMARY
 5434 ! %o3 = saved %tl
 5435 ! %o4 = saved %pstate
 5436 ! %o5 = saved primary ctx
 5437
 5438 ! Need this for UP as well
 5439 rdpr %pstate, %o4
 5440 andn %o4, PSTATE_IE, %o3 ! disable interrupts
 5441 wrpr %o3, 0, %pstate
 5442
5414 !! 5443 !!
5415 !! Cheetahs do not support flushing the IMMU from secondary context 5444 !! Cheetahs do not support flushing the IMMU from secondary context
5416 !! 5445 !!
5417 rdpr %tl, %o3 5446 rdpr %tl, %o3
5418 mov CTX_PRIMARY, %o2 5447 mov CTX_PRIMARY, %o2
5419 brnz,pt %o3, 1f 5448 brnz,pt %o3, 1f
5420 andn %o0, 0xfff, %o0 ! drop unused va bits 5449 andn %o0, 0xfff, %o0 ! drop unused va bits
5421 wrpr %g0, 1, %tl ! Make sure we're NUCLEUS 5450 wrpr %g0, 1, %tl ! Make sure we're NUCLEUS
54221:  54511:
5423 ldxa [%o2] ASI_DMMU, %o5 ! Save primary context 5452 ldxa [%o2] ASI_DMMU, %o5 ! Save primary context
5424 sethi %hi(KERNBASE), %o4 
5425 membar #LoadStore 5453 membar #LoadStore
5426 stxa %o1, [%o2] ASI_DMMU ! Insert context to demap 5454 stxa %o1, [%o2] ASI_DMMU ! Insert context to demap
 5455 sethi %hi(KERNBASE), %o1
5427 membar #Sync 5456 membar #Sync
5428 or %o0, DEMAP_PAGE_PRIMARY, %o0 5457 or %o0, DEMAP_PAGE_PRIMARY, %o0
5429 stxa %o0, [%o0] ASI_DMMU_DEMAP ! Do the demap 5458 stxa %o0, [%o0] ASI_DMMU_DEMAP ! Do the demap
5430 stxa %o0, [%o0] ASI_IMMU_DEMAP ! to both TLBs 5459 stxa %o0, [%o0] ASI_IMMU_DEMAP ! to both TLBs
 5460#ifdef _LP64
5431 srl %o0, 0, %o0 ! and make sure it's both 32- and 64-bit entries 5461 srl %o0, 0, %o0 ! and make sure it's both 32- and 64-bit entries
5432 stxa %o0, [%o0] ASI_DMMU_DEMAP ! Do the demap 5462 stxa %o0, [%o0] ASI_DMMU_DEMAP ! Do the demap
5433 stxa %o0, [%o0] ASI_IMMU_DEMAP ! Do the demap 5463 stxa %o0, [%o0] ASI_IMMU_DEMAP ! Do the demap
5434 flush %o4 5464#endif
 5465 flush %o1
5435 stxa %o5, [%o2] ASI_DMMU ! Restore primary context 5466 stxa %o5, [%o2] ASI_DMMU ! Restore primary context
5436 brz,pt %o3, 1f 5467 brz,pt %o3, 1f
5437 flush %o4 5468 flush %o1
5438 retl 5469 retl
5439 nop 5470 nop
54401:  54711:
 5472 wrpr %o4, %pstate ! restore interrupts
5441 retl 5473 retl
5442 wrpr %g0, %o3, %tl ! Return to kernel mode. 5474 wrpr %g0, %o3, %tl ! Return to kernel mode.
5443#endif 5475#endif
5444 5476
5445 5477
5446/* 5478/*
5447 * sp_tlb_flush_all(void) 5479 * sp_tlb_flush_all(void)
5448 * 5480 *
5449 * Flush all user TLB entries from both IMMU and DMMU. 5481 * Flush all user TLB entries from both IMMU and DMMU.
5450 */ 5482 */
5451 .align 8 5483 .align 8
5452ENTRY(sp_tlb_flush_all) 5484ENTRY(sp_tlb_flush_all)
5453#ifdef SPITFIRE 5485#ifdef SPITFIRE