 @@ -1,14 +1,14 @@
-/*	$NetBSD: pmap_motorola.h,v 1.27 2009/12/11 18:57:44 tsutsui Exp $	*/
+/*	$NetBSD: pmap_motorola.h,v 1.28 2009/12/13 12:32:46 tsutsui Exp $	*/
 /*
  * Copyright (c) 1991, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This code is derived from software contributed to Berkeley by
  * the Systems Programming Group of the University of Utah Computer
  * Science Department.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -91,28 +91,28 @@ struct pmap {
 	uint16_t		pm_sref;	/* segment table ref count */
 	uint16_t		pm_count;	/* pmap reference count */
 	struct simplelock	pm_lock;	/* lock on pmap */
 	struct pmap_statistics	pm_stats;	/* pmap statistics */
 	int			pm_ptpages;	/* more stats: PT pages */
 };
 /*
  * MMU specific segment values
+ *
  * We are using following segment layout in m68k pmap_motorola.c:
  * 68020/030 4KB/page: l1,l2,page    == 10,10,12	(%tc = 0x82c0aa00)
  * 68020/030 8KB/page: l1,l2,page    ==  8,11,13	(%tc = 0x82d08b00)
- * 68040/060 4KB/page: l1,l2,l3,page == 7,7,6,12
+ * 68040/060 4KB/page: l1,l2,l3,page == 7,7,6,12	(%tc = 0x8000)
- * 68040/060 8KB/page: l1,l2,l3,page == 7,7,5,13
+ * 68040/060 8KB/page: l1,l2,l3,page == 7,7,5,13	(%tc = 0xc000)
+ *
  * 68020/030 l2 size is chosen per NPTEPG, a number of page table entries
  * per page, to use one whole page for PTEs per one segment table entry,
  * and maybe also because 68020 HP MMU machines use simlar structures.
+ *
  * 68040/060 layout is defined by hardware design and not configurable,
  * as defined in <m68k/pte_motorola.h>.
+ *
  * Even on 68040/060, we still appropriate 2-level ste-pte pmap structures
  * for 68020/030 (derived from 4.4BSD/hp300) to handle 040's 3-level MMU.
  * TIA_SIZE and TIB_SIZE are used to represent such pmap structures and
  * they are also refered on 040/060.
+ *
 @@ -142,38 +142,40 @@ struct pmap {
 #define SEGOFSET	(NBSEG - 1)	/* byte offset into segment */
 #define	m68k_round_seg(x)	((((vaddr_t)(x)) + SEGOFSET) & ~SEGOFSET)
 #define	m68k_trunc_seg(x)	((vaddr_t)(x) & ~SEGOFSET)
 #define	m68k_seg_offset(x)	((vaddr_t)(x) & SEGOFSET)
 /*
  * On the 040, we keep track of which level 2 blocks are already in use
  * with the pm_stfree mask.  Bits are arranged from LSB (block 0) to MSB
  * (block 31).  For convenience, the level 1 table is considered to be
  * block 0.
+ *
- * MAX[KU]L2SIZE control how many pages of level 2 descriptors are allowed.
+ * MAX[KU]L2SIZE control how many pages of level 2 descriptors are allowed
- * for the kernel and users.  8 implies only the initial "segment table"
+ * for the kernel and users.
- * page is used.  WARNING: don't change MAXUL2SIZE unless you can allocate
+ * 16 or 8 implies only the initial "segment table" page is used,
- * physically contiguous pages for the ST in pmap.c!
+ * i.e. it means PAGE_SIZE / (SG4_LEV1SIZE * sizeof(st_entry_t)).
  * WARNING: don't change MAXUL2SIZE unless you can allocate
  * physically contiguous pages for the ST in pmap_motorola.c!
  */
 #define MAXKL2SIZE	32
-#if PAGE_SIZE == 8192
+#if PAGE_SIZE == 8192	/* NBPG / (SG4_LEV1SIZE * sizeof(st_entry_t)) */
 #define MAXUL2SIZE	16
 #else
 #define MAXUL2SIZE	8
 #endif
-#define l2tobm(n)	(1 << (n))
+#define l2tobm(n)	(1U << (n))
 #define bmtol2(n)	(ffs(n) - 1)
 /*
  * Macros for speed
  */
 #define	PMAP_ACTIVATE(pmap, loadhw)					\
 {									\
 	if ((loadhw))							\
 		loadustp(m68k_btop((paddr_t)(pmap)->pm_stpa));		\
+}
 /*
  * For each struct vm_page, there is a list of all currently valid virtual