 @@ -1,34 +1,34 @@
-/*	$NetBSD: pxa2x0_mci.c,v 1.4 2010/03/13 12:28:44 nonaka Exp $	*/
+/*	$NetBSD: pxa2x0_mci.c,v 1.5 2010/04/06 15:55:46 nonaka Exp $	*/
 /*	$OpenBSD: pxa2x0_mmc.c,v 1.5 2009/02/23 18:09:55 miod Exp $	*/
 /*
  * Copyright (c) 2007 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 /*-
- * Copyright (c) 2007-2009 NONAKA Kimihiro <nonaka@netbsd.org>
+ * Copyright (c) 2007-2010 NONAKA Kimihiro <nonaka@netbsd.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 @@ -44,63 +44,63 @@
  */
 /*
  * MMC/SD/SDIO controller driver for Intel PXA2xx processors
+ *
  * Power management is beyond control of the processor's SD/SDIO/MMC
  * block, so this driver depends on the attachment driver to provide
  * us with some callback functions via the "tag" member in our softc.
  * Bus power management calls are then dispatched to the attachment
  * driver.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pxa2x0_mci.c,v 1.4 2010/03/13 12:28:44 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pxa2x0_mci.c,v 1.5 2010/04/06 15:55:46 nonaka Exp $");
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/systm.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/proc.h>
 #include <sys/bus.h>
 #include <sys/mutex.h>
 #include <sys/condvar.h>
 #include <machine/intr.h>
 #include <dev/sdmmc/sdmmcvar.h>
 #include <dev/sdmmc/sdmmcchip.h>
 #include <arm/xscale/pxa2x0cpu.h>
 #include <arm/xscale/pxa2x0reg.h>
 #include <arm/xscale/pxa2x0var.h>
 #include <arm/xscale/pxa2x0_dmac.h>
 #include <arm/xscale/pxa2x0_gpio.h>
 #include <arm/xscale/pxa2x0_mci.h>
 #ifdef PXAMCI_DEBUG
-int pxamci_debug = 1;
+int pxamci_debug = 9;
 #define DPRINTF(n,s)	do { if ((n) <= pxamci_debug) printf s; } while (0)
 #else
 #define DPRINTF(n,s)	do {} while (0)
 #endif
-#ifndef DEBUG
+#ifndef PXAMCI_DEBUG
-#define	STOPCLK_TIMO	2	/* ms */
+#define	STOPCLK_TIMO	2	/* sec */
-#define	EXECCMD_TIMO	2	/* ms */
+#define	EXECCMD_TIMO	2	/* sec */
 #else
-#define	STOPCLK_TIMO	2	/* ms */
+#define	STOPCLK_TIMO	2	/* sec */
-#define	EXECCMD_TIMO	5	/* ms */
+#define	EXECCMD_TIMO	5	/* sec */
 #endif
 static int	pxamci_host_reset(sdmmc_chipset_handle_t);
 static uint32_t	pxamci_host_ocr(sdmmc_chipset_handle_t);
 static int	pxamci_host_maxblklen(sdmmc_chipset_handle_t);
 static int	pxamci_card_detect(sdmmc_chipset_handle_t);
 static int	pxamci_write_protect(sdmmc_chipset_handle_t);
 static int	pxamci_bus_power(sdmmc_chipset_handle_t, uint32_t);
 static int	pxamci_bus_clock(sdmmc_chipset_handle_t, int);
 static int	pxamci_bus_width(sdmmc_chipset_handle_t, int);
 static void	pxamci_exec_command(sdmmc_chipset_handle_t,
 		    struct sdmmc_command *);
 static void	pxamci_card_enable_intr(sdmmc_chipset_handle_t, int);
 @@ -145,26 +145,34 @@ static void	pxamci_stop_clock(struct pxa
 #define CSR_READ_1(sc, reg) \
 	bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg))
 #define CSR_WRITE_1(sc, reg, val) \
 	bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
 #define CSR_READ_4(sc, reg) \
 	bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
 #define CSR_WRITE_4(sc, reg, val) \
 	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
 #define CSR_SET_4(sc, reg, val) \
 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val))
 #define CSR_CLR_4(sc, reg, val) \
 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val))
 #if 0	/* XXX */
 #define	DMA_ALIGNED(addr) \
 	(((u_long)(addr) & 0x7) == 0 || !CPU_IS_PXA250)
 #else
 #define	DMA_ALIGNED(addr) \
 	(((u_long)(addr) & 0x1f) == 0)
 #endif
 static void
 pxamci_enable_intr(struct pxamci_softc *sc, uint32_t mask)
+{
 	int s;
 	s = splsdmmc();
 	sc->sc_imask &= ~mask;
 	CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask);
 	splx(s);
+}
 static void
 pxamci_disable_intr(struct pxamci_softc *sc, uint32_t mask)
 @@ -228,29 +236,26 @@ pxamci_attach_sub(device_t self, struct
 	pxamci_bus_clock(sc, sc->sc_clkbase);
 	/* Setup max block length */
 	if (CPU_IS_PXA270) {
 		sc->sc_maxblklen = 2048;
 	} else {
 		sc->sc_maxblklen = 512;
+	}
 	/* Set default bus width */
 	sc->sc_buswidth = 1;
 	/* setting DMA */
 #if 1	/* XXX */
 	SET(sc->sc_caps, PMC_CAPS_NO_DMA);	/* disable DMA */
 #endif
 	if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) {
 		aprint_normal_dev(sc->sc_dev, "using DMA transfer\n");
 		sc->sc_rxdr.ds_addr = PXA2X0_MMC_BASE + MMC_RXFIFO;
 		sc->sc_rxdr.ds_len = 1;
 		sc->sc_rxdx = pxa2x0_dmac_allocate_xfer(M_NOWAIT);
 		if (sc->sc_rxdx == NULL) {
 			aprint_error_dev(sc->sc_dev,
 			    "couldn't alloc rx dma xfer\n");
 			goto free_intr;
+		}
 		sc->sc_rxdx->dx_cookie = sc;
 		sc->sc_rxdx->dx_priority = DMAC_PRIORITY_NORMAL;
 @@ -291,30 +296,28 @@ pxamci_attach_sub(device_t self, struct
 	 * Attach the generic SD/MMC bus driver.  (The bus driver must
 	 * not invoke any chipset functions before it is attached.)
 	 */
 	memset(&saa, 0, sizeof(saa));
 	saa.saa_busname = "sdmmc";
 	saa.saa_sct = &pxamci_chip_functions;
 	saa.saa_sch = sc;
 	saa.saa_dmat = pxa->pxa_dmat;
 	saa.saa_clkmin = sc->sc_clkmin;
 	saa.saa_clkmax = sc->sc_clkmax;
 	saa.saa_caps = 0;
 	if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA))
 		SET(saa.saa_caps, SMC_CAPS_DMA);
 #if notyet
 	if (CPU_IS_PXA270 && ISSET(sc->sc_caps, PMC_CAPS_4BIT))
 		SET(saa.saa_caps, SMC_CAPS_4BIT_MODE);
 #endif
 	sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL);
 	if (sc->sc_sdmmc == NULL) {
 		aprint_error_dev(sc->sc_dev, "couldn't attach bus\n");
 		goto free_xfer;
+	}
 	return 0;
 free_xfer:
 	if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) {
 		if (sc->sc_rxdx)
 			pxa2x0_dmac_free_xfer(sc->sc_rxdx);
 		if (sc->sc_txdx)
 @@ -602,55 +605,60 @@ pxamci_exec_command(sdmmc_chipset_handle
 		if (numblk > NOB_MASK) {
 			aprint_error_dev(sc->sc_dev, "too much data\n");
 			cmd->c_error = EINVAL;
 			goto out;
+		}
 		CSR_WRITE_4(sc, MMC_BLKLEN, blklen);
 		CSR_WRITE_4(sc, MMC_NOB, numblk);
 		CSR_WRITE_4(sc, MMC_RDTO, RDTO_MASK);
 		cmdat |= CMDAT_DATA_EN;
 		/* setting DMA */
-		if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) {
+		if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)
 		 && DMA_ALIGNED(cmd->c_data)) {
 			struct dmac_xfer_desc *dx_desc;
 			DPRINTF(1,("%s: using DMA\n",device_xname(sc->sc_dev)));
 			cmdat |= CMDAT_MMC_DMA_EN;
 			if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
 				dx_desc = &sc->sc_rxdx->dx_desc[DMAC_DESC_DST];
 				dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs;
 				dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs;
 				error = pxa2x0_dmac_start_xfer(sc->sc_rxdx);
 			} else {
 				dx_desc = &sc->sc_txdx->dx_desc[DMAC_DESC_SRC];
 				dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs;
 				dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs;
 				/* workaround for erratum #91 */
 				error = 0;
 				if (!CPU_IS_PXA270) {
 					error =
 					    pxa2x0_dmac_start_xfer(sc->sc_txdx);
+				}
+			}
 			if (error) {
 				aprint_error_dev(sc->sc_dev,
 				    "couldn't start dma xfer. (error=%d)\n",
 				    error);
 				cmd->c_error = EIO;
 				goto err;
+			}
 		} else {
 			DPRINTF(1,("%s: using PIO\n",device_xname(sc->sc_dev)));
 			cmd->c_resid = cmd->c_datalen;
 			cmd->c_buf = cmd->c_data;
 			pxamci_enable_intr(sc, MMC_I_RXFIFO_RD_REQ
 					       | MMC_I_TXFIFO_WR_REQ
 					       | MMC_I_DAT_ERR);
+		}
+	}
 	sc->sc_cmd = cmd;
 	/*
 	 * "After reset, the MMC card must be initialized by sending
 @@ -729,50 +737,51 @@ pxamci_stop_clock(struct pxamci_softc *s
  * SD/MMC controller interrput handler
  */
 static int
 pxamci_intr(void *arg)
+{
 	struct pxamci_softc *sc = arg;
 	int status;
 #ifdef PXAMCI_DEBUG
 	int ostatus;
 	ostatus =
 #endif
 	status = CSR_READ_4(sc, MMC_I_REG) & ~CSR_READ_4(sc, MMC_I_MASK);
-	DPRINTF(9,("%s: intr status = %08x\n", device_xname(sc->sc_dev),
+	DPRINTF(10,("%s: intr status = %08x\n", device_xname(sc->sc_dev),
 	    status));
 	/*
 	 * Notify the process waiting in pxamci_clock_stop() when
 	 * the clock has really stopped.
 	 */
 	if (ISSET(status, MMC_I_CLK_IS_OFF)) {
 		DPRINTF(2,("%s: clock is now off\n", device_xname(sc->sc_dev)));
 		wakeup(sc);
 		pxamci_disable_intr(sc, MMC_I_CLK_IS_OFF);
 		CLR(status, MMC_I_CLK_IS_OFF);
+	}
 	if (sc->sc_cmd == NULL)
 		goto end;
 	if (ISSET(status, MMC_I_RES_ERR)) {
 		DPRINTF(9, ("%s: handling MMC_I_RES_ERR\n",
 		    device_xname(sc->sc_dev)));
 		pxamci_disable_intr(sc, MMC_I_RES_ERR);
 		CLR(status, MMC_I_RES_ERR|MMC_I_END_CMD_RES);
 		if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)
-		 && (sc->sc_cmd->c_datalen > 0)) {
+		 && (sc->sc_cmd->c_datalen > 0)
 		 && DMA_ALIGNED(sc->sc_cmd->c_data)) {
 			if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) {
 				pxa2x0_dmac_abort_xfer(sc->sc_rxdx);
 			} else {
 				pxa2x0_dmac_abort_xfer(sc->sc_txdx);
+			}
+		}
 		sc->sc_cmd->c_error = ENOEXEC;
 		pxamci_intr_done(sc);
 		goto end;
+	}
 	if (ISSET(status, MMC_I_END_CMD_RES)) {
 		DPRINTF(9,("%s: handling MMC_I_END_CMD_RES\n",
 @@ -786,51 +795,52 @@ pxamci_intr(void *arg)
 			CLR(status, MMC_I_PRG_DONE);
+		}
 		if (sc->sc_cmd == NULL)
 			goto end;
+	}
 	if (ISSET(status, MMC_I_DAT_ERR)) {
 		DPRINTF(9, ("%s: handling MMC_I_DAT_ERR\n",
 		    device_xname(sc->sc_dev)));
 		sc->sc_cmd->c_error = EIO;
 		pxamci_intr_done(sc);
 		pxamci_disable_intr(sc, MMC_I_DAT_ERR);
 		CLR(status, MMC_I_DAT_ERR);
-		if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) {
+		if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)
 		 && DMA_ALIGNED(sc->sc_cmd->c_data)) {
 			if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) {
 				pxa2x0_dmac_abort_xfer(sc->sc_rxdx);
 			} else {
 				pxa2x0_dmac_abort_xfer(sc->sc_txdx);
+			}
+		}
 		/* ignore transmission done condition */
 		if (ISSET(status, MMC_I_DATA_TRAN_DONE)) {
 			pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE);
 			CLR(status, MMC_I_DATA_TRAN_DONE);
+		}
 		goto end;
+	}
 	if (ISSET(status, MMC_I_DATA_TRAN_DONE)) {
 		DPRINTF(9,("%s: handling MMC_I_DATA_TRAN_DONE\n",
 		    device_xname(sc->sc_dev)));
 		pxamci_intr_done(sc);
 		pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE);
 		CLR(status, MMC_I_DATA_TRAN_DONE);
+	}
 	if (ISSET(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ)) {
-		DPRINTF(9,("%s: handling MMC_I_xxFIFO_xx_REQ\n",
+		DPRINTF(10,("%s: handling MMC_I_xxFIFO_xx_REQ\n",
 		    device_xname(sc->sc_dev)));
 		pxamci_intr_data(sc);
 		CLR(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ);
+	}
 	if (ISSET(status, STAT_SDIO_INT)) {
 		DPRINTF(9,("%s: handling STAT_SDIO_INT\n",
 		    device_xname(sc->sc_dev)));
 		sdmmc_card_intr(sc->sc_sdmmc);
 		CLR(status, STAT_SDIO_INT);
+	}
 end:
 @@ -910,55 +920,57 @@ pxamci_intr_cmd(struct pxamci_softc *sc)
 	      && ISSET(cmd->c_flags, SCF_RSP_CRC)
 	      && CPU_IS_PXA270) {
 		/* workaround for erratum #42 */
 		if (ISSET(cmd->c_flags, SCF_RSP_136)
 		 && (cmd->c_resp[0] & 0x80000000U)) {
 			DPRINTF(1,("%s: ignore CRC error\n",
 			    device_xname(sc->sc_dev)));
 		} else
 			cmd->c_error = EIO;
 	} else if (ISSET(status, STAT_ERR))
 		cmd->c_error = EIO;
 	if (cmd->c_error == 0 && cmd->c_datalen > 0) {
 		/* workaround for erratum #91 */
 		if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)
-		 && CPU_IS_PXA270
+		 && DMA_ALIGNED(cmd->c_data)) {
-		 && !ISSET(cmd->c_flags, SCF_CMD_READ)) {
+			/* workaround for erratum #91 */
-			error = pxa2x0_dmac_start_xfer(sc->sc_txdx);
+			if (CPU_IS_PXA270
-			if (error) {
+			 && !ISSET(cmd->c_flags, SCF_CMD_READ)) {
-				aprint_error_dev(sc->sc_dev,
+				error = pxa2x0_dmac_start_xfer(sc->sc_txdx);
-				    "couldn't start dma xfer. (error=%d)\n",
+				if (error) {
-				    error);
+					aprint_error_dev(sc->sc_dev,
-				cmd->c_error = EIO;
+					    "couldn't start dma xfer."
-				pxamci_intr_done(sc);
+					    " (error=%d)\n", error);
-				return;
+					cmd->c_error = EIO;
 					pxamci_intr_done(sc);
 					return;
+				}
+			}
 			pxamci_enable_intr(sc,
 			    MMC_I_DATA_TRAN_DONE|MMC_I_DAT_ERR);
+		}
 	} else {
 		pxamci_intr_done(sc);
+	}
+}
 static void
 pxamci_intr_data(struct pxamci_softc *sc)
+{
 	struct sdmmc_command *cmd = sc->sc_cmd;
 	int intr;
 	int n;
-	DPRINTF(1,("%s: pxamci_intr_data: cmd = %p, resid = %d\n",
+	DPRINTF(10,("%s: pxamci_intr_data: cmd = %p, resid = %d\n",
 	    device_xname(sc->sc_dev), cmd, cmd->c_resid));
 	n = MIN(32, cmd->c_resid);
 	cmd->c_resid -= n;
 	if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
 		intr = MMC_I_RXFIFO_RD_REQ;
 		while (n-- > 0)
 			*cmd->c_buf++ = CSR_READ_1(sc, MMC_RXFIFO);
 	} else {
 		int short_xfer = n < 32;
 		intr = MMC_I_TXFIFO_WR_REQ;
 @@ -988,29 +1000,39 @@ pxamci_intr_done(struct pxamci_softc *sc
 	pxamci_disable_intr(sc, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ|
 	    MMC_I_DATA_TRAN_DONE|MMC_I_END_CMD_RES|MMC_I_RES_ERR|MMC_I_DAT_ERR);
 	SET(sc->sc_cmd->c_flags, SCF_ITSDONE);
 	sc->sc_cmd = NULL;
 	wakeup(sc);
+}
 static void
 pxamci_dmac_iintr(struct dmac_xfer *dx, int status)
+{
 	struct pxamci_softc *sc = dx->dx_cookie;
 	DPRINTF(1,("%s: pxamci_dmac_iintr: status = %#x\n",
 	    device_xname(sc->sc_dev), status));
 	if (status) {
 		aprint_error_dev(sc->sc_dev, "pxamci_dmac_iintr: "
 		    "non-zero completion status %d\n", status);
+	}
+}
 static void
 pxamci_dmac_ointr(struct dmac_xfer *dx, int status)
+{
 	struct pxamci_softc *sc = dx->dx_cookie;
-	if (status) {
+	DPRINTF(1,("%s: pxamci_dmac_ointr: status = %#x\n",
 	    device_xname(sc->sc_dev), status));
 	if (status == 0) {
 		if (sc->sc_cmd != NULL && (sc->sc_cmd->c_datalen & 31) != 0) {
 			CSR_WRITE_4(sc, MMC_PRTBUF, 1);
+		}
 	} else {
 		aprint_error_dev(sc->sc_dev, "pxamci_dmac_ointr: "
 		    "non-zero completion status %d\n", status);
+	}
+}