Tue Apr 27 05:44:30 2010 UTC ()
seperate RMI CPU revision codes from RMI CPU processor codes
and improve comment


(cliff)
diff -r1.74.28.17 -r1.74.28.18 src/sys/arch/mips/include/cpuregs.h
cvs diff -r1.74.28.17 -r1.74.28.18 src/sys/arch/mips/include/cpuregs.h (expand / switch to unified diff)

--- src/sys/arch/mips/include/cpuregs.h 2010/03/29 23:33:00 1.74.28.17
+++ src/sys/arch/mips/include/cpuregs.h 2010/04/27 05:44:30 1.74.28.18
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpuregs.h,v 1.74.28.17 2010/03/29 23:33:00 cliff Exp $ */ 1/* $NetBSD: cpuregs.h,v 1.74.28.18 2010/04/27 05:44:30 cliff Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1992, 1993 4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved. 5 * The Regents of the University of California. All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to Berkeley by 7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem. 8 * Ralph Campbell and Rick Macklem.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -861,32 +861,35 @@ @@ -861,32 +861,35 @@
861#define MIPS_AU1550 0x03 861#define MIPS_AU1550 0x03
862 862
863/* 863/*
864 * CPU processor revision IDs for company ID == 4 (SiByte) 864 * CPU processor revision IDs for company ID == 4 (SiByte)
865 */ 865 */
866#define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 866#define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */
867 867
868/* 868/*
869 * CPU processor revision IDs for company ID == 5 (SandCraft) 869 * CPU processor revision IDs for company ID == 5 (SandCraft)
870 */ 870 */
871#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ 871#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
872 872
873/* 873/*
874 * CPU processor revision IDs for company ID == 12 (RMI) 874 * CPU revision IDs for company ID == 12 (RMI)
875 * note: the XLR Pid value meaning depends on 875 * note: unlisted Rev values may indicate pre-production silicon
876 * the Rev value (Stepping B2 or C4) 876 */
 877#define MIPS_XLR_B2 0x04 /* RMI XLR Production Rev B2 */
 878#define MIPS_XLR_C4 0x91 /* RMI XLR Production Rev C4 */
 879
 880/*
 881 * CPU processor IDs for company ID == 12 (RMI)
877 */ 882 */
878#define MIPS_XLR_B2 0x04 /* RMI XLR Rev B2 */ 
879#define MIPS_XLR_C4 0x91 /* RMI XLR Rev C4 */ 
880#define MIPS_XLR308B 0x06 /* RMI XLR308-B ISA 64 */ 883#define MIPS_XLR308B 0x06 /* RMI XLR308-B ISA 64 */
881#define MIPS_XLR508B 0x07 /* RMI XLR508-B ISA 64 */ 884#define MIPS_XLR508B 0x07 /* RMI XLR508-B ISA 64 */
882#define MIPS_XLR516B 0x08 /* RMI XLR516-B ISA 64 */ 885#define MIPS_XLR516B 0x08 /* RMI XLR516-B ISA 64 */
883#define MIPS_XLR532B 0x09 /* RMI XLR532-B ISA 64 */ 886#define MIPS_XLR532B 0x09 /* RMI XLR532-B ISA 64 */
884#define MIPS_XLR716B 0x0a /* RMI XLR716-B ISA 64 */ 887#define MIPS_XLR716B 0x0a /* RMI XLR716-B ISA 64 */
885#define MIPS_XLR732B 0x0b /* RMI XLR732-B ISA 64 */ 888#define MIPS_XLR732B 0x0b /* RMI XLR732-B ISA 64 */
886#define MIPS_XLR732C 0x00 /* RMI XLR732-C ISA 64 */ 889#define MIPS_XLR732C 0x00 /* RMI XLR732-C ISA 64 */
887#define MIPS_XLR716C 0x02 /* RMI XLR716-C ISA 64 */ 890#define MIPS_XLR716C 0x02 /* RMI XLR716-C ISA 64 */
888#define MIPS_XLR532C 0x08 /* RMI XLR532-C ISA 64 */ 891#define MIPS_XLR532C 0x08 /* RMI XLR532-C ISA 64 */
889#define MIPS_XLR516C 0x0a /* RMI XLR516-C ISA 64 */ 892#define MIPS_XLR516C 0x0a /* RMI XLR516-C ISA 64 */
890#define MIPS_XLR508C 0x0b /* RMI XLR508-C ISA 64 */ 893#define MIPS_XLR508C 0x0b /* RMI XLR508-C ISA 64 */
891#define MIPS_XLR308C 0x0f /* RMI XLR308-C ISA 64 */ 894#define MIPS_XLR308C 0x0f /* RMI XLR308-C ISA 64 */
892#define MIPS_XLS616 0x40 /* RMI XLS616 ISA 64 */ 895#define MIPS_XLS616 0x40 /* RMI XLS616 ISA 64 */