Sun Aug 8 18:44:16 2010 UTC ()
merge sparc and sparc64 fsr.h into one file.
add the missing FSR_TT_* definitions.
fix FSR_FTT_MASK.  fix the V9 FCC fields.


(chs)
diff -r1.4 -r1.5 src/sys/arch/sparc/include/fsr.h
diff -r1.3 -r1.4 src/sys/arch/sparc64/include/fsr.h
cvs diff -r1.4 -r1.5 src/sys/arch/sparc/include/fsr.h (expand / switch to unified diff)

--- src/sys/arch/sparc/include/fsr.h 2005/12/11 12:19:05 1.4
+++ src/sys/arch/sparc/include/fsr.h 2010/08/08 18:44:15 1.5
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: fsr.h,v 1.4 2005/12/11 12:19:05 christos Exp $ */ 1/* $NetBSD: fsr.h,v 1.5 2010/08/08 18:44:15 chs Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1992, 1993 4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved. 5 * The Regents of the University of California. All rights reserved.
6 * 6 *
7 * This software was developed by the Computer Systems Engineering group 7 * This software was developed by the Computer Systems Engineering group
8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9 * contributed to Berkeley. 9 * contributed to Berkeley.
10 * 10 *
11 * All advertising materials mentioning features or use of this software 11 * All advertising materials mentioning features or use of this software
12 * must display the following acknowledgement: 12 * must display the following acknowledgement:
13 * This product includes software developed by the University of 13 * This product includes software developed by the University of
14 * California, Lawrence Berkeley Laboratory. 14 * California, Lawrence Berkeley Laboratory.
@@ -30,28 +30,28 @@ @@ -30,28 +30,28 @@
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE. 38 * SUCH DAMAGE.
39 * 39 *
40 * @(#)fsr.h 8.1 (Berkeley) 6/11/93 40 * @(#)fsr.h 8.1 (Berkeley) 6/11/93
41 */ 41 */
42 42
43#ifndef _MACHINE_FSR_H_ 43#ifndef _SPARC_FSR_H_
44#define _MACHINE_FSR_H_ 44#define _SPARC_FSR_H_
45 45
46/* 46/*
47 * Bits in FSR. 47 * Bits in FSR.
48 */ 48 */
49#define FSR_RD 0xc0000000 /* rounding direction */ 49#define FSR_RD 0xc0000000 /* rounding direction */
50#define FSR_RD_RN 0 /* round to nearest */ 50#define FSR_RD_RN 0 /* round to nearest */
51#define FSR_RD_RZ 1 /* round towards 0 */ 51#define FSR_RD_RZ 1 /* round towards 0 */
52#define FSR_RD_RP 2 /* round towards +inf */ 52#define FSR_RD_RP 2 /* round towards +inf */
53#define FSR_RD_RM 3 /* round towards -inf */ 53#define FSR_RD_RM 3 /* round towards -inf */
54#define FSR_RD_SHIFT 30 54#define FSR_RD_SHIFT 30
55#define FSR_RD_MASK 0x03 55#define FSR_RD_MASK 0x03
56 56
57#define FSR_RP 0x30000000 /* extended rounding precision */ 57#define FSR_RP 0x30000000 /* extended rounding precision */
@@ -71,42 +71,69 @@ @@ -71,42 +71,69 @@
71#define FSR_MBZ 0x00300000 /* reserved; must be zero */ 71#define FSR_MBZ 0x00300000 /* reserved; must be zero */
72 72
73#define FSR_VER 0x000e0000 /* version bits */ 73#define FSR_VER 0x000e0000 /* version bits */
74#define FSR_VER_SHIFT 17 74#define FSR_VER_SHIFT 17
75#define FSR_VER_MASK 0x07 75#define FSR_VER_MASK 0x07
76 76
77#define FSR_FTT 0x0001c000 /* FP trap type */ 77#define FSR_FTT 0x0001c000 /* FP trap type */
78#define FSR_TT_NONE 0 /* no trap */ 78#define FSR_TT_NONE 0 /* no trap */
79#define FSR_TT_IEEE 1 /* IEEE exception */ 79#define FSR_TT_IEEE 1 /* IEEE exception */
80#define FSR_TT_UNFIN 2 /* unfinished operation */ 80#define FSR_TT_UNFIN 2 /* unfinished operation */
81#define FSR_TT_UNIMP 3 /* unimplemented operation */ 81#define FSR_TT_UNIMP 3 /* unimplemented operation */
82#define FSR_TT_SEQ 4 /* sequence error */ 82#define FSR_TT_SEQ 4 /* sequence error */
83#define FSR_TT_HWERR 5 /* hardware error (unrecoverable) */ 83#define FSR_TT_HWERR 5 /* hardware error (unrecoverable) */
 84#define FSR_TT_INVR 6 /* invalid fp register */
 85#define FSR_TT_RESV 7 /* reserved */
84#define FSR_FTT_SHIFT 14 86#define FSR_FTT_SHIFT 14
85#define FSR_FTT_MASK 0x03 87#define FSR_FTT_MASK 0x07
86 88
87#define FSR_QNE 0x00002000 /* queue not empty */ 89#define FSR_QNE 0x00002000 /* queue not empty */
88#define FSR_PR 0x00001000 /* partial result */ 90#define FSR_PR 0x00001000 /* partial result */
89 91
90#define FSR_FCC 0x00000c00 /* FP condition codes */ 92#define FSR_FCC 0x00000c00 /* FP condition codes */
91#define FSR_CC_EQ 0 /* f1 = f2 */ 93#define FSR_CC_EQ 0 /* f1 = f2 */
92#define FSR_CC_LT 1 /* f1 < f2 */ 94#define FSR_CC_LT 1 /* f1 < f2 */
93#define FSR_CC_GT 2 /* f1 > f2 */ 95#define FSR_CC_GT 2 /* f1 > f2 */
94#define FSR_CC_UO 3 /* (f1,f2) unordered */ 96#define FSR_CC_UO 3 /* (f1,f2) unordered */
95#define FSR_FCC_SHIFT 10 97#define FSR_FCC_SHIFT 10
96#define FSR_FCC_MASK 0x03 98#define FSR_FCC_MASK 0x03
97 99
98#define FSR_AX 0x000003e0 /* accrued exceptions */ 100#define FSR_AX 0x000003e0 /* accrued exceptions */
99#define FSR_AX_SHIFT 5 101#define FSR_AX_SHIFT 5
100#define FSR_AX_MASK 0x1f 102#define FSR_AX_MASK 0x1f
101#define FSR_CX 0x0000001f /* current exceptions */ 103#define FSR_CX 0x0000001f /* current exceptions */
102#define FSR_CX_SHIFT 0 104#define FSR_CX_SHIFT 0
103#define FSR_CX_MASK 0x1f 105#define FSR_CX_MASK 0x1f
104 106
105/* The following exceptions apply to TEM, AX, and CX. */ 107/* The following exceptions apply to TEM, AX, and CX. */
106#define FSR_NV 0x10 /* invalid operand */ 108#define FSR_NV 0x10 /* invalid operand */
107#define FSR_OF 0x08 /* overflow */ 109#define FSR_OF 0x08 /* overflow */
108#define FSR_UF 0x04 /* underflow */ 110#define FSR_UF 0x04 /* underflow */
109#define FSR_DZ 0x02 /* division by zero */ 111#define FSR_DZ 0x02 /* division by zero */
110#define FSR_NX 0x01 /* inexact result */ 112#define FSR_NX 0x01 /* inexact result */
111 113
112#endif /* _MACHINE_FSR_H_ */ 114#ifdef __sparc_v9__
 115
 116/*
 117 * The rest of these are only for sparcv9.
 118 */
 119
 120/* These are the 3 new v9 fcc's */
 121#define FSR_FCC3 0x0000003000000000ULL /* FP condition codes */
 122#define FSR_FCC3_SHIFT 36
 123
 124#define FSR_FCC2 0x0000000c00000000ULL /* FP condition codes */
 125#define FSR_FCC2_SHIFT 34
 126
 127#define FSR_FCC1 0x0000000300000000ULL /* FP condition codes */
 128#define FSR_FCC1_SHIFT 32
 129
 130/*
 131 * Bits in FPRS.
 132 */
 133#define FPRS_FEF 0x04 /* Enable FP -- must be set to enable FP regs */
 134#define FPRS_DU 0x02 /* Dirty upper -- upper fp regs are dirty */
 135#define FPRS_DL 0x01 /* Dirty lower -- lower fp regs are dirty */
 136
 137#endif /* __sparc_v9__ */
 138
 139#endif /* _SPARC_FSR_H_ */
cvs diff -r1.3 -r1.4 src/sys/arch/sparc64/include/fsr.h (expand / switch to unified diff)

--- src/sys/arch/sparc64/include/fsr.h 2005/12/11 12:19:10 1.3
+++ src/sys/arch/sparc64/include/fsr.h 2010/08/08 18:44:16 1.4
@@ -1,131 +1,3 @@ @@ -1,131 +1,3 @@
1/* $NetBSD: fsr.h,v 1.3 2005/12/11 12:19:10 christos Exp $ */ 1/* $NetBSD: fsr.h,v 1.4 2010/08/08 18:44:16 chs Exp $ */
2 2
3/* 3#include <sparc/fsr.h>
4 * Copyright (c) 1992, 1993 
5 * The Regents of the University of California. All rights reserved. 
6 * 
7 * This software was developed by the Computer Systems Engineering group 
8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 
9 * contributed to Berkeley. 
10 * 
11 * All advertising materials mentioning features or use of this software 
12 * must display the following acknowledgement: 
13 * This product includes software developed by the University of 
14 * California, Lawrence Berkeley Laboratory. 
15 * 
16 * Redistribution and use in source and binary forms, with or without 
17 * modification, are permitted provided that the following conditions 
18 * are met: 
19 * 1. Redistributions of source code must retain the above copyright 
20 * notice, this list of conditions and the following disclaimer. 
21 * 2. Redistributions in binary form must reproduce the above copyright 
22 * notice, this list of conditions and the following disclaimer in the 
23 * documentation and/or other materials provided with the distribution. 
24 * 3. Neither the name of the University nor the names of its contributors 
25 * may be used to endorse or promote products derived from this software 
26 * without specific prior written permission. 
27 * 
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
38 * SUCH DAMAGE. 
39 * 
40 * @(#)fsr.h 8.1 (Berkeley) 6/11/93 
41 */ 
42 
43#ifndef _MACHINE_FSR_H_ 
44#define _MACHINE_FSR_H_ 
45 
46/*  
47 * Bits in FPRS 
48 */ 
49#define FPRS_FEF 0x04 /* Enable FP -- must be set to enable FP regs */ 
50#define FPRS_DU 0x02 /* Dirty upper -- upper fp regs are dirty */ 
51#define FPRS_DL 0x01 /* Dirty lower -- lower fp regs are dirty */ 
52 
53/* 
54 * Bits in FSR. 
55 */ 
56 
57#define FSR_RD 0xc0000000 /* rounding direction */ 
58#define FSR_RD_RN 0 /* round to nearest */ 
59#define FSR_RD_RZ 1 /* round towards 0 */ 
60#define FSR_RD_RP 2 /* round towards +inf */ 
61#define FSR_RD_RM 3 /* round towards -inf */ 
62#define FSR_RD_SHIFT 30 
63#define FSR_RD_MASK 0x03 
64 
65#define FSR_RP 0x30000000 /* extended rounding precision */ 
66#define FSR_RP_X 0 /* extended stays extended */ 
67#define FSR_RP_S 1 /* extended => single */ 
68#define FSR_RP_D 2 /* extended => double */ 
69#define FSR_RP_80 3 /* extended => 80-bit */ 
70#define FSR_RP_SHIFT 28 
71#define FSR_RP_MASK 0x03 
72 
73#define FSR_TEM 0x0f800000 /* trap enable mask */ 
74#define FSR_TEM_SHIFT 23 
75#define FSR_TEM_MASK 0x1f 
76 
77#define FSR_NS 0x00400000 /* ``nonstandard mode'' */ 
78#define FSR_AU 0x00400000 /* aka abrupt underflow mode */ 
79#define FSR_MBZ 0x00300000 /* reserved; must be zero */ 
80 
81#define FSR_VER 0x000e0000 /* version bits */ 
82#define FSR_VER_SHIFT 17 
83#define FSR_VER_MASK 0x07 
84 
85#define FSR_FTT 0x0001c000 /* FP trap type */ 
86#define FSR_TT_NONE 0 /* no trap */ 
87#define FSR_TT_IEEE 1 /* IEEE exception */ 
88#define FSR_TT_UNFIN 2 /* unfinished operation */ 
89#define FSR_TT_UNIMP 3 /* unimplemented operation */ 
90#define FSR_TT_SEQ 4 /* sequence error */ 
91#define FSR_TT_HWERR 5 /* hardware error (unrecoverable) */ 
92#define FSR_FTT_SHIFT 14 
93#define FSR_FTT_MASK 0x03 
94 
95#define FSR_QNE 0x00002000 /* queue not empty */ 
96#define FSR_PR 0x00001000 /* partial result */ 
97 
98#define FSR_FCC 0x00000c00 /* FP condition codes */ 
99#define FSR_CC_EQ 0 /* f1 = f2 */ 
100#define FSR_CC_LT 1 /* f1 < f2 */ 
101#define FSR_CC_GT 2 /* f1 > f2 */ 
102#define FSR_CC_UO 3 /* (f1,f2) unordered */ 
103#define FSR_FCC_SHIFT 10 
104#define FSR_FCC_MASK 0x03 
105 
106#define FSR_AX 0x000003e0 /* accrued exceptions */ 
107#define FSR_AX_SHIFT 5 
108#define FSR_AX_MASK 0x1f 
109#define FSR_CX 0x0000001f /* current exceptions */ 
110#define FSR_CX_SHIFT 0 
111#define FSR_CX_MASK 0x1f 
112 
113/* These are the 3 new v9 fcc's */ 
114#define FSR_FCC3 0x06000000000 /* FP condition codes */ 
115#define FSR_FCC3_SHIFT 36 
116 
117#define FSR_FCC2 0x0c00000000 /* FP condition codes */ 
118#define FSR_FCC2_SHIFT 34 
119 
120#define FSR_FCC1 0x0600000000 /* FP condition codes */ 
121#define FSR_FCC1_SHIFT 32 
122 
123 
124/* The following exceptions apply to TEM, AX, and CX. */ 
125#define FSR_NV 0x10 /* invalid operand */ 
126#define FSR_OF 0x08 /* overflow */ 
127#define FSR_UF 0x04 /* underflow */ 
128#define FSR_DZ 0x02 /* division by zero */ 
129#define FSR_NX 0x01 /* inexact result */ 
130 
131#endif /* _MACHINE_FSR_H_ */