 @@ -1,444 +1,428 @@
-/* $NetBSD: acpi_cpu_md.c,v 1.5 2010/08/08 16:58:41 jruoho Exp $ */
+/* $NetBSD: acpi_cpu_md.c,v 1.6 2010/08/09 04:18:48 jruoho Exp $ */
 /*-
  * Copyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
+ *
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.5 2010/08/08 16:58:41 jruoho Exp $");
+__KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.6 2010/08/09 04:18:48 jruoho Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/kcore.h>
 #include <sys/sysctl.h>
 #include <sys/xcall.h>
 #include <x86/cpu.h>
 #include <x86/cpufunc.h>
 #include <x86/cputypes.h>
 #include <x86/cpuvar.h>
 #include <x86/cpu_msr.h>
 #include <x86/machdep.h>
 #include <dev/acpi/acpica.h>
 #include <dev/acpi/acpi_cpu.h>
 static char	  native_idle_text[16];
 void		(*native_idle)(void) = NULL;
 static int	 acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO);
 static int	 acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO);
 static int	 acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO);
 extern uint32_t cpus_running;
 extern struct acpicpu_softc **acpicpu_sc;
 uint32_t
 acpicpu_md_cap(void)
+{
 	struct cpu_info *ci = curcpu();
 	uint32_t val = 0;
 	if (cpu_vendor != CPUVENDOR_INTEL)
 		return val;
 	/*
 	 * Basic SMP C-states (required for _CST).
 	 */
 	val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3;
         /*
 	 * If MONITOR/MWAIT is available, announce
 	 * support for native instructions in all C-states.
 	 */
         if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0)
 		val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH;
 	/*
 	 * Set native P-states if EST is available.
 	 */
         if ((ci->ci_feat_val[1] & CPUID2_EST) != 0)
 		val |= ACPICPU_PDC_P_FFH;
 	return val;
+}
 uint32_t
 acpicpu_md_quirks(void)
+{
 	struct cpu_info *ci = curcpu();
 	uint32_t val = 0;
 	if (acpicpu_md_cpus_running() == 1)
 		val |= ACPICPU_FLAG_C_BM;
 	if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0)
 		val |= ACPICPU_FLAG_C_FFH;
 	switch (cpu_vendor) {
 	case CPUVENDOR_INTEL:
 		val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB;
 		if ((ci->ci_feat_val[1] & CPUID2_EST) != 0)
 			val |= ACPICPU_FLAG_P_FFH;
 		/*
 		 * Bus master arbitration is not
 		 * needed on some recent Intel CPUs.
 		 */
 		if (CPUID2FAMILY(ci->ci_signature) > 15)
 			val &= ~ACPICPU_FLAG_C_ARB;
 		if (CPUID2FAMILY(ci->ci_signature) == 6 &&
 		    CPUID2MODEL(ci->ci_signature) >= 15)
 			val &= ~ACPICPU_FLAG_C_ARB;
 		break;
 	case CPUVENDOR_AMD:
 		/*
 		 * XXX: Deal with the AMD C1E extension here.
 		 */
 		break;
+	}
 	return val;
+}
 uint32_t
 acpicpu_md_cpus_running(void)
+{
 	return popcount32(cpus_running);
+}
 int
 acpicpu_md_idle_init(void)
+{
 	const size_t size = sizeof(native_idle_text);
 	x86_disable_intr();
 	x86_cpu_idle_get(&native_idle, native_idle_text, size);
 	x86_enable_intr();
 	return 0;
+}
 int
 acpicpu_md_idle_start(void)
+{
 	x86_disable_intr();
 	x86_cpu_idle_set(acpicpu_cstate_idle, "acpi");
 	x86_enable_intr();
 	return 0;
+}
 int
 acpicpu_md_idle_stop(void)
+{
 	uint64_t xc;
 	x86_disable_intr();
 	x86_cpu_idle_set(native_idle, native_idle_text);
 	x86_enable_intr();
 	/*
 	 * Run a cross-call to ensure that all CPUs are
 	 * out from the ACPI idle-loop before detachment.
 	 */
 	xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL);
 	xc_wait(xc);
 	return 0;
+}
 /*
  * The MD idle loop. Called with interrupts disabled.
  */
 void
 acpicpu_md_idle_enter(int method, int state)
+{
 	struct cpu_info *ci = curcpu();
 	switch (method) {
 	case ACPICPU_C_STATE_FFH:
 		x86_enable_intr();
 		x86_monitor(&ci->ci_want_resched, 0, 0);
 		if (__predict_false(ci->ci_want_resched) != 0)
 			return;
 		x86_mwait((state - 1) << 4, 0);
 		break;
 	case ACPICPU_C_STATE_HALT:
 		if (__predict_false(ci->ci_want_resched) != 0) {
 			x86_enable_intr();
 			return;
+		}
 		x86_stihlt();
 		break;
+	}
+}
 int
 acpicpu_md_pstate_start(void)
+{
-	switch (cpu_vendor) {
+	cpu_freq_sysctl_get = acpicpu_md_pstate_sysctl_get;
 	cpu_freq_sysctl_set = acpicpu_md_pstate_sysctl_set;
-	case CPUVENDOR_INTEL:
+	cpu_freq_sysctl_all = acpicpu_md_pstate_sysctl_all;
 		est_sysctl_get = acpicpu_md_pstate_sysctl_get;
 		est_sysctl_set = acpicpu_md_pstate_sysctl_set;
 		est_sysctl_all = acpicpu_md_pstate_sysctl_all;
 		break;
 	default:
 		return ENODEV;
 	return 0;
+}
 int
 acpicpu_md_pstate_stop(void)
+{
-	switch (cpu_vendor) {
+	cpu_freq_sysctl_get = NULL;
 	cpu_freq_sysctl_set = NULL;
-	case CPUVENDOR_INTEL:
+	cpu_freq_sysctl_all = NULL;
 		est_sysctl_get = NULL;
 		est_sysctl_set = NULL;
 		est_sysctl_all = NULL;
 		break;
 	default:
 		return ENODEV;
 	return 0;
+}
 static int
 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS)
+{
 	struct cpu_info *ci = curcpu();
 	struct acpicpu_softc *sc;
 	struct sysctlnode node;
 	uint32_t freq;
 	int err;
 	/*
 	 * We can use any ACPI CPU to manipulate the
 	 * frequencies. In MP environments all CPUs
 	 * are mandated to support the same number of
 	 * P-states and each state must have identical
 	 * parameters across CPUs.
 	 */
 	sc = acpicpu_sc[ci->ci_acpiid];
 	if (sc == NULL)
 		return ENXIO;
 	err = acpicpu_pstate_get(sc, &freq);
 	if (err != 0)
 		return err;
 	node = *rnode;
 	node.sysctl_data = &freq;
 	err = sysctl_lookup(SYSCTLFN_CALL(&node));
 	if (err != 0 || newp == NULL)
 		return err;
 	return 0;
+}
 static int
 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS)
+{
 	struct cpu_info *ci = curcpu();
 	struct acpicpu_softc *sc;
 	struct sysctlnode node;
 	uint32_t freq;
 	int err;
 	sc = acpicpu_sc[ci->ci_acpiid];
 	if (sc == NULL)
 		return ENXIO;
 	err = acpicpu_pstate_get(sc, &freq);
 	if (err != 0)
 		return err;
 	node = *rnode;
 	node.sysctl_data = &freq;
 	err = sysctl_lookup(SYSCTLFN_CALL(&node));
 	if (err != 0 || newp == NULL)
 		return err;
 	err = acpicpu_pstate_set(sc, freq);
 	if (err != 0)
 		return err;
 	return 0;
+}
 static int
 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS)
+{
 	struct cpu_info *ci = curcpu();
 	struct acpicpu_softc *sc;
 	struct sysctlnode node;
 	char buf[1024];
 	size_t len;
 	uint32_t i;
 	int err;
 	sc = acpicpu_sc[ci->ci_acpiid];
 	if (sc == NULL)
 		return ENXIO;
 	(void)memset(&buf, 0, sizeof(buf));
 	mutex_enter(&sc->sc_mtx);
 	for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) {
 		if (sc->sc_pstate[i].ps_freq == 0)
 			continue;
 		len += snprintf(buf + len, sizeof(buf) - len, "%u%s",
 		    sc->sc_pstate[i].ps_freq,
 		    i < (sc->sc_pstate_count - 1) ? " " : "");
+	}
 	mutex_exit(&sc->sc_mtx);
 	node = *rnode;
 	node.sysctl_data = buf;
 	err = sysctl_lookup(SYSCTLFN_CALL(&node));
 	if (err != 0 || newp == NULL)
 		return err;
 	return 0;
+}
 int
 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq)
+{
 	struct acpicpu_pstate *ps;
 	uint64_t val;
 	uint32_t i;
 	switch (cpu_vendor) {
 	case CPUVENDOR_INTEL:
 		val = rdmsr(MSR_PERF_STATUS);
 		val = val & 0xffff;
 		mutex_enter(&sc->sc_mtx);
 		for (i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) {
 			ps = &sc->sc_pstate[i];
 			if (ps->ps_freq == 0)
 				continue;
 			if (val == ps->ps_status) {
 				mutex_exit(&sc->sc_mtx);
 				*freq = ps->ps_freq;
 				return 0;
+			}
+		}
 		mutex_exit(&sc->sc_mtx);
 		return EIO;
 	default:
 		return ENODEV;
+	}
 	return 0;
+}
 int
 acpicpu_md_pstate_set(struct acpicpu_pstate *ps)
+{
 	struct msr_rw_info msr;
 	uint64_t xc, val;
 	int i;
 	switch (cpu_vendor) {
 	case CPUVENDOR_INTEL:
 		msr.msr_read  = true;
 		msr.msr_type  = MSR_PERF_CTL;
 		msr.msr_value = ps->ps_control;
 		msr.msr_mask  = 0xffffULL;
 		break;
 	default:
 		return ENODEV;
+	}
 	xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL);
 	xc_wait(xc);
 	for (i = val = 0; i < ACPICPU_P_STATE_RETRY; i++) {
 		val = rdmsr(MSR_PERF_STATUS);
 		val = val & 0xffff;
 		if (val == ps->ps_status)
 			return 0;
 		DELAY(ps->ps_latency);
+	}
 	return EAGAIN;
+}

 @@ -1,1132 +1,1136 @@
-/*	$NetBSD: cpu.c,v 1.74 2010/08/04 10:02:12 jruoho Exp $	*/
+/*	$NetBSD: cpu.c,v 1.75 2010/08/09 04:18:48 jruoho Exp $	*/
 /*-
  * Copyright (c) 2000, 2006, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Copyright (c) 1999 Stefan Grefen
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *      This product includes software developed by the NetBSD
  *      Foundation, Inc. and its contributors.
  * 4. Neither the name of The NetBSD Foundation nor the names of its
  *    contributors may be used to endorse or promote products derived
  *    from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.74 2010/08/04 10:02:12 jruoho Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.75 2010/08/09 04:18:48 jruoho Exp $");
 #include "opt_ddb.h"
 #include "opt_mpbios.h"		/* for MPDEBUG */
 #include "opt_mtrr.h"
 #include "lapic.h"
 #include "ioapic.h"
 #ifdef i386
 #include "npx.h"
 #endif
 #include <sys/param.h>
 #include <sys/proc.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kmem.h>
 #include <sys/cpu.h>
 #include <sys/atomic.h>
 #include <sys/reboot.h>
 #include <uvm/uvm_extern.h>
 #include <machine/cpufunc.h>
 #include <machine/cpuvar.h>
 #include <machine/pmap.h>
 #include <machine/vmparam.h>
 #include <machine/mpbiosvar.h>
 #include <machine/pcb.h>
 #include <machine/specialreg.h>
 #include <machine/segments.h>
 #include <machine/gdt.h>
 #include <machine/mtrr.h>
 #include <machine/pio.h>
 #include <machine/cpu_counter.h>
 #ifdef i386
 #include <machine/tlog.h>
 #endif
 #include <machine/apicvar.h>
 #include <machine/i82489reg.h>
 #include <machine/i82489var.h>
 #include <dev/ic/mc146818reg.h>
 #include <i386/isa/nvram.h>
 #include <dev/isa/isareg.h>
 #include "tsc.h"
 #if MAXCPUS > 32
 #error cpu_info contains 32bit bitmasks
 #endif
 int     cpu_match(device_t, cfdata_t, void *);
 void    cpu_attach(device_t, device_t, void *);
 static bool	cpu_suspend(device_t, const pmf_qual_t *);
 static bool	cpu_resume(device_t, const pmf_qual_t *);
 struct cpu_softc {
 	device_t sc_dev;		/* device tree glue */
 	struct cpu_info *sc_info;	/* pointer to CPU info */
 	bool sc_wasonline;
 };
 int mp_cpu_start(struct cpu_info *, paddr_t);
 void mp_cpu_start_cleanup(struct cpu_info *);
 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL,
 					    mp_cpu_start_cleanup };
 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc),
     cpu_match, cpu_attach, NULL, NULL);
 /*
  * Statically-allocated CPU info for the primary CPU (or the only
  * CPU, on uniprocessors).  The CPU info list is initialized to
  * point at it.
  */
 #ifdef TRAPLOG
 struct tlog tlog_primary;
 #endif
 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = {
 	.ci_dev = 0,
 	.ci_self = &cpu_info_primary,
 	.ci_idepth = -1,
 	.ci_curlwp = &lwp0,
 	.ci_curldt = -1,
 #ifdef TRAPLOG
 	.ci_tlog_base = &tlog_primary,
 #endif /* !TRAPLOG */
 };
 struct cpu_info *cpu_info_list = &cpu_info_primary;
 static void	cpu_set_tss_gates(struct cpu_info *);
 #ifdef i386
 static void	tss_init(struct i386tss *, void *, void *);
 #endif
 static void	cpu_init_idle_lwp(struct cpu_info *);
 uint32_t cpus_attached = 0;
 uint32_t cpus_running = 0;
 uint32_t cpu_feature[5]; /* X86 CPUID feature bits
 			  *	[0] basic features %edx
 			  *	[1] basic features %ecx
 			  *	[2] extended features %edx
 			  *	[3] extended features %ecx
 			  *	[4] VIA padlock features
 			  */
 extern char x86_64_doubleflt_stack[];
 bool x86_mp_online;
 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE;
 static vaddr_t cmos_data_mapping;
 struct cpu_info *cpu_starting;
 int (*cpu_freq_sysctl_get)(SYSCTLFN_PROTO) = NULL;
 int (*cpu_freq_sysctl_set)(SYSCTLFN_PROTO) = NULL;
 int (*cpu_freq_sysctl_all)(SYSCTLFN_PROTO) = NULL;
 void    	cpu_hatch(void *);
 static void    	cpu_boot_secondary(struct cpu_info *ci);
 static void    	cpu_start_secondary(struct cpu_info *ci);
 static void	cpu_copy_trampoline(void);
 /*
  * Runs once per boot once multiprocessor goo has been detected and
  * the local APIC on the boot processor has been mapped.
+ *
  * Called from lapic_boot_init() (from mpbios_scan()).
  */
 void
 cpu_init_first(void)
+{
 	cpu_info_primary.ci_cpuid = lapic_cpu_number();
 	cpu_copy_trampoline();
 	cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY);
 	if (cmos_data_mapping == 0)
 		panic("No KVA for page 0");
 	pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE, 0);
 	pmap_update(pmap_kernel());
+}
 int
 cpu_match(device_t parent, cfdata_t match, void *aux)
+{
 	return 1;
+}
 static void
 cpu_vm_init(struct cpu_info *ci)
+{
 	int ncolors = 2, i;
 	for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) {
 		struct x86_cache_info *cai;
 		int tcolors;
 		cai = &ci->ci_cinfo[i];
 		tcolors = atop(cai->cai_totalsize);
 		switch(cai->cai_associativity) {
 		case 0xff:
 			tcolors = 1; /* fully associative */
 			break;
 		case 0:
 		case 1:
 			break;
 		default:
 			tcolors /= cai->cai_associativity;
+		}
 		ncolors = max(ncolors, tcolors);
 		/*
 		 * If the desired number of colors is not a power of
 		 * two, it won't be good.  Find the greatest power of
 		 * two which is an even divisor of the number of colors,
 		 * to preserve even coloring of pages.
 		 */
 		if (ncolors & (ncolors - 1) ) {
 			int try, picked = 1;
 			for (try = 1; try < ncolors; try *= 2) {
 				if (ncolors % try == 0) picked = try;
+			}
 			if (picked == 1) {
 				panic("desired number of cache colors %d is "
 			      	" > 1, but not even!", ncolors);
+			}
 			ncolors = picked;
+		}
+	}
 	/*
 	 * Knowing the size of the largest cache on this CPU, re-color
 	 * our pages.
 	 */
 	if (ncolors <= uvmexp.ncolors)
 		return;
 	aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors);
 	uvm_page_recolor(ncolors);
+}
 void
 cpu_attach(device_t parent, device_t self, void *aux)
+{
 	struct cpu_softc *sc = device_private(self);
 	struct cpu_attach_args *caa = aux;
 	struct cpu_info *ci;
 	uintptr_t ptr;
 	int cpunum = caa->cpu_number;
 	static bool again;
 	sc->sc_dev = self;
 	if (cpus_attached == ~0) {
 		aprint_error(": increase MAXCPUS\n");
 		return;
+	}
 	/*
 	 * If we're an Application Processor, allocate a cpu_info
 	 * structure, otherwise use the primary's.
 	 */
 	if (caa->cpu_role == CPU_ROLE_AP) {
 		if ((boothowto & RB_MD1) != 0) {
 			aprint_error(": multiprocessor boot disabled\n");
 			if (!pmf_device_register(self, NULL, NULL))
 				aprint_error_dev(self,
 				    "couldn't establish power handler\n");
 			return;
+		}
 		aprint_naive(": Application Processor\n");
 		ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1,
 		    KM_SLEEP);
 		ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE);
 		ci->ci_curldt = -1;
 #ifdef TRAPLOG
 		ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP);
 #endif
 	} else {
 		aprint_naive(": %s Processor\n",
 		    caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot");
 		ci = &cpu_info_primary;
 		if (cpunum != lapic_cpu_number()) {
 			/* XXX should be done earlier. */
 			uint32_t reg;
 			aprint_verbose("\n");
 			aprint_verbose_dev(self, "running CPU at apic %d"
 			    " instead of at expected %d", lapic_cpu_number(),
 			    cpunum);
 			reg = i82489_readreg(LAPIC_ID);
 			i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) |
 			    (cpunum << LAPIC_ID_SHIFT));
+		}
 		if (cpunum != lapic_cpu_number()) {
 			aprint_error_dev(self, "unable to reset apic id\n");
+		}
+	}
 	ci->ci_self = ci;
 	sc->sc_info = ci;
 	ci->ci_dev = self;
 	ci->ci_acpiid = caa->cpu_id;
 	ci->ci_cpuid = caa->cpu_number;
 	ci->ci_func = caa->cpu_func;
 	/* Must be before mi_cpu_attach(). */
 	cpu_vm_init(ci);
 	if (caa->cpu_role == CPU_ROLE_AP) {
 		int error;
 		error = mi_cpu_attach(ci);
 		if (error != 0) {
 			aprint_normal("\n");
 			aprint_error_dev(self,
 			    "mi_cpu_attach failed with %d\n", error);
 			return;
+		}
 		cpu_init_tss(ci);
 	} else {
 		KASSERT(ci->ci_data.cpu_idlelwp != NULL);
+	}
 	ci->ci_cpumask = (1 << cpu_index(ci));
 	pmap_reference(pmap_kernel());
 	ci->ci_pmap = pmap_kernel();
 	ci->ci_tlbstate = TLBSTATE_STALE;
 	/*
 	 * Boot processor may not be attached first, but the below
 	 * must be done to allow booting other processors.
 	 */
 	if (!again) {
 		atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY);
 		/* Basic init. */
 		cpu_intr_init(ci);
 		cpu_get_tsc_freq(ci);
 		cpu_init(ci);
 		cpu_set_tss_gates(ci);
 		pmap_cpu_init_late(ci);
 		if (caa->cpu_role != CPU_ROLE_SP) {
 			/* Enable lapic. */
 			lapic_enable();
 			lapic_set_lvt();
 			lapic_calibrate_timer(ci);
+		}
 		/* Make sure DELAY() is initialized. */
 		DELAY(1);
 		again = true;
+	}
 	/* further PCB init done later. */
 	switch (caa->cpu_role) {
 	case CPU_ROLE_SP:
 		atomic_or_32(&ci->ci_flags, CPUF_SP);
 		cpu_identify(ci);
 		x86_errata();
 		x86_cpu_idle_init();
 		break;
 	case CPU_ROLE_BP:
 		atomic_or_32(&ci->ci_flags, CPUF_BSP);
 		cpu_identify(ci);
 		x86_errata();
 		x86_cpu_idle_init();
 		break;
 	case CPU_ROLE_AP:
 		/*
 		 * report on an AP
 		 */
 		cpu_intr_init(ci);
 		gdt_alloc_cpu(ci);
 		cpu_set_tss_gates(ci);
 		pmap_cpu_init_early(ci);
 		pmap_cpu_init_late(ci);
 		cpu_start_secondary(ci);
 		if (ci->ci_flags & CPUF_PRESENT) {
 			struct cpu_info *tmp;
 			cpu_identify(ci);
 			tmp = cpu_info_list;
 			while (tmp->ci_next)
 				tmp = tmp->ci_next;
 			tmp->ci_next = ci;
+		}
 		break;
 	default:
 		aprint_normal("\n");
 		panic("unknown processor type??\n");
+	}
 	pat_init(ci);
 	atomic_or_32(&cpus_attached, ci->ci_cpumask);
 	if (!pmf_device_register(self, cpu_suspend, cpu_resume))
 		aprint_error_dev(self, "couldn't establish power handler\n");
 	if (mp_verbose) {
 		struct lwp *l = ci->ci_data.cpu_idlelwp;
 		struct pcb *pcb = lwp_getpcb(l);
 		aprint_verbose_dev(self,
 		    "idle lwp at %p, idle sp at %p\n",
 		    l,
 #ifdef i386
 		    (void *)pcb->pcb_esp
 #else
 		    (void *)pcb->pcb_rsp
 #endif
 		);
+	}
+}
 /*
  * Initialize the processor appropriately.
  */
 void
 cpu_init(struct cpu_info *ci)
+{
 	lcr0(rcr0() | CR0_WP);
 	/*
 	 * On a P6 or above, enable global TLB caching if the
 	 * hardware supports it.
 	 */
 	if (cpu_feature[0] & CPUID_PGE)
 		lcr4(rcr4() | CR4_PGE);	/* enable global TLB caching */
 	/*
 	 * If we have FXSAVE/FXRESTOR, use them.
 	 */
 	if (cpu_feature[0] & CPUID_FXSR) {
 		lcr4(rcr4() | CR4_OSFXSR);
 		/*
 		 * If we have SSE/SSE2, enable XMM exceptions.
 		 */
 		if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2))
 			lcr4(rcr4() | CR4_OSXMMEXCPT);
+	}
 #ifdef MTRR
 	/*
 	 * On a P6 or above, initialize MTRR's if the hardware supports them.
 	 */
 	if (cpu_feature[0] & CPUID_MTRR) {
 		if ((ci->ci_flags & CPUF_AP) == 0)
 			i686_mtrr_init_first();
 		mtrr_init_cpu(ci);
+	}
 #ifdef i386
 	if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) {
 		/*
 		 * Must be a K6-2 Step >= 7 or a K6-III.
 		 */
 		if (CPUID2FAMILY(ci->ci_signature) == 5) {
 			if (CPUID2MODEL(ci->ci_signature) > 8 ||
 			    (CPUID2MODEL(ci->ci_signature) == 8 &&
 			     CPUID2STEPPING(ci->ci_signature) >= 7)) {
 				mtrr_funcs = &k6_mtrr_funcs;
 				k6_mtrr_init_first();
 				mtrr_init_cpu(ci);
+			}
+		}
+	}
 #endif	/* i386 */
 #endif /* MTRR */
 	atomic_or_32(&cpus_running, ci->ci_cpumask);
 	if (ci != &cpu_info_primary) {
 		/* Synchronize TSC again, and check for drift. */
 		wbinvd();
 		atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
 		tsc_sync_ap(ci);
 	} else {
 		atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
+	}
+}
 void
 cpu_boot_secondary_processors(void)
+{
 	struct cpu_info *ci;
 	u_long i;
 	/* Now that we know the number of CPUs, patch the text segment. */
 	x86_patch(false);
 	for (i=0; i < maxcpus; i++) {
 		ci = cpu_lookup(i);
 		if (ci == NULL)
 			continue;
 		if (ci->ci_data.cpu_idlelwp == NULL)
 			continue;
 		if ((ci->ci_flags & CPUF_PRESENT) == 0)
 			continue;
 		if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY))
 			continue;
 		cpu_boot_secondary(ci);
+	}
 	x86_mp_online = true;
 	/* Now that we know about the TSC, attach the timecounter. */
 	tsc_tc_init();
 	/* Enable zeroing of pages in the idle loop if we have SSE2. */
 	vm_page_zero_enable = ((cpu_feature[0] & CPUID_SSE2) != 0);
+}
 static void
 cpu_init_idle_lwp(struct cpu_info *ci)
+{
 	struct lwp *l = ci->ci_data.cpu_idlelwp;
 	struct pcb *pcb = lwp_getpcb(l);
 	pcb->pcb_cr0 = rcr0();
+}
 void
 cpu_init_idle_lwps(void)
+{
 	struct cpu_info *ci;
 	u_long i;
 	for (i = 0; i < maxcpus; i++) {
 		ci = cpu_lookup(i);
 		if (ci == NULL)
 			continue;
 		if (ci->ci_data.cpu_idlelwp == NULL)
 			continue;
 		if ((ci->ci_flags & CPUF_PRESENT) == 0)
 			continue;
 		cpu_init_idle_lwp(ci);
+	}
+}
 void
 cpu_start_secondary(struct cpu_info *ci)
+{
 	extern paddr_t mp_pdirpa;
 	u_long psl;
 	int i;
 	mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr);
 	atomic_or_32(&ci->ci_flags, CPUF_AP);
 	ci->ci_curlwp = ci->ci_data.cpu_idlelwp;
 	if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) {
 		return;
+	}
 	/*
 	 * Wait for it to become ready.   Setting cpu_starting opens the
 	 * initial gate and allows the AP to start soft initialization.
 	 */
 	KASSERT(cpu_starting == NULL);
 	cpu_starting = ci;
 	for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) {
 #ifdef MPDEBUG
 		extern int cpu_trace[3];
 		static int otrace[3];
 		if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) {
 			aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n",
 			    cpu_trace[0], cpu_trace[1], cpu_trace[2]);
 			memcpy(otrace, cpu_trace, sizeof(otrace));
+		}
 #endif
 		i8254_delay(10);
+	}
 	if ((ci->ci_flags & CPUF_PRESENT) == 0) {
 		aprint_error_dev(ci->ci_dev, "failed to become ready\n");
 #if defined(MPDEBUG) && defined(DDB)
 		printf("dropping into debugger; continue from here to resume boot\n");
 		Debugger();
 #endif
 	} else {
 		/*
 		 * Synchronize time stamp counters. Invalidate cache and do
 		 * twice to try and minimize possible cache effects. Disable
 		 * interrupts to try and rule out any external interference.
 		 */
 		psl = x86_read_psl();
 		x86_disable_intr();
 		wbinvd();
 		tsc_sync_bp(ci);
 		x86_write_psl(psl);
+	}
 	CPU_START_CLEANUP(ci);
 	cpu_starting = NULL;
+}
 void
 cpu_boot_secondary(struct cpu_info *ci)
+{
 	int64_t drift;
 	u_long psl;
 	int i;
 	atomic_or_32(&ci->ci_flags, CPUF_GO);
 	for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) {
 		i8254_delay(10);
+	}
 	if ((ci->ci_flags & CPUF_RUNNING) == 0) {
 		aprint_error_dev(ci->ci_dev, "failed to start\n");
 #if defined(MPDEBUG) && defined(DDB)
 		printf("dropping into debugger; continue from here to resume boot\n");
 		Debugger();
 #endif
 	} else {
 		/* Synchronize TSC again, check for drift. */
 		drift = ci->ci_data.cpu_cc_skew;
 		psl = x86_read_psl();
 		x86_disable_intr();
 		wbinvd();
 		tsc_sync_bp(ci);
 		x86_write_psl(psl);
 		drift -= ci->ci_data.cpu_cc_skew;
 		aprint_debug_dev(ci->ci_dev, "TSC skew=%lld drift=%lld\n",
 		    (long long)ci->ci_data.cpu_cc_skew, (long long)drift);
 		tsc_sync_drift(drift);
+	}
+}
 /*
  * The CPU ends up here when its ready to run
  * This is called from code in mptramp.s; at this point, we are running
  * in the idle pcb/idle stack of the new CPU.  When this function returns,
  * this processor will enter the idle loop and start looking for work.
  */
 void
 cpu_hatch(void *v)
+{
 	struct cpu_info *ci = (struct cpu_info *)v;
 	struct pcb *pcb;
 	int s, i;
 	cpu_init_msrs(ci, true);
 	cpu_probe(ci);
 	ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq;
 	/* cpu_get_tsc_freq(ci); */
 	KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0);
 	/*
 	 * Synchronize time stamp counters.  Invalidate cache and do twice
 	 * to try and minimize possible cache effects.  Note that interrupts
 	 * are off at this point.
 	 */
 	wbinvd();
 	atomic_or_32(&ci->ci_flags, CPUF_PRESENT);
 	tsc_sync_ap(ci);
 	/*
 	 * Wait to be brought online.  Use 'monitor/mwait' if available,
 	 * in order to make the TSC drift as much as possible. so that
 	 * we can detect it later.  If not available, try 'pause'.
 	 * We'd like to use 'hlt', but we have interrupts off.
 	 */
 	while ((ci->ci_flags & CPUF_GO) == 0) {
 		if ((cpu_feature[1] & CPUID2_MONITOR) != 0) {
 			x86_monitor(&ci->ci_flags, 0, 0);
 			if ((ci->ci_flags & CPUF_GO) != 0) {
 				continue;
+			}
 			x86_mwait(0, 0);
 		} else {
 			for (i = 10000; i != 0; i--) {
 				x86_pause();
+			}
+		}
+	}
 	/* Because the text may have been patched in x86_patch(). */
 	wbinvd();
 	x86_flush();
 	KASSERT((ci->ci_flags & CPUF_RUNNING) == 0);
 #ifdef PAE
 	pd_entry_t * l3_pd = ci->ci_pae_l3_pdir;
 	for (i = 0 ; i < PDP_SIZE; i++) {
 		l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PG_V;
+	}
 	lcr3(ci->ci_pae_l3_pdirpa);
 #else
 	lcr3(pmap_pdirpa(pmap_kernel(), 0));
 #endif
 	pcb = lwp_getpcb(curlwp);
 	pcb->pcb_cr3 = rcr3();
 	pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp);
 	lcr0(pcb->pcb_cr0);
 	cpu_init_idt();
 	gdt_init_cpu(ci);
 	lapic_enable();
 	lapic_set_lvt();
 	lapic_initclocks();
 #ifdef i386
 #if NNPX > 0
 	npxinit(ci);
 #endif
 #else
 	fpuinit(ci);
 #endif
 	lldt(GSYSSEL(GLDT_SEL, SEL_KPL));
 	ltr(ci->ci_tss_sel);
 	cpu_init(ci);
 	cpu_get_tsc_freq(ci);
 	s = splhigh();
 #ifdef i386
 	lapic_tpr = 0;
 #else
 	lcr8(0);
 #endif
 	x86_enable_intr();
 	splx(s);
 	x86_errata();
 	aprint_debug_dev(ci->ci_dev, "running\n");
+}
 #if defined(DDB)
 #include <ddb/db_output.h>
 #include <machine/db_machdep.h>
 /*
  * Dump CPU information from ddb.
  */
 void
 cpu_debug_dump(void)
+{
 	struct cpu_info *ci;
 	CPU_INFO_ITERATOR cii;
 	db_printf("addr		dev	id	flags	ipis	curlwp 		fpcurlwp\n");
 	for (CPU_INFO_FOREACH(cii, ci)) {
 		db_printf("%p	%s	%ld	%x	%x	%10p	%10p\n",
 		    ci,
 		    ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev),
 		    (long)ci->ci_cpuid,
 		    ci->ci_flags, ci->ci_ipis,
 		    ci->ci_curlwp,
 		    ci->ci_fpcurlwp);
+	}
+}
 #endif
 static void
 cpu_copy_trampoline(void)
+{
 	/*
 	 * Copy boot code.
 	 */
 	extern u_char cpu_spinup_trampoline[];
 	extern u_char cpu_spinup_trampoline_end[];
 	vaddr_t mp_trampoline_vaddr;
 	mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0,
 	    UVM_KMF_VAONLY);
 	pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr,
 	    VM_PROT_READ | VM_PROT_WRITE, 0);
 	pmap_update(pmap_kernel());
 	memcpy((void *)mp_trampoline_vaddr,
 	    cpu_spinup_trampoline,
 	    cpu_spinup_trampoline_end - cpu_spinup_trampoline);
 	pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE);
 	pmap_update(pmap_kernel());
 	uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY);
+}
 #ifdef i386
 static void
 tss_init(struct i386tss *tss, void *stack, void *func)
+{
 	KASSERT(curcpu()->ci_pmap == pmap_kernel());
 	memset(tss, 0, sizeof *tss);
 	tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16);
 	tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
 	tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL);
 	tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL);
 	tss->tss_gs = tss->__tss_es = tss->__tss_ds =
 	    tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL);
 	/* %cr3 contains the value associated to pmap_kernel */
 	tss->tss_cr3 = rcr3();
 	tss->tss_esp = (int)((char *)stack + USPACE - 16);
 	tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
 	tss->__tss_eflags = PSL_MBO | PSL_NT;	/* XXX not needed? */
 	tss->__tss_eip = (int)func;
+}
 /* XXX */
 #define IDTVEC(name)	__CONCAT(X, name)
 typedef void (vector)(void);
 extern vector IDTVEC(tss_trap08);
 #ifdef DDB
 extern vector Xintrddbipi;
 extern int ddb_vec;
 #endif
 static void
 cpu_set_tss_gates(struct cpu_info *ci)
+{
 	struct segment_descriptor sd;
 	ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
 	    UVM_KMF_WIRED);
 	tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack,
 	    IDTVEC(tss_trap08));
 	setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1,
 	    SDT_SYS386TSS, SEL_KPL, 0, 0);
 	ci->ci_gdt[GTRAPTSS_SEL].sd = sd;
 	setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
 	    GSEL(GTRAPTSS_SEL, SEL_KPL));
 #if defined(DDB)
 	/*
 	 * Set up separate handler for the DDB IPI, so that it doesn't
 	 * stomp on a possibly corrupted stack.
+	 *
 	 * XXX overwriting the gate set in db_machine_init.
 	 * Should rearrange the code so that it's set only once.
 	 */
 	ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
 	    UVM_KMF_WIRED);
 	tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, Xintrddbipi);
 	setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1,
 	    SDT_SYS386TSS, SEL_KPL, 0, 0);
 	ci->ci_gdt[GIPITSS_SEL].sd = sd;
 	setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
 	    GSEL(GIPITSS_SEL, SEL_KPL));
 #endif
+}
 #else
 static void
 cpu_set_tss_gates(struct cpu_info *ci)
+{
+}
 #endif	/* i386 */
 int
 mp_cpu_start(struct cpu_info *ci, paddr_t target)
+{
 	unsigned short dwordptr[2];
 	int error;
 	/*
 	 * Bootstrap code must be addressable in real mode
 	 * and it must be page aligned.
 	 */
 	KASSERT(target < 0x10000 && target % PAGE_SIZE == 0);
 	/*
 	 * "The BSP must initialize CMOS shutdown code to 0Ah ..."
 	 */
 	outb(IO_RTC, NVRAM_RESET);
 	outb(IO_RTC+1, NVRAM_RESET_JUMP);
 	/*
 	 * "and the warm reset vector (DWORD based at 40:67) to point
 	 * to the AP startup code ..."
 	 */
 	dwordptr[0] = 0;
 	dwordptr[1] = target >> 4;
 	memcpy((uint8_t *)cmos_data_mapping + 0x467, dwordptr, 4);
 	if ((cpu_feature[0] & CPUID_APIC) == 0) {
 		aprint_error("mp_cpu_start: CPU does not have APIC\n");
 		return ENODEV;
+	}
 	/*
 	 * ... prior to executing the following sequence:".  We'll also add in
 	 * local cache flush, in case the BIOS has left the AP with its cache
 	 * disabled.  It may not be able to cope with MP coherency.
 	 */
 	wbinvd();
 	if (ci->ci_flags & CPUF_AP) {
 		error = x86_ipi_init(ci->ci_cpuid);
 		if (error != 0) {
 			aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n",
 			    __func__);
 			return error;
+		}
 		i8254_delay(10000);
 		error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE);
 		if (error != 0) {
 			aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n",
 			    __func__);
 			return error;
+		}
 		i8254_delay(200);
 		error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE);
 		if (error != 0) {
 			aprint_error_dev(ci->ci_dev, "%s: IPI not taken (3)\n",
 			    __func__);
 			return error;
+		}
 		i8254_delay(200);
+	}
 	return 0;
+}
 void
 mp_cpu_start_cleanup(struct cpu_info *ci)
+{
 	/*
 	 * Ensure the NVRAM reset byte contains something vaguely sane.
 	 */
 	outb(IO_RTC, NVRAM_RESET);
 	outb(IO_RTC+1, NVRAM_RESET_RST);
+}
 #ifdef __x86_64__
 typedef void (vector)(void);
 extern vector Xsyscall, Xsyscall32;
 #endif
 void
 cpu_init_msrs(struct cpu_info *ci, bool full)
+{
 #ifdef __x86_64__
 	wrmsr(MSR_STAR,
 	    ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
 	    ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48));
 	wrmsr(MSR_LSTAR, (uint64_t)Xsyscall);
 	wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32);
 	wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C);
 	if (full) {
 		wrmsr(MSR_FSBASE, 0);
 		wrmsr(MSR_GSBASE, (uint64_t)ci);
 		wrmsr(MSR_KERNELGSBASE, 0);
+	}
 #endif	/* __x86_64__ */
 	if (cpu_feature[2] & CPUID_NOX)
 		wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE);
+}
 void
 cpu_offline_md(void)
+{
 	int s;
 	s = splhigh();
 #ifdef i386
 #if NNPX > 0
 	npxsave_cpu(true);
 #endif
 #else
 	fpusave_cpu(true);
 #endif
 	splx(s);
+}
 /* XXX joerg restructure and restart CPUs individually */
 static bool
 cpu_suspend(device_t dv, const pmf_qual_t *qual)
+{
 	struct cpu_softc *sc = device_private(dv);
 	struct cpu_info *ci = sc->sc_info;
 	int err;
 	if (ci->ci_flags & CPUF_PRIMARY)
 		return true;
 	if (ci->ci_data.cpu_idlelwp == NULL)
 		return true;
 	if ((ci->ci_flags & CPUF_PRESENT) == 0)
 		return true;
 	sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE);
 	if (sc->sc_wasonline) {
 		mutex_enter(&cpu_lock);
 		err = cpu_setstate(ci, false);
 		mutex_exit(&cpu_lock);
 		if (err)
 			return false;
+	}
 	return true;
+}
 static bool
 cpu_resume(device_t dv, const pmf_qual_t *qual)
+{
 	struct cpu_softc *sc = device_private(dv);
 	struct cpu_info *ci = sc->sc_info;
 	int err = 0;
 	if (ci->ci_flags & CPUF_PRIMARY)
 		return true;
 	if (ci->ci_data.cpu_idlelwp == NULL)
 		return true;
 	if ((ci->ci_flags & CPUF_PRESENT) == 0)
 		return true;
 	if (sc->sc_wasonline) {
 		mutex_enter(&cpu_lock);
 		err = cpu_setstate(ci, true);
 		mutex_exit(&cpu_lock);
+	}
 	return err == 0;
+}
 void
 cpu_get_tsc_freq(struct cpu_info *ci)
+{
 	uint64_t last_tsc;
 	if (cpu_hascounter()) {
 		last_tsc = rdmsr(MSR_TSC);
 		i8254_delay(100000);
 		ci->ci_data.cpu_cc_freq = (rdmsr(MSR_TSC) - last_tsc) * 10;
+	}
+}
 void
 x86_cpu_idle_mwait(void)
+{
 	struct cpu_info *ci = curcpu();
 	KASSERT(ci->ci_ilevel == IPL_NONE);
 	x86_monitor(&ci->ci_want_resched, 0, 0);
 	if (__predict_false(ci->ci_want_resched)) {
 		return;
+	}
 	x86_mwait(0, 0);
+}
 void
 x86_cpu_idle_halt(void)
+{
 	struct cpu_info *ci = curcpu();
 	KASSERT(ci->ci_ilevel == IPL_NONE);
 	x86_disable_intr();
 	if (!__predict_false(ci->ci_want_resched)) {
 		x86_stihlt();
 	} else {
 		x86_enable_intr();
+	}
+}
 /*
  * Loads pmap for the current CPU.
  */
 void
 cpu_load_pmap(struct pmap *pmap)
+{
 #ifdef PAE
 	int i, s;
 	struct cpu_info *ci;
 	s = splvm(); /* just to be safe */
 	ci = curcpu();
 	pd_entry_t *l3_pd = ci->ci_pae_l3_pdir;
 	for (i = 0 ; i < PDP_SIZE; i++) {
 		l3_pd[i] = pmap->pm_pdirpa[i] | PG_V;
+	}
 	splx(s);
 	tlbflush();
 #else /* PAE */
 	lcr3(pmap_pdirpa(pmap, 0));
 #endif /* PAE */
+}

 @@ -1,1359 +1,1355 @@
-/*	$NetBSD: est.c,v 1.16 2010/08/08 16:58:42 jruoho Exp $	*/
+/*	$NetBSD: est.c,v 1.17 2010/08/09 04:18:49 jruoho Exp $	*/
 /*
  * Copyright (c) 2003 Michael Eriksson.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /*-
  * Copyright (c) 2004 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * This is a driver for Intel's Enhanced SpeedStep Technology (EST),
  * as implemented in Pentium M processors.
+ *
  * Reference documentation:
+ *
  * - IA-32 Intel Architecture Software Developer's Manual, Volume 3:
  *   System Programming Guide.
  *   Section 13.14, Enhanced Intel SpeedStep technology.
  *   Table B-2, MSRs in Pentium M Processors.
  *   http://www.intel.com/design/pentium4/manuals/253668.htm
+ *
  * - Intel Pentium M Processor Datasheet.
  *   Table 5, Voltage and Current Specifications.
  *   http://www.intel.com/design/mobile/datashts/252612.htm
+ *
  * - Intel Pentium M Processor on 90 nm Process with 2-MB L2 Cache Datasheet
  *   Table 3-4, 3-5, 3-6, Voltage and Current Specifications.
  *   http://www.intel.com/design/mobile/datashts/302189.htm
+ *
  * - Linux cpufreq patches, speedstep-centrino.c.
  *   Encoding of MSR_PERF_CTL and MSR_PERF_STATUS.
  *   http://www.codemonkey.org.uk/projects/cpufreq/cpufreq-2.4.22-pre6-1.gz
+ *
  *   ACPI objects: _PCT is MSR location, _PSS is freq/voltage, _PPC is caps.
  */
 /* #define EST_DEBUG */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: est.c,v 1.16 2010/08/08 16:58:42 jruoho Exp $");
+__KERNEL_RCSID(0, "$NetBSD: est.c,v 1.17 2010/08/09 04:18:49 jruoho Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <sys/sysctl.h>
 #include <sys/once.h>
 #include <sys/xcall.h>
 #include <x86/cpuvar.h>
 #include <x86/cputypes.h>
 #include <x86/cpu_msr.h>
 #include <machine/cpu.h>
 #include <machine/specialreg.h>
 #include "opt_est.h"
 #ifdef EST_FREQ_USERWRITE
 #define	EST_TARGET_CTLFLAG	(CTLFLAG_READWRITE | CTLFLAG_ANYWRITE)
 #else
 #define	EST_TARGET_CTLFLAG	CTLFLAG_READWRITE
 #endif
 /* Convert MHz and mV into IDs for passing to the MSR. */
 #define ID16(MHz, mV, bus_clk) \
 	((((MHz * 100 + 50) / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
 /* Possible bus speeds (multiplied by 100 for rounding) */
 enum { BUS100 = 10000, BUS133 = 13333, BUS166 = 16666, BUS200 = 20000 };
 /* Ultra Low Voltage Intel Pentium M processor 900 MHz */
 static const uint16_t pm130_900_ulv[] = {
 	ID16( 900, 1004, BUS100),
 	ID16( 800,  988, BUS100),
 	ID16( 600,  844, BUS100),
 };
 /* Ultra Low Voltage Intel Pentium M processor 1.00 GHz */
 static const uint16_t pm130_1000_ulv[] = {
 	ID16(1000, 1004, BUS100),
 	ID16( 900,  988, BUS100),
 	ID16( 800,  972, BUS100),
 	ID16( 600,  844, BUS100),
 };
 /* Ultra Low Voltage Intel Pentium M processor 1.10 GHz */
 static const uint16_t pm130_1100_ulv[] = {
 	ID16(1100, 1004, BUS100),
 	ID16(1000,  988, BUS100),
 	ID16( 900,  972, BUS100),
 	ID16( 800,  956, BUS100),
 	ID16( 600,  844, BUS100),
 };
 /* Low Voltage Intel Pentium M processor 1.10 GHz */
 static const uint16_t pm130_1100_lv[] = {
 	ID16(1100, 1180, BUS100),
 	ID16(1000, 1164, BUS100),
 	ID16( 900, 1100, BUS100),
 	ID16( 800, 1020, BUS100),
 	ID16( 600,  956, BUS100),
 };
 /* Low Voltage Intel Pentium M processor 1.20 GHz */
 static const uint16_t pm130_1200_lv[] = {
 	ID16(1200, 1180, BUS100),
 	ID16(1100, 1164, BUS100),
 	ID16(1000, 1100, BUS100),
 	ID16( 900, 1020, BUS100),
 	ID16( 800, 1004, BUS100),
 	ID16( 600,  956, BUS100),
 };
 /* Low Voltage Intel Pentium M processor 1.30 GHz */
 static const uint16_t pm130_1300_lv[] = {
 	ID16(1300, 1180, BUS100),
 	ID16(1200, 1164, BUS100),
 	ID16(1100, 1100, BUS100),
 	ID16(1000, 1020, BUS100),
 	ID16( 900, 1004, BUS100),
 	ID16( 800,  988, BUS100),
 	ID16( 600,  956, BUS100),
 };
 /* Intel Pentium M processor 1.30 GHz */
 static const uint16_t pm130_1300[] = {
 	ID16(1300, 1388, BUS100),
 	ID16(1200, 1356, BUS100),
 	ID16(1000, 1292, BUS100),
 	ID16( 800, 1260, BUS100),
 	ID16( 600,  956, BUS100),
 };
 /* Intel Pentium M processor 1.40 GHz */
 static const uint16_t pm130_1400[] = {
 	ID16(1400, 1484, BUS100),
 	ID16(1200, 1436, BUS100),
 	ID16(1000, 1308, BUS100),
 	ID16( 800, 1180, BUS100),
 	ID16( 600,  956, BUS100),
 };
 /* Intel Pentium M processor 1.50 GHz */
 static const uint16_t pm130_1500[] = {
 	ID16(1500, 1484, BUS100),
 	ID16(1400, 1452, BUS100),
 	ID16(1200, 1356, BUS100),
 	ID16(1000, 1228, BUS100),
 	ID16( 800, 1116, BUS100),
 	ID16( 600,  956, BUS100),
 };
 /* Intel Pentium M processor 1.60 GHz */
 static const uint16_t pm130_1600[] = {
 	ID16(1600, 1484, BUS100),
 	ID16(1400, 1420, BUS100),
 	ID16(1200, 1276, BUS100),
 	ID16(1000, 1164, BUS100),
 	ID16( 800, 1036, BUS100),
 	ID16( 600,  956, BUS100),
 };
 /* Intel Pentium M processor 1.70 GHz */
 static const uint16_t pm130_1700[] = {
 	ID16(1700, 1484, BUS100),
 	ID16(1400, 1308, BUS100),
 	ID16(1200, 1228, BUS100),
 	ID16(1000, 1116, BUS100),
 	ID16( 800, 1004, BUS100),
 	ID16( 600,  956, BUS100),
 };
 /* Intel Pentium M processor 723 1.0 GHz */
 static const uint16_t pm90_n723[] = {
 	ID16(1000,  940, BUS100),
 	ID16( 900,  908, BUS100),
 	ID16( 800,  876, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 733 1.1 GHz, VID #G */
 static const uint16_t pm90_n733g[] = {
 	ID16(1100,  956, BUS100),
 	ID16(1000,  940, BUS100),
 	ID16( 900,  908, BUS100),
 	ID16( 800,  876, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 733 1.1 GHz, VID #H */
 static const uint16_t pm90_n733h[] = {
 	ID16(1100,  940, BUS100),
 	ID16(1000,  924, BUS100),
 	ID16( 900,  892, BUS100),
 	ID16( 800,  876, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 733 1.1 GHz, VID #I */
 static const uint16_t pm90_n733i[] = {
 	ID16(1100,  924, BUS100),
 	ID16(1000,  908, BUS100),
 	ID16( 900,  892, BUS100),
 	ID16( 800,  860, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 733 1.1 GHz, VID #J */
 static const uint16_t pm90_n733j[] = {
 	ID16(1100,  908, BUS100),
 	ID16(1000,  892, BUS100),
 	ID16( 900,  876, BUS100),
 	ID16( 800,  860, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 733 1.1 GHz, VID #K */
 static const uint16_t pm90_n733k[] = {
 	ID16(1100,  892, BUS100),
 	ID16(1000,  876, BUS100),
 	ID16( 900,  860, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 733 1.1 GHz, VID #L */
 static const uint16_t pm90_n733l[] = {
 	ID16(1100,  876, BUS100),
 	ID16(1000,  876, BUS100),
 	ID16( 900,  860, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 753 1.2 GHz, VID #G */
 static const uint16_t pm90_n753g[] = {
 	ID16(1200,  956, BUS100),
 	ID16(1100,  940, BUS100),
 	ID16(1000,  908, BUS100),
 	ID16( 900,  892, BUS100),
 	ID16( 800,  860, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 753 1.2 GHz, VID #H */
 static const uint16_t pm90_n753h[] = {
 	ID16(1200,  940, BUS100),
 	ID16(1100,  924, BUS100),
 	ID16(1000,  908, BUS100),
 	ID16( 900,  876, BUS100),
 	ID16( 800,  860, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 753 1.2 GHz, VID #I */
 static const uint16_t pm90_n753i[] = {
 	ID16(1200,  924, BUS100),
 	ID16(1100,  908, BUS100),
 	ID16(1000,  892, BUS100),
 	ID16( 900,  876, BUS100),
 	ID16( 800,  860, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 753 1.2 GHz, VID #J */
 static const uint16_t pm90_n753j[] = {
 	ID16(1200,  908, BUS100),
 	ID16(1100,  892, BUS100),
 	ID16(1000,  876, BUS100),
 	ID16( 900,  860, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 753 1.2 GHz, VID #K */
 static const uint16_t pm90_n753k[] = {
 	ID16(1200,  892, BUS100),
 	ID16(1100,  892, BUS100),
 	ID16(1000,  876, BUS100),
 	ID16( 900,  860, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 753 1.2 GHz, VID #L */
 static const uint16_t pm90_n753l[] = {
 	ID16(1200,  876, BUS100),
 	ID16(1100,  876, BUS100),
 	ID16(1000,  860, BUS100),
 	ID16( 900,  844, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 773 1.3 GHz, VID #G */
 static const uint16_t pm90_n773g[] = {
 	ID16(1300,  956, BUS100),
 	ID16(1200,  940, BUS100),
 	ID16(1100,  924, BUS100),
 	ID16(1000,  908, BUS100),
 	ID16( 900,  876, BUS100),
 	ID16( 800,  860, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 773 1.3 GHz, VID #H */
 static const uint16_t pm90_n773h[] = {
 	ID16(1300,  940, BUS100),
 	ID16(1200,  924, BUS100),
 	ID16(1100,  908, BUS100),
 	ID16(1000,  892, BUS100),
 	ID16( 900,  876, BUS100),
 	ID16( 800,  860, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 773 1.3 GHz, VID #I */
 static const uint16_t pm90_n773i[] = {
 	ID16(1300,  924, BUS100),
 	ID16(1200,  908, BUS100),
 	ID16(1100,  892, BUS100),
 	ID16(1000,  876, BUS100),
 	ID16( 900,  860, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 773 1.3 GHz, VID #J */
 static const uint16_t pm90_n773j[] = {
 	ID16(1300,  908, BUS100),
 	ID16(1200,  908, BUS100),
 	ID16(1100,  892, BUS100),
 	ID16(1000,  876, BUS100),
 	ID16( 900,  860, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 773 1.3 GHz, VID #K */
 static const uint16_t pm90_n773k[] = {
 	ID16(1300,  892, BUS100),
 	ID16(1200,  892, BUS100),
 	ID16(1100,  876, BUS100),
 	ID16(1000,  860, BUS100),
 	ID16( 900,  860, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 773 1.3 GHz, VID #L */
 static const uint16_t pm90_n773l[] = {
 	ID16(1300,  876, BUS100),
 	ID16(1200,  876, BUS100),
 	ID16(1100,  860, BUS100),
 	ID16(1000,  860, BUS100),
 	ID16( 900,  844, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  812, BUS100),
 };
 /* Intel Pentium M processor 738 1.4 GHz */
 static const uint16_t pm90_n738[] = {
 	ID16(1400, 1116, BUS100),
 	ID16(1300, 1116, BUS100),
 	ID16(1200, 1100, BUS100),
 	ID16(1100, 1068, BUS100),
 	ID16(1000, 1052, BUS100),
 	ID16( 900, 1036, BUS100),
 	ID16( 800, 1020, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 758 1.5 GHz */
 static const uint16_t pm90_n758[] = {
 	ID16(1500, 1116, BUS100),
 	ID16(1400, 1116, BUS100),
 	ID16(1300, 1100, BUS100),
 	ID16(1200, 1084, BUS100),
 	ID16(1100, 1068, BUS100),
 	ID16(1000, 1052, BUS100),
 	ID16( 900, 1036, BUS100),
 	ID16( 800, 1020, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 778 1.6 GHz */
 static const uint16_t pm90_n778[] = {
 	ID16(1600, 1116, BUS100),
 	ID16(1500, 1116, BUS100),
 	ID16(1400, 1100, BUS100),
 	ID16(1300, 1184, BUS100),
 	ID16(1200, 1068, BUS100),
 	ID16(1100, 1052, BUS100),
 	ID16(1000, 1052, BUS100),
 	ID16( 900, 1036, BUS100),
 	ID16( 800, 1020, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 710 1.4 GHz, 533 MHz FSB */
 static const uint16_t pm90_n710[] = {
 	ID16(1400, 1340, BUS133),
 	ID16(1200, 1228, BUS133),
 	ID16(1000, 1148, BUS133),
 	ID16( 800, 1068, BUS133),
 	ID16( 600,  998, BUS133),
 };
 /* Intel Pentium M processor 715 1.5 GHz, VID #A */
 static const uint16_t pm90_n715a[] = {
 	ID16(1500, 1340, BUS100),
 	ID16(1200, 1228, BUS100),
 	ID16(1000, 1148, BUS100),
 	ID16( 800, 1068, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 715 1.5 GHz, VID #B */
 static const uint16_t pm90_n715b[] = {
 	ID16(1500, 1324, BUS100),
 	ID16(1200, 1212, BUS100),
 	ID16(1000, 1148, BUS100),
 	ID16( 800, 1068, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 715 1.5 GHz, VID #C */
 static const uint16_t pm90_n715c[] = {
 	ID16(1500, 1308, BUS100),
 	ID16(1200, 1212, BUS100),
 	ID16(1000, 1132, BUS100),
 	ID16( 800, 1068, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 715 1.5 GHz, VID #D */
 static const uint16_t pm90_n715d[] = {
 	ID16(1500, 1276, BUS100),
 	ID16(1200, 1180, BUS100),
 	ID16(1000, 1116, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 725 1.6 GHz, VID #A */
 static const uint16_t pm90_n725a[] = {
 	ID16(1600, 1340, BUS100),
 	ID16(1400, 1276, BUS100),
 	ID16(1200, 1212, BUS100),
 	ID16(1000, 1132, BUS100),
 	ID16( 800, 1068, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 725 1.6 GHz, VID #B */
 static const uint16_t pm90_n725b[] = {
 	ID16(1600, 1324, BUS100),
 	ID16(1400, 1260, BUS100),
 	ID16(1200, 1196, BUS100),
 	ID16(1000, 1132, BUS100),
 	ID16( 800, 1068, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 725 1.6 GHz, VID #C */
 static const uint16_t pm90_n725c[] = {
 	ID16(1600, 1308, BUS100),
 	ID16(1400, 1244, BUS100),
 	ID16(1200, 1180, BUS100),
 	ID16(1000, 1116, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 725 1.6 GHz, VID #D */
 static const uint16_t pm90_n725d[] = {
 	ID16(1600, 1276, BUS100),
 	ID16(1400, 1228, BUS100),
 	ID16(1200, 1164, BUS100),
 	ID16(1000, 1116, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 730 1.6 GHz, 533 MHz FSB */
 static const uint16_t pm90_n730[] = {
        ID16(1600, 1308, BUS133),
        ID16(1333, 1260, BUS133),
        ID16(1200, 1212, BUS133),
        ID16(1067, 1180, BUS133),
        ID16( 800,  988, BUS133),
 };
 /* Intel Pentium M processor 735 1.7 GHz, VID #A */
 static const uint16_t pm90_n735a[] = {
 	ID16(1700, 1340, BUS100),
 	ID16(1400, 1244, BUS100),
 	ID16(1200, 1180, BUS100),
 	ID16(1000, 1116, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 735 1.7 GHz, VID #B */
 static const uint16_t pm90_n735b[] = {
 	ID16(1700, 1324, BUS100),
 	ID16(1400, 1244, BUS100),
 	ID16(1200, 1180, BUS100),
 	ID16(1000, 1116, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 735 1.7 GHz, VID #C */
 static const uint16_t pm90_n735c[] = {
 	ID16(1700, 1308, BUS100),
 	ID16(1400, 1228, BUS100),
 	ID16(1200, 1164, BUS100),
 	ID16(1000, 1116, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 735 1.7 GHz, VID #D */
 static const uint16_t pm90_n735d[] = {
 	ID16(1700, 1276, BUS100),
 	ID16(1400, 1212, BUS100),
 	ID16(1200, 1148, BUS100),
 	ID16(1000, 1100, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 740 1.73 GHz, 533 MHz FSB */
 static const uint16_t pm90_n740[] = {
        ID16(1733, 1356, BUS133),
        ID16(1333, 1212, BUS133),
        ID16(1067, 1100, BUS133),
        ID16( 800,  988, BUS133),
 };
 /* Intel Pentium M processor 745 1.8 GHz, VID #A */
 static const uint16_t pm90_n745a[] = {
 	ID16(1800, 1340, BUS100),
 	ID16(1600, 1292, BUS100),
 	ID16(1400, 1228, BUS100),
 	ID16(1200, 1164, BUS100),
 	ID16(1000, 1116, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 745 1.8 GHz, VID #B */
 static const uint16_t pm90_n745b[] = {
 	ID16(1800, 1324, BUS100),
 	ID16(1600, 1276, BUS100),
 	ID16(1400, 1212, BUS100),
 	ID16(1200, 1164, BUS100),
 	ID16(1000, 1116, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 745 1.8 GHz, VID #C */
 static const uint16_t pm90_n745c[] = {
 	ID16(1800, 1308, BUS100),
 	ID16(1600, 1260, BUS100),
 	ID16(1400, 1212, BUS100),
 	ID16(1200, 1148, BUS100),
 	ID16(1000, 1100, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 745 1.8 GHz, VID #D */
 static const uint16_t pm90_n745d[] = {
 	ID16(1800, 1276, BUS100),
 	ID16(1600, 1228, BUS100),
 	ID16(1400, 1180, BUS100),
 	ID16(1200, 1132, BUS100),
 	ID16(1000, 1084, BUS100),
 	ID16( 800, 1036, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 750 1.86 GHz, 533 MHz FSB */
 /* values extracted from \_PR\NPSS (via _PSS) SDST ACPI table */
 static const uint16_t pm90_n750[] = {
 	ID16(1867, 1308, BUS133),
 	ID16(1600, 1228, BUS133),
 	ID16(1333, 1148, BUS133),
 	ID16(1067, 1068, BUS133),
 	ID16( 800,  988, BUS133),
 };
 /* Intel Pentium M processor 755 2.0 GHz, VID #A */
 static const uint16_t pm90_n755a[] = {
 	ID16(2000, 1340, BUS100),
 	ID16(1800, 1292, BUS100),
 	ID16(1600, 1244, BUS100),
 	ID16(1400, 1196, BUS100),
 	ID16(1200, 1148, BUS100),
 	ID16(1000, 1100, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 755 2.0 GHz, VID #B */
 static const uint16_t pm90_n755b[] = {
 	ID16(2000, 1324, BUS100),
 	ID16(1800, 1276, BUS100),
 	ID16(1600, 1228, BUS100),
 	ID16(1400, 1180, BUS100),
 	ID16(1200, 1132, BUS100),
 	ID16(1000, 1084, BUS100),
 	ID16( 800, 1036, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 755 2.0 GHz, VID #C */
 static const uint16_t pm90_n755c[] = {
 	ID16(2000, 1308, BUS100),
 	ID16(1800, 1276, BUS100),
 	ID16(1600, 1228, BUS100),
 	ID16(1400, 1180, BUS100),
 	ID16(1200, 1132, BUS100),
 	ID16(1000, 1084, BUS100),
 	ID16( 800, 1036, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 755 2.0 GHz, VID #D */
 static const uint16_t pm90_n755d[] = {
 	ID16(2000, 1276, BUS100),
 	ID16(1800, 1244, BUS100),
 	ID16(1600, 1196, BUS100),
 	ID16(1400, 1164, BUS100),
 	ID16(1200, 1116, BUS100),
 	ID16(1000, 1084, BUS100),
 	ID16( 800, 1036, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 760 2.0 GHz, 533 MHz FSB */
 static const uint16_t pm90_n760[] = {
 	ID16(2000, 1356, BUS133),
 	ID16(1600, 1244, BUS133),
 	ID16(1333, 1164, BUS133),
 	ID16(1067, 1084, BUS133),
 	ID16( 800,  988, BUS133),
 };
 /* Intel Pentium M processor 765 2.1 GHz, VID #A */
 static const uint16_t pm90_n765a[] = {
 	ID16(2100, 1340, BUS100),
 	ID16(1800, 1276, BUS100),
 	ID16(1600, 1228, BUS100),
 	ID16(1400, 1180, BUS100),
 	ID16(1200, 1132, BUS100),
 	ID16(1000, 1084, BUS100),
 	ID16( 800, 1036, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 765 2.1 GHz, VID #B */
 static const uint16_t pm90_n765b[] = {
 	ID16(2100, 1324, BUS100),
 	ID16(1800, 1260, BUS100),
 	ID16(1600, 1212, BUS100),
 	ID16(1400, 1180, BUS100),
 	ID16(1200, 1132, BUS100),
 	ID16(1000, 1084, BUS100),
 	ID16( 800, 1036, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 765 2.1 GHz, VID #C */
 static const uint16_t pm90_n765c[] = {
 	ID16(2100, 1308, BUS100),
 	ID16(1800, 1244, BUS100),
 	ID16(1600, 1212, BUS100),
 	ID16(1400, 1164, BUS100),
 	ID16(1200, 1116, BUS100),
 	ID16(1000, 1084, BUS100),
 	ID16( 800, 1036, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 765 2.1 GHz, VID #E */
 static const uint16_t pm90_n765e[] = {
 	ID16(2100, 1356, BUS100),
 	ID16(1800, 1292, BUS100),
 	ID16(1600, 1244, BUS100),
 	ID16(1400, 1196, BUS100),
 	ID16(1200, 1148, BUS100),
 	ID16(1000, 1100, BUS100),
 	ID16( 800, 1052, BUS100),
 	ID16( 600,  988, BUS100),
 };
 /* Intel Pentium M processor 770 2.13 GHz */
 static const uint16_t pm90_n770[] = {
 	ID16(2133, 1356, BUS133),
 	ID16(1867, 1292, BUS133),
 	ID16(1600, 1212, BUS133),
 	ID16(1333, 1148, BUS133),
 	ID16(1067, 1068, BUS133),
 	ID16( 800,  988, BUS133),
 };
 /* Intel Pentium M processor 780 2.26 GHz */
 static const uint16_t pm90_n780[] = {
 	ID16(2267, 1388, BUS133),
 	ID16(1867, 1292, BUS133),
 	ID16(1600, 1212, BUS133),
 	ID16(1333, 1148, BUS133),
 	ID16(1067, 1068, BUS133),
 	ID16( 800,  988, BUS133),
 };
 /*
  * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
  * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
  */
 /* 1.00GHz Centaur C7-M ULV */
 static const uint16_t C7M_770_ULV[] = {
 	ID16(1000,  844, BUS100),
 	ID16( 800,  796, BUS100),
 	ID16( 600,  796, BUS100),
 	ID16( 400,  796, BUS100),
 };
 /* 1.00GHz Centaur C7-M ULV */
 static const uint16_t C7M_779_ULV[] = {
 	ID16(1000,  796, BUS100),
 	ID16( 800,  796, BUS100),
 	ID16( 600,  796, BUS100),
 	ID16( 400,  796, BUS100),
 };
 /* 1.20GHz Centaur C7-M ULV */
 static const uint16_t C7M_772_ULV[] = {
 	ID16(1200,  844, BUS100),
 	ID16(1000,  844, BUS100),
 	ID16( 800,  828, BUS100),
 	ID16( 600,  796, BUS100),
 	ID16( 400,  796, BUS100),
 };
 /* 1.50GHz Centaur C7-M ULV */
 static const uint16_t C7M_775_ULV[] = {
 	ID16(1500,  956, BUS100),
 	ID16(1400,  940, BUS100),
 	ID16(1000,  860, BUS100),
 	ID16( 800,  828, BUS100),
 	ID16( 600,  796, BUS100),
 	ID16( 400,  796, BUS100),
 };
 /* 1.20GHz Centaur C7-M 400 MHz FSB */
 static const uint16_t C7M_771[] = {
 	ID16(1200,  860, BUS100),
 	ID16(1000,  860, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  844, BUS100),
 	ID16( 400,  844, BUS100),
 };
 /* 1.50GHz Centaur C7-M 400 MHz FSB */
 static const uint16_t C7M_754[] = {
 	ID16(1500, 1004, BUS100),
 	ID16(1400,  988, BUS100),
 	ID16(1000,  940, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  844, BUS100),
 	ID16( 400,  844, BUS100),
 };
 /* 1.60GHz Centaur C7-M 400 MHz FSB */
 static const uint16_t C7M_764[] = {
 	ID16(1600, 1084, BUS100),
 	ID16(1400, 1052, BUS100),
 	ID16(1000, 1004, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  844, BUS100),
 	ID16( 400,  844, BUS100),
 };
 /* 1.80GHz Centaur C7-M 400 MHz FSB */
 static const uint16_t C7M_784[] = {
 	ID16(1800, 1148, BUS100),
 	ID16(1600, 1100, BUS100),
 	ID16(1400, 1052, BUS100),
 	ID16(1000, 1004, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  844, BUS100),
 	ID16( 400,  844, BUS100),
 };
 /* 2.00GHz Centaur C7-M 400 MHz FSB */
 static const uint16_t C7M_794[] = {
 	ID16(2000, 1148, BUS100),
 	ID16(1800, 1132, BUS100),
 	ID16(1600, 1100, BUS100),
 	ID16(1400, 1052, BUS100),
 	ID16(1000, 1004, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  844, BUS100),
 	ID16( 400,  844, BUS100),
 };
 /* 1.60GHz Centaur C7-M 533 MHz FSB */
 static const uint16_t C7M_765[] = {
 	ID16(1600, 1084, BUS133),
 	ID16(1467, 1052, BUS133),
 	ID16(1200, 1004, BUS133),
 	ID16( 800,  844, BUS133),
 	ID16( 667,  844, BUS133),
 	ID16( 533,  844, BUS133),
 };
 /* 2.00GHz Centaur C7-M 533 MHz FSB */
 static const uint16_t C7M_785[] = {
 	ID16(1867, 1148, BUS133),
 	ID16(1600, 1100, BUS133),
 	ID16(1467, 1052, BUS133),
 	ID16(1200, 1004, BUS133),
 	ID16( 800,  844, BUS133),
 	ID16( 667,  844, BUS133),
 	ID16( 533,  844, BUS133),
 };
 /* 2.00GHz Centaur C7-M 533 MHz FSB */
 static const uint16_t C7M_795[] = {
 	ID16(2000, 1148, BUS133),
 	ID16(1867, 1132, BUS133),
 	ID16(1600, 1100, BUS133),
 	ID16(1467, 1052, BUS133),
 	ID16(1200, 1004, BUS133),
 	ID16( 800,  844, BUS133),
 	ID16( 667,  844, BUS133),
 	ID16( 533,  844, BUS133),
 };
 /* 1.00GHz VIA Eden 90nm 'Esther' */
 static const uint16_t eden90_1000[] = {
 	ID16(1000,  844, BUS100),
 	ID16( 800,  844, BUS100),
 	ID16( 600,  844, BUS100),
 	ID16( 400,  844, BUS100),
 };
 struct fqlist {
 	int vendor;
 	unsigned bus_clk;
 	unsigned n;
 	const uint16_t *table;
 };
 #define ENTRY(ven, bus_clk, tab) \
 	{ CPUVENDOR_##ven, bus_clk == BUS133 ? 1 : 0, __arraycount(tab), tab }
 #define BUS_CLK(fqp) ((fqp)->bus_clk ? BUS133 : BUS100)
 static const struct fqlist est_cpus[] = {
 	ENTRY(INTEL, BUS100, pm130_900_ulv),
 	ENTRY(INTEL, BUS100, pm130_1000_ulv),
 	ENTRY(INTEL, BUS100, pm130_1100_ulv),
 	ENTRY(INTEL, BUS100, pm130_1100_lv),
 	ENTRY(INTEL, BUS100, pm130_1200_lv),
 	ENTRY(INTEL, BUS100, pm130_1300_lv),
 	ENTRY(INTEL, BUS100, pm130_1300),
 	ENTRY(INTEL, BUS100, pm130_1400),
 	ENTRY(INTEL, BUS100, pm130_1500),
 	ENTRY(INTEL, BUS100, pm130_1600),
 	ENTRY(INTEL, BUS100, pm130_1700),
 	ENTRY(INTEL, BUS100, pm90_n723),
 	ENTRY(INTEL, BUS100, pm90_n733g),
 	ENTRY(INTEL, BUS100, pm90_n733h),
 	ENTRY(INTEL, BUS100, pm90_n733i),
 	ENTRY(INTEL, BUS100, pm90_n733j),
 	ENTRY(INTEL, BUS100, pm90_n733k),
 	ENTRY(INTEL, BUS100, pm90_n733l),
 	ENTRY(INTEL, BUS100, pm90_n753g),
 	ENTRY(INTEL, BUS100, pm90_n753h),
 	ENTRY(INTEL, BUS100, pm90_n753i),
 	ENTRY(INTEL, BUS100, pm90_n753j),
 	ENTRY(INTEL, BUS100, pm90_n753k),
 	ENTRY(INTEL, BUS100, pm90_n753l),
 	ENTRY(INTEL, BUS100, pm90_n773g),
 	ENTRY(INTEL, BUS100, pm90_n773h),
 	ENTRY(INTEL, BUS100, pm90_n773i),
 	ENTRY(INTEL, BUS100, pm90_n773j),
 	ENTRY(INTEL, BUS100, pm90_n773k),
 	ENTRY(INTEL, BUS100, pm90_n773l),
 	ENTRY(INTEL, BUS100, pm90_n738),
 	ENTRY(INTEL, BUS100, pm90_n758),
 	ENTRY(INTEL, BUS100, pm90_n778),
 	ENTRY(INTEL, BUS133, pm90_n710),
 	ENTRY(INTEL, BUS100, pm90_n715a),
 	ENTRY(INTEL, BUS100, pm90_n715b),
 	ENTRY(INTEL, BUS100, pm90_n715c),
 	ENTRY(INTEL, BUS100, pm90_n715d),
 	ENTRY(INTEL, BUS100, pm90_n725a),
 	ENTRY(INTEL, BUS100, pm90_n725b),
 	ENTRY(INTEL, BUS100, pm90_n725c),
 	ENTRY(INTEL, BUS100, pm90_n725d),
 	ENTRY(INTEL, BUS133, pm90_n730),
 	ENTRY(INTEL, BUS100, pm90_n735a),
 	ENTRY(INTEL, BUS100, pm90_n735b),
 	ENTRY(INTEL, BUS100, pm90_n735c),
 	ENTRY(INTEL, BUS100, pm90_n735d),
 	ENTRY(INTEL, BUS133, pm90_n740),
 	ENTRY(INTEL, BUS100, pm90_n745a),
 	ENTRY(INTEL, BUS100, pm90_n745b),
 	ENTRY(INTEL, BUS100, pm90_n745c),
 	ENTRY(INTEL, BUS100, pm90_n745d),
 	ENTRY(INTEL, BUS133, pm90_n750),
 	ENTRY(INTEL, BUS100, pm90_n755a),
 	ENTRY(INTEL, BUS100, pm90_n755b),
 	ENTRY(INTEL, BUS100, pm90_n755c),
 	ENTRY(INTEL, BUS100, pm90_n755d),
 	ENTRY(INTEL, BUS133, pm90_n760),
 	ENTRY(INTEL, BUS100, pm90_n765a),
 	ENTRY(INTEL, BUS100, pm90_n765b),
 	ENTRY(INTEL, BUS100, pm90_n765c),
 	ENTRY(INTEL, BUS100, pm90_n765e),
 	ENTRY(INTEL, BUS133, pm90_n770),
 	ENTRY(INTEL, BUS133, pm90_n780),
 	ENTRY(IDT, BUS100, C7M_770_ULV),
 	ENTRY(IDT, BUS100, C7M_779_ULV),
 	ENTRY(IDT, BUS100, C7M_772_ULV),
 	ENTRY(IDT, BUS100, C7M_771),
 	ENTRY(IDT, BUS100, C7M_775_ULV),
 	ENTRY(IDT, BUS100, C7M_754),
 	ENTRY(IDT, BUS100, C7M_764),
 	ENTRY(IDT, BUS133, C7M_765),
 	ENTRY(IDT, BUS100, C7M_784),
 	ENTRY(IDT, BUS133, C7M_785),
 	ENTRY(IDT, BUS100, C7M_794),
 	ENTRY(IDT, BUS133, C7M_795),
 	ENTRY(IDT, BUS100, eden90_1000)
 };
 #define MSR2FREQINC(msr)	(((int) (msr) >> 8) & 0xff)
 #define MSR2VOLTINC(msr)	((int) (msr) & 0xff)
 #define MSR2MHZ(msr, bus)	((MSR2FREQINC((msr)) * (bus) + 50) / 100)
 #define MSR2MV(msr)		(MSR2VOLTINC(msr) * 16 + 700)
 static const struct 	fqlist *est_fqlist;	/* not NULL if functional */
 static uint16_t		*fake_table;		/* guessed est_cpu table */
 static char		*freq_names;
 static struct fqlist    fake_fqlist;
 static int 		est_node_target, est_node_current;
 static const char 	est_desc[] = "Enhanced SpeedStep";
 static int		lvendor, bus_clock;
 static int		est_init_once(void);
 static void		est_init_main(int);
 static int		est_sysctl_helper(SYSCTLFN_PROTO);
 static int		est_sysctl_helper_get(SYSCTLFN_PROTO);
 static int		est_sysctl_helper_set(SYSCTLFN_PROTO);
 static int		est_sysctl_helper_all(SYSCTLFN_PROTO);
 int (*est_sysctl_get)(SYSCTLFN_PROTO) = NULL;
 int (*est_sysctl_set)(SYSCTLFN_PROTO) = NULL;
 int (*est_sysctl_all)(SYSCTLFN_PROTO) = NULL;
 static int
 est_sysctl_helper_get(SYSCTLFN_ARGS)
+{
-	if (est_sysctl_get != NULL)
+	if (cpu_freq_sysctl_get != NULL)
-		return (*est_sysctl_get)(SYSCTLFN_CALL(rnode));
+		return (*cpu_freq_sysctl_get)(SYSCTLFN_CALL(rnode));
 	return est_sysctl_helper(SYSCTLFN_CALL(rnode));
+}
 static int
 est_sysctl_helper_set(SYSCTLFN_ARGS)
+{
-	if (est_sysctl_set != NULL)
+	if (cpu_freq_sysctl_set != NULL)
-		return (*est_sysctl_set)(SYSCTLFN_CALL(rnode));
+		return (*cpu_freq_sysctl_set)(SYSCTLFN_CALL(rnode));
 	return est_sysctl_helper(SYSCTLFN_CALL(rnode));
+}
 static int
 est_sysctl_helper_all(SYSCTLFN_ARGS)
+{
 	struct sysctlnode node;
 	int err;
-	if (est_sysctl_all != NULL)
+	if (cpu_freq_sysctl_all != NULL)
-		return (*est_sysctl_all)(SYSCTLFN_CALL(rnode));
+		return (*cpu_freq_sysctl_all)(SYSCTLFN_CALL(rnode));
 	if (freq_names == NULL)
 		return ENXIO;
 	node = *rnode;
 	node.sysctl_data = freq_names;
 	err = sysctl_lookup(SYSCTLFN_CALL(&node));
 	if (err != 0 || newp == NULL)
 		return err;
 	return 0;
+}
 static int
 est_sysctl_helper(SYSCTLFN_ARGS)
+{
 	struct sysctlnode	node;
 	int			fq, oldfq, error;
 	if (freq_names == NULL)
 		return ENXIO;
 	if (est_fqlist == NULL)
 		return EOPNOTSUPP;
 	node = *rnode;
 	node.sysctl_data = &fq;
 	oldfq = 0;
 	if (rnode->sysctl_num == est_node_target)
 		fq = oldfq = MSR2MHZ(rdmsr(MSR_PERF_CTL), bus_clock);
 	else if (rnode->sysctl_num == est_node_current)
 		fq = MSR2MHZ(rdmsr(MSR_PERF_STATUS), bus_clock);
 	else
 		return EOPNOTSUPP;
 	error = sysctl_lookup(SYSCTLFN_CALL(&node));
 	if (error || newp == NULL)
 		return error;
 	/* support writing to ...frequency.target */
 	if (rnode->sysctl_num == est_node_target && fq != oldfq) {
 		struct msr_rw_info msr;
 		uint64_t where;
 		int i;
 		for (i = est_fqlist->n - 1; i > 0; i--)
 			if (MSR2MHZ(est_fqlist->table[i], bus_clock) >= fq)
 				break;
 		fq = MSR2MHZ(est_fqlist->table[i], bus_clock);
 		msr.msr_read = true;
 		msr.msr_type = MSR_PERF_CTL;
 		msr.msr_mask = 0xffffULL;
 		msr.msr_value = est_fqlist->table[i];
 		where = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL);
 		xc_wait(where);
+	}
 	return 0;
+}
 static int
 est_init_once(void)
+{
 	est_init_main(lvendor);
 	return 0;
+}
 void
 est_init(int vendor)
+{
 	int error;
 	static ONCE_DECL(est_initialized);
 	lvendor = vendor;
 	error = RUN_ONCE(&est_initialized, est_init_once);
 	if (__predict_false(error != 0))
 		return;
+}
 static void
 est_init_main(int vendor)
+{
 #ifdef __i386__
 	const struct fqlist	*fql;
 #endif
 	const struct sysctlnode	*node, *estnode, *freqnode;
 	uint64_t		msr;
 	uint16_t		cur, idhi, idlo;
 	uint8_t			crhi, crlo, crcur;
 	int			i, mv, rc;
 	size_t			len, freq_len;
 	if (CPUID2FAMILY(curcpu()->ci_signature) == 15)
 		bus_clock = p4_get_bus_clock(curcpu());
 	else if (CPUID2FAMILY(curcpu()->ci_signature) == 6) {
 		if (vendor == CPUVENDOR_IDT) {
 			switch (CPUID2MODEL(curcpu()->ci_signature)) {
 			case 0xa: /* C7 Esther */
 			case 0xd: /* C7 Esther */
 				bus_clock = viac7_get_bus_clock(curcpu());
 				break;
 			default:
 				bus_clock = via_get_bus_clock(curcpu());
 				break;
+			}
 		} else
 			bus_clock = p3_get_bus_clock(curcpu());
+	}
 	if (bus_clock == 0) {
 		aprint_debug("%s: unknown system bus clock\n", __func__);
 		return;
+	}
 	msr = rdmsr(MSR_PERF_STATUS);
 	idhi = (msr >> 32) & 0xffff;
 	idlo = (msr >> 48) & 0xffff;
 	cur = msr & 0xffff;
 	crhi = (idhi  >> 8) & 0xff;
 	crlo = (idlo  >> 8) & 0xff;
 	crcur = (cur >> 8) & 0xff;
 #ifdef __i386__
 	if (idhi == 0 || idlo == 0 || cur == 0 ||
 	    ((cur >> 8) & 0xff) < ((idlo >> 8) & 0xff) ||
 	    ((cur >> 8) & 0xff) > ((idhi >> 8) & 0xff)) {
 		aprint_debug("%s: strange msr value 0x%016llx\n",
 		    __func__, msr);
 		return;
+	}
 #endif
 #ifdef __amd64__
 	if (crlo == 0 || crhi == 0 || crcur == 0 || crhi == crlo ||
 	    crlo > crhi || crcur < crlo || crcur > crhi) {
 		/*
 		 * Do complain about other weirdness, because we first want to
 		 * know about it, before we decide what to do with it
 		 */
 		aprint_debug("%s: strange msr value 0x%" PRIu64 "\n",
 		    __func__, msr);
 		aprint_debug("%s: crhi=%" PRIu8 ", crlo=%" PRIu8 ", crcur=%"
 		    PRIu8 "\n", __func__, crhi, crlo, crcur);
 		return;
+	}
 #endif
 	msr = rdmsr(MSR_PERF_STATUS);
 	mv = MSR2MV(msr);
 #ifdef __i386__
 	/*
 	 * Find an entry which matches (vendor, bus_clock, idhi, idlo)
 	 */
 	est_fqlist = NULL;
 	for (i = 0; i < __arraycount(est_cpus); i++) {
 		fql = &est_cpus[i];
 		if (vendor == fql->vendor && bus_clock == BUS_CLK(fql) &&
 		    idhi == fql->table[0] && idlo == fql->table[fql->n - 1]) {
 			est_fqlist = fql;
 			break;
+		}
+	}
 #endif
 	if (est_fqlist == NULL) {
 		int j, tablesize, freq, volt;
 		int minfreq, minvolt, maxfreq, maxvolt, freqinc, voltinc;
 		/*
 		 * Some CPUs report the same frequency in idhi and idlo,
 		 * so do not run est on them.
 		 */
 		if (idhi == idlo) {
 			aprint_debug("%s: idhi == idlo\n", __func__);
 			return;
+		}
 #ifdef EST_DEBUG
 		printf("%s: bus_clock = %d\n", __func__, bus_clock);
 		printf("%s: idlo = 0x%x\n", __func__, idlo);
 		printf("%s: lo  %4d mV, %4d MHz\n", __func__,
 		    MSR2MV(idlo), MSR2MHZ(idlo, bus_clock));
 		printf("%s: raw %4d   , %4d    \n", __func__,
 		    (idlo & 0xff), ((idlo >> 8) & 0xff));
 		printf("%s: idhi = 0x%x\n", __func__, idhi);
 		printf("%s: hi  %4d mV, %4d MHz\n", __func__,
 		    MSR2MV(idhi), MSR2MHZ(idhi, bus_clock));
 		printf("%s: raw %4d   , %4d    \n", __func__,
 		    (idhi & 0xff), ((idhi >> 8) & 0xff));
 		printf("%s: cur  = 0x%x\n", __func__, cur);
 #endif
                 /*
                  * Generate a fake table with the power states we know,
 		 * interpolating the voltages and frequencies between the
 		 * high and low values.  The (milli)voltages are always
 		 * rounded up when computing the table.
                  */
 		minfreq = MSR2FREQINC(idlo);
 		maxfreq = MSR2FREQINC(idhi);
 		minvolt = MSR2VOLTINC(idlo);
 		maxvolt = MSR2VOLTINC(idhi);
 		freqinc = maxfreq - minfreq;
 		voltinc = maxvolt - minvolt;
 		/* Avoid diving by zero. */
 		if (freqinc == 0)
 			return;
 		if (freqinc < voltinc || voltinc == 0) {
 			tablesize = maxfreq - minfreq + 1;
 			if (voltinc != 0)
 				voltinc = voltinc * 100 / freqinc - 1;
 			freqinc = 100;
 		} else {
 			tablesize = maxvolt - minvolt + 1;
 			freqinc = freqinc * 100 / voltinc - 1;
 			voltinc = 100;
+		}
 		fake_table = malloc(tablesize * sizeof(uint16_t), M_DEVBUF,
 		    M_WAITOK);
 		fake_fqlist.n = tablesize;
 		/* The frequency/voltage table is highest frequency first */
 		freq = maxfreq * 100;
 		volt = maxvolt * 100;
 		for (j = 0; j < tablesize; j++) {
 			fake_table[j] = (((freq + 99) / 100) << 8) +
 			    (volt + 99) / 100;
 #ifdef EST_DEBUG
 			printf("%s: fake entry %d: %4d mV, %4d MHz  "
 			    "MSR*100 mV = %4d freq = %4d\n",
 			    __func__, j, MSR2MV(fake_table[j]),
 			    MSR2MHZ(fake_table[j], bus_clock),
 			    volt, freq);
 #endif /* EST_DEBUG */
 			freq -= freqinc;
 			volt -= voltinc;
+		}
 		fake_fqlist.vendor = vendor;
 		fake_fqlist.table = fake_table;
 		est_fqlist = &fake_fqlist;
+	}
 	/*
 	 * OK, tell the user the available frequencies.
 	 */
 	freq_len = est_fqlist->n * (sizeof("9999 ")-1) + 1;
 	freq_names = malloc(freq_len, M_SYSCTLDATA, M_WAITOK);
 	freq_names[0] = '\0';
 	len = 0;
 	for (i = 0; i < est_fqlist->n; i++) {
 		len += snprintf(freq_names + len, freq_len - len, "%d%s",
 		    MSR2MHZ(est_fqlist->table[i], bus_clock),
 		    i < est_fqlist->n - 1 ? " " : "");
+	}
 	aprint_debug_dev(curcpu()->ci_dev, "%s (%d mV) ", est_desc, mv);
 	aprint_debug("%d (MHz): %s\n", MSR2MHZ(msr, bus_clock), freq_names);
 	/*
 	 * Setup the sysctl sub-tree machdep.est.*
 	 */
 	if ((rc = sysctl_createv(NULL, 0, NULL, &node,
 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL,
 	    NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0)
 		goto err;
 	if ((rc = sysctl_createv(NULL, 0, &node, &estnode,
 , CTLTYPE_NODE, "est", NULL,
 	    NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	if ((rc = sysctl_createv(NULL, 0, &estnode, &freqnode,
 , CTLTYPE_NODE, "frequency", NULL,
 	    NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	if ((rc = sysctl_createv(NULL, 0, &freqnode, &node,
 	    EST_TARGET_CTLFLAG, CTLTYPE_INT, "target", NULL,
 	    est_sysctl_helper_set, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	est_node_target = node->sysctl_num;
 	if ((rc = sysctl_createv(NULL, 0, &freqnode, &node,
 , CTLTYPE_INT, "current", NULL,
 	    est_sysctl_helper_get, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	est_node_current = node->sysctl_num;
 	if ((rc = sysctl_createv(NULL, 0, &freqnode, &node,
 	    CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL,
 	    est_sysctl_helper_all, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	return;
  err:
 	free(freq_names, M_SYSCTLDATA);
 	freq_names = NULL;
 	aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
+}