Mon Aug 9 10:57:23 2010 UTC ()
Group hyphens differently.


(wiz)
diff -r1.3 -r1.4 src/share/man/man4/acpicpu.4
cvs diff -r1.3 -r1.4 src/share/man/man4/acpicpu.4 (switch to unified diff)

--- src/share/man/man4/acpicpu.4 2010/08/09 06:40:33 1.3
+++ src/share/man/man4/acpicpu.4 2010/08/09 10:57:23 1.4
@@ -1,247 +1,247 @@ @@ -1,247 +1,247 @@
1.\" $NetBSD: acpicpu.4,v 1.3 2010/08/09 06:40:33 jruoho Exp $ 1.\" $NetBSD: acpicpu.4,v 1.4 2010/08/09 10:57:23 wiz Exp $
2.\" 2.\"
3.\" Coyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi> 3.\" Coyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi>
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27.Dd August 9, 2010 27.Dd August 9, 2010
28.Dt ACPICPU 4 28.Dt ACPICPU 4
29.Os 29.Os
30.Sh NAME 30.Sh NAME
31.Nm acpicpu 31.Nm acpicpu
32.Nd ACPI CPU 32.Nd ACPI CPU
33.Sh SYNOPSIS 33.Sh SYNOPSIS
34.Cd "acpicpu* at acpi?" 34.Cd "acpicpu* at acpi?"
35.Sh DESCRIPTION 35.Sh DESCRIPTION
36The 36The
37.Nm 37.Nm
38device driver supports certain processor features that are 38device driver supports certain processor features that are
39either only available via 39either only available via
40.Tn ACPI 40.Tn ACPI
41or that require 41or that require
42.Tn ACPI 42.Tn ACPI
43to function properly. 43to function properly.
44Typically the 44Typically the
45.Tn ACPI 45.Tn ACPI
46processor functionality is grouped into so-called C, P, and T -states. 46processor functionality is grouped into so-called C-, P-, and T-states.
47Presently, 47Presently,
48.Nm 48.Nm
49supports C and P -states. 49supports C- and P-states.
50.Ss C-states 50.Ss C-states
51The processor power states, or C-states, 51The processor power states, or C-states,
52are low-power modes that can be used when the 52are low-power modes that can be used when the
53.Tn CPU 53.Tn CPU
54is idle. 54is idle.
55The idea is not new: already in the 55The idea is not new: already in the
56.Tn 80486 56.Tn 80486
57processor a specific instruction 57processor a specific instruction
58.Pq Tn HLT 58.Pq Tn HLT
59was used for this purpose. 59was used for this purpose.
60This was later accompanied by a pair of other instructions 60This was later accompanied by a pair of other instructions
61.Pq Tn MONITOR , MWAIT . 61.Pq Tn MONITOR , MWAIT .
62By default, 62By default,
63.Nx 63.Nx
64may use either one; see the 64may use either one; see the
65.Ic machdep.idle-mechanism 65.Ic machdep.idle-mechanism
66.Xr sysctl 8 66.Xr sysctl 8
67variable. 67variable.
68.Tn ACPI 68.Tn ACPI
69provides the latest amendment. 69provides the latest amendment.
70.Pp 70.Pp
71The following C-states are typically available. 71The following C-states are typically available.
72Additional processor or vendor specific 72Additional processor or vendor specific
73states (C4, ..., Cn) are handled internally by 73states (C4, ..., Cn) are handled internally by
74.Nm . 74.Nm .
75.Pp 75.Pp
76.Bl -tag -width C1 -offset indent 76.Bl -tag -width C1 -offset indent
77.It Dv C0 77.It Dv C0
78This is the normal state of a processor; the 78This is the normal state of a processor; the
79.Tn CPU 79.Tn CPU
80is busy executing instructions. 80is busy executing instructions.
81.It Dv C1 81.It Dv C1
82This is the state that is typically reached via the mentioned 82This is the state that is typically reached via the mentioned
83.Tn x86 83.Tn x86
84instructions. 84instructions.
85On a typical processor, 85On a typical processor,
86.Dv C1 86.Dv C1
87turns off the main internal 87turns off the main internal
88.Tn CPU 88.Tn CPU
89clock, leaving 89clock, leaving
90.Tn APIC 90.Tn APIC
91running at full speed. 91running at full speed.
92The 92The
93.Tn CPU 93.Tn CPU
94is free to temporarily leave the state to deal with important requests. 94is free to temporarily leave the state to deal with important requests.
95.It Dv C2 95.It Dv C2
96The main difference between 96The main difference between
97.Dv C1 97.Dv C1
98and 98and
99.Dv C2 99.Dv C2
100lies in the internal hardware entry method of the processor. 100lies in the internal hardware entry method of the processor.
101While less power is expected to be consumed than in 101While less power is expected to be consumed than in
102.Dv C1 , 102.Dv C1 ,
103the bus interface unit is still running. 103the bus interface unit is still running.
104But depending on the processor, the local 104But depending on the processor, the local
105.Tn APIC 105.Tn APIC
106timer may be stopped. 106timer may be stopped.
107Like with 107Like with
108.Dv C1 , 108.Dv C1 ,
109entering and exiting the state are expected to be fast operations. 109entering and exiting the state are expected to be fast operations.
110.It Dv C3 110.It Dv C3
111This is the deepest conventional state. 111This is the deepest conventional state.
112Parts of the 112Parts of the
113.Tn CPU 113.Tn CPU
114are actively powered down. 114are actively powered down.
115The internal 115The internal
116.Tn CPU 116.Tn CPU
117clock is stopped. 117clock is stopped.
118The local 118The local
119.Tn APIC 119.Tn APIC
120timer is stopped. 120timer is stopped.
121Depending on the processor, additional timers such as 121Depending on the processor, additional timers such as
122.Tn TSC 122.Tn TSC
123.Pq time stamp counter 123.Pq time stamp counter
124may be stopped. 124may be stopped.
125Entry and exit latencies are expected to be high; the 125Entry and exit latencies are expected to be high; the
126.Tn CPU 126.Tn CPU
127can no longer 127can no longer
128.Dq quickly 128.Dq quickly
129respond to bus activity or other interruptions. 129respond to bus activity or other interruptions.
130.El 130.El
131.Pp 131.Pp
132Each state has a latency associated with entry and exit. 132Each state has a latency associated with entry and exit.
133The higher the state, the lower the power consumption, and 133The higher the state, the lower the power consumption, and
134the higher the potential performance costs. 134the higher the potential performance costs.
135.Pp 135.Pp
136The 136The
137.Nm 137.Nm
138driver tries to balance the latency 138driver tries to balance the latency
139constraints when choosing the appropriate state. 139constraints when choosing the appropriate state.
140One of the checks involves bus master activity; 140One of the checks involves bus master activity;
141if such activity is detected, a lower state is used. 141if such activity is detected, a lower state is used.
142It is known that particularly 142It is known that particularly
143.Xr usb 4 143.Xr usb 4
144may cause high activity even when not in use. 144may cause high activity even when not in use.
145If maximum power savings are desirable, 145If maximum power savings are desirable,
146it may be necessary to use a custom kernel without 146it may be necessary to use a custom kernel without
147.Tn USB 147.Tn USB
148support. 148support.
149And generally: to save power with C-states, one should 149And generally: to save power with C-states, one should
150avoid polling, both in userland and in the kernel. 150avoid polling, both in userland and in the kernel.
151.Ss P-states 151.Ss P-states
152The processor performance states, or P-states, are used to 152The processor performance states, or P-states, are used to
153control the clock frequencies and voltages of a 153control the clock frequencies and voltages of a
154.Tn CPU . 154.Tn CPU .
155Underneath the abstractions of 155Underneath the abstractions of
156.Tn ACPI , 156.Tn ACPI ,
157P-states are associated with such technologies as 157P-states are associated with such technologies as
158.Dq SpeedStep 158.Dq SpeedStep
159.Pq Intel , 159.Pq Intel ,
160.Dq PowerNow! 160.Dq PowerNow!
161.Pq Tn AMD , 161.Pq Tn AMD ,
162and 162and
163.Dq PowerSaver 163.Dq PowerSaver
164.Pq VIA . 164.Pq VIA .
165.Pp 165.Pp
166The 166The
167.Dv P0 167.Dv P0
168state is always the highest operating frequency sypported by the processor. 168state is always the highest operating frequency sypported by the processor.
169The number of additional P-states may vary across processors and vendors. 169The number of additional P-states may vary across processors and vendors.
170Each higher numbered P-state represents lower 170Each higher numbered P-state represents lower
171clock frequencies and hence lower power consumption. 171clock frequencies and hence lower power consumption.
172.Pp 172.Pp
173Unlike conventional 173Unlike conventional
174.Tn CPU 174.Tn CPU
175frequency management, 175frequency management,
176.Tn ACPI 176.Tn ACPI
177provides support for Dynamic Frequency and Voltage Scaling 177provides support for Dynamic Frequency and Voltage Scaling
178.Pq Tn DVFS . 178.Pq Tn DVFS .
179This means that the firmware may request the implementation to 179This means that the firmware may request the implementation to
180dynamically scale the presently supported maximum clock frequency. 180dynamically scale the presently supported maximum clock frequency.
181For example, if 181For example, if
182.Xr acpiacad 4 182.Xr acpiacad 4
183is disconnected, the maximum available frequency may be lowered. 183is disconnected, the maximum available frequency may be lowered.
184Currently the 184Currently the
185.Nx 185.Nx
186implementation reacts to these events by imposing the dynamic maximum, but 186implementation reacts to these events by imposing the dynamic maximum, but
187.Nm 187.Nm
188does not take any actions to manipulate the frequencies by itself. 188does not take any actions to manipulate the frequencies by itself.
189.Sh SEE ALSO 189.Sh SEE ALSO
190.Xr acpi 4 , 190.Xr acpi 4 ,
191.Xr cpu_idle 9 191.Xr cpu_idle 9
192.Sh HISTORY 192.Sh HISTORY
193The 193The
194.Nm 194.Nm
195device driver appeared in 195device driver appeared in
196.Nx 6.0 . 196.Nx 6.0 .
197.Sh AUTHORS 197.Sh AUTHORS
198.An Jukka Ruohonen 198.An Jukka Ruohonen
199.Aq jruohonen@iki.fi 199.Aq jruohonen@iki.fi
200.Sh CAVEATS 200.Sh CAVEATS
201The 201The
202.Nm 202.Nm
203driver should be considered experimental. 203driver should be considered experimental.
204At least the following caveats can be mentioned. 204At least the following caveats can be mentioned.
205.Bl -bullet 205.Bl -bullet
206.It 206.It
207It is currently only safe to use 207It is currently only safe to use
208.Dv C1 208.Dv C1
209on 209on
210.Nx . 210.Nx .
211All other C-states are disabled by default. 211All other C-states are disabled by default.
212.It 212.It
213The 213The
214.Tn AMD 214.Tn AMD
215.Tn C1E 215.Tn C1E
216extension is not supported. 216extension is not supported.
217If this extension is available in a vendor 217If this extension is available in a vendor
218.Tn BIOS , 218.Tn BIOS ,
219it is recommended to turn it off, with or without 219it is recommended to turn it off, with or without
220.Nm . 220.Nm .
221.It 221.It
222The use of native instructions in P-states 222The use of native instructions in P-states
223is currently supported only on Intel 223is currently supported only on Intel
224.Tn CPUs . 224.Tn CPUs .
225.It 225.It
226Neither processor thermal control (see 226Neither processor thermal control (see
227.Xr acpitz 4 ) 227.Xr acpitz 4 )
228nor 228nor
229.Dq throttling 229.Dq throttling
230are currently supported. 230are currently supported.
231.It 231.It
232There is currently neither a well-defined, machine-independent 232There is currently neither a well-defined, machine-independent
233.Tn API 233.Tn API
234for processor performance management nor a 234for processor performance management nor a
235.Dq governor 235.Dq governor
236for different policies. 236for different policies.
237It is only possible to control the 237It is only possible to control the
238.Tn CPU 238.Tn CPU
239frequencies from userland. 239frequencies from userland.
240.It 240.It
241There are currently no proper ways to export 241There are currently no proper ways to export
242statistical and other information from 242statistical and other information from
243.Nm . 243.Nm .
244This applies to 244This applies to
245.Tn ACPI 245.Tn ACPI
246generally. 246generally.
247.El 247.El