| @@ -4443,48 +4443,64 @@ static void RADEONSaveMemMapRegisters(Sc | | | @@ -4443,48 +4443,64 @@ static void RADEONSaveMemMapRegisters(Sc |
4443 | RADEONInfoPtr info = RADEONPTR(pScrn); | | 4443 | RADEONInfoPtr info = RADEONPTR(pScrn); |
4444 | unsigned char *RADEONMMIO = info->MMIO; | | 4444 | unsigned char *RADEONMMIO = info->MMIO; |
4445 | | | 4445 | |
4446 | radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location, | | 4446 | radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location, |
4447 | &save->mc_agp_location, &save->mc_agp_location_hi); | | 4447 | &save->mc_agp_location, &save->mc_agp_location_hi); |
4448 | | | 4448 | |
4449 | if (!IS_AVIVO_VARIANT) { | | 4449 | if (!IS_AVIVO_VARIANT) { |
4450 | save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); | | 4450 | save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); |
4451 | save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); | | 4451 | save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); |
4452 | save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); | | 4452 | save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); |
4453 | } | | 4453 | } |
4454 | } | | 4454 | } |
4455 | | | 4455 | |
4456 | | | | |
4457 | #if 0 | | | |
4458 | /* Read palette data */ | | 4456 | /* Read palette data */ |
4459 | static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) | | 4457 | static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) |
4460 | { | | 4458 | { |
4461 | RADEONInfoPtr info = RADEONPTR(pScrn); | | 4459 | RADEONInfoPtr info = RADEONPTR(pScrn); |
4462 | unsigned char *RADEONMMIO = info->MMIO; | | 4460 | unsigned char *RADEONMMIO = info->MMIO; |
4463 | int i; | | 4461 | int i; |
4464 | | | 4462 | |
4465 | #ifdef ENABLE_FLAT_PANEL | | | |
4466 | /* Select palette 0 (main CRTC) if using FP-enabled chip */ | | | |
4467 | /* if (info->Port1 == MT_DFP) PAL_SELECT(1); */ | | | |
4468 | #endif | | | |
4469 | PAL_SELECT(1); | | 4463 | PAL_SELECT(1); |
4470 | INPAL_START(0); | | 4464 | INPAL_START(0); |
4471 | for (i = 0; i < 256; i++) save->palette2[i] = INPAL_NEXT(); | | 4465 | for (i = 0; i < 256; i++) { |
| | | 4466 | save->palette2[i] = INREG(RADEON_PALETTE_30_DATA); |
| | | 4467 | } |
| | | 4468 | |
4472 | PAL_SELECT(0); | | 4469 | PAL_SELECT(0); |
4473 | INPAL_START(0); | | 4470 | INPAL_START(0); |
4474 | for (i = 0; i < 256; i++) save->palette[i] = INPAL_NEXT(); | | 4471 | for (i = 0; i < 256; i++) { |
4475 | save->palette_valid = TRUE; | | 4472 | save->palette[i] = INREG(RADEON_PALETTE_30_DATA); |
| | | 4473 | } |
| | | 4474 | } |
| | | 4475 | |
| | | 4476 | static void RADEONRestorePalette(ScrnInfoPtr pScrn, RADEONSavePtr restore) |
| | | 4477 | { |
| | | 4478 | RADEONInfoPtr info = RADEONPTR(pScrn); |
| | | 4479 | unsigned char *RADEONMMIO = info->MMIO; |
| | | 4480 | int i; |
| | | 4481 | |
| | | 4482 | PAL_SELECT(1); |
| | | 4483 | OUTPAL_START(0); |
| | | 4484 | for (i = 0; i < 256; i++) { |
| | | 4485 | OUTREG(RADEON_PALETTE_30_DATA, restore->palette2[i]); |
| | | 4486 | } |
| | | 4487 | |
| | | 4488 | PAL_SELECT(0); |
| | | 4489 | OUTPAL_START(0); |
| | | 4490 | for (i = 0; i < 256; i++) { |
| | | 4491 | OUTREG(RADEON_PALETTE_30_DATA, restore->palette[i]); |
| | | 4492 | } |
4476 | } | | 4493 | } |
4477 | #endif | | | |
4478 | | | 4494 | |
4479 | static void | | 4495 | static void |
4480 | avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) | | 4496 | avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) |
4481 | { | | 4497 | { |
4482 | RADEONInfoPtr info = RADEONPTR(pScrn); | | 4498 | RADEONInfoPtr info = RADEONPTR(pScrn); |
4483 | unsigned char *RADEONMMIO = info->MMIO; | | 4499 | unsigned char *RADEONMMIO = info->MMIO; |
4484 | struct avivo_state *state = &save->avivo; | | 4500 | struct avivo_state *state = &save->avivo; |
4485 | int i, j; | | 4501 | int i, j; |
4486 | | | 4502 | |
4487 | // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); | | 4503 | // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); |
4488 | // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); | | 4504 | // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); |
4489 | state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); | | 4505 | state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); |
4490 | state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL); | | 4506 | state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL); |
| @@ -5337,26 +5353,28 @@ static void RADEONSave(ScrnInfoPtr pScrn | | | @@ -5337,26 +5353,28 @@ static void RADEONSave(ScrnInfoPtr pScrn |
5337 | avivo_save(pScrn, save); | | 5353 | avivo_save(pScrn, save); |
5338 | } else { | | 5354 | } else { |
5339 | save->dp_datatype = INREG(RADEON_DP_DATATYPE); | | 5355 | save->dp_datatype = INREG(RADEON_DP_DATATYPE); |
5340 | save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); | | 5356 | save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); |
5341 | save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); | | 5357 | save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); |
5342 | RADEONPllErrataAfterIndex(info); | | 5358 | RADEONPllErrataAfterIndex(info); |
5343 | | | 5359 | |
5344 | RADEONSaveMemMapRegisters(pScrn, save); | | 5360 | RADEONSaveMemMapRegisters(pScrn, save); |
5345 | RADEONSaveCommonRegisters(pScrn, save); | | 5361 | RADEONSaveCommonRegisters(pScrn, save); |
5346 | RADEONSavePLLRegisters(pScrn, save); | | 5362 | RADEONSavePLLRegisters(pScrn, save); |
5347 | RADEONSaveCrtcRegisters(pScrn, save); | | 5363 | RADEONSaveCrtcRegisters(pScrn, save); |
5348 | RADEONSaveFPRegisters(pScrn, save); | | 5364 | RADEONSaveFPRegisters(pScrn, save); |
5349 | RADEONSaveDACRegisters(pScrn, save); | | 5365 | RADEONSaveDACRegisters(pScrn, save); |
| | | 5366 | RADEONSavePalette(pScrn, save); |
| | | 5367 | |
5350 | if (pRADEONEnt->HasCRTC2) { | | 5368 | if (pRADEONEnt->HasCRTC2) { |
5351 | RADEONSaveCrtc2Registers(pScrn, save); | | 5369 | RADEONSaveCrtc2Registers(pScrn, save); |
5352 | RADEONSavePLL2Registers(pScrn, save); | | 5370 | RADEONSavePLL2Registers(pScrn, save); |
5353 | } | | 5371 | } |
5354 | if (info->InternalTVOut) | | 5372 | if (info->InternalTVOut) |
5355 | RADEONSaveTVRegisters(pScrn, save); | | 5373 | RADEONSaveTVRegisters(pScrn, save); |
5356 | } | | 5374 | } |
5357 | | | 5375 | |
5358 | if (info->ChipFamily < CHIP_FAMILY_R600) | | 5376 | if (info->ChipFamily < CHIP_FAMILY_R600) |
5359 | RADEONSaveSurfaces(pScrn, save); | | 5377 | RADEONSaveSurfaces(pScrn, save); |
5360 | | | 5378 | |
5361 | } | | 5379 | } |
5362 | | | 5380 | |
| @@ -5458,44 +5476,35 @@ static void RADEONRestore(ScrnInfoPtr pS | | | @@ -5458,44 +5476,35 @@ static void RADEONRestore(ScrnInfoPtr pS |
5458 | # else | | 5476 | # else |
5459 | vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL ); | | 5477 | vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL ); |
5460 | # endif | | 5478 | # endif |
5461 | vgaHWLock(hwp); | | 5479 | vgaHWLock(hwp); |
5462 | } | | 5480 | } |
5463 | #endif | | 5481 | #endif |
5464 | | | 5482 | |
5465 | /* to restore console mode, DAC registers should be set after every other registers are set, | | 5483 | /* to restore console mode, DAC registers should be set after every other registers are set, |
5466 | * otherwise,we may get blank screen | | 5484 | * otherwise,we may get blank screen |
5467 | */ | | 5485 | */ |
5468 | if (IS_AVIVO_VARIANT) | | 5486 | if (IS_AVIVO_VARIANT) |
5469 | avivo_restore_vga_regs(pScrn, restore); | | 5487 | avivo_restore_vga_regs(pScrn, restore); |
5470 | | | 5488 | |
5471 | if (!IS_AVIVO_VARIANT) | | 5489 | if (!IS_AVIVO_VARIANT) { |
| | | 5490 | RADEONRestorePalette(pScrn, restore); |
5472 | RADEONRestoreDACRegisters(pScrn, restore); | | 5491 | RADEONRestoreDACRegisters(pScrn, restore); |
5473 | | | 5492 | } |
5474 | #if 0 | | 5493 | #if 0 |
5475 | RADEONWaitForVerticalSync(pScrn); | | 5494 | RADEONWaitForVerticalSync(pScrn); |
5476 | #endif | | 5495 | #endif |
5477 | } | | 5496 | } |
5478 | | | 5497 | |
5479 | #if 0 | | | |
5480 | /* Define initial palette for requested video mode. This doesn't do | | | |
5481 | * anything for XFree86 4.0. | | | |
5482 | */ | | | |
5483 | static void RADEONInitPalette(RADEONSavePtr save) | | | |
5484 | { | | | |
5485 | save->palette_valid = FALSE; | | | |
5486 | } | | | |
5487 | #endif | | | |
5488 | | | | |
5489 | static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode) | | 5498 | static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode) |
5490 | { | | 5499 | { |
5491 | ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; | | 5500 | ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; |
5492 | Bool unblank; | | 5501 | Bool unblank; |
5493 | | | 5502 | |
5494 | xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, | | 5503 | xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, |
5495 | "RADEONSaveScreen(%d)\n", mode); | | 5504 | "RADEONSaveScreen(%d)\n", mode); |
5496 | | | 5505 | |
5497 | unblank = xf86IsUnblank(mode); | | 5506 | unblank = xf86IsUnblank(mode); |
5498 | if (unblank) SetTimeSinceLastInputEvent(); | | 5507 | if (unblank) SetTimeSinceLastInputEvent(); |
5499 | | | 5508 | |
5500 | if ((pScrn != NULL) && pScrn->vtSema) { | | 5509 | if ((pScrn != NULL) && pScrn->vtSema) { |
5501 | if (unblank) | | 5510 | if (unblank) |