Sat Dec 11 18:09:34 2010 UTC ()
Regen.


(matt)
diff -r1.100 -r1.101 src/sys/dev/mii/miidevs.h
diff -r1.88 -r1.89 src/sys/dev/mii/miidevs_data.h
cvs diff -r1.100 -r1.101 src/sys/dev/mii/miidevs.h (expand / switch to unified diff)

--- src/sys/dev/mii/miidevs.h 2010/11/27 20:15:43 1.100
+++ src/sys/dev/mii/miidevs.h 2010/12/11 18:09:33 1.101
@@ -1,20 +1,20 @@ @@ -1,20 +1,20 @@
1/* $NetBSD: miidevs.h,v 1.100 2010/11/27 20:15:43 christos Exp $ */ 1/* $NetBSD: miidevs.h,v 1.101 2010/12/11 18:09:33 matt Exp $ */
2 2
3/* 3/*
4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
5 * 5 *
6 * generated from: 6 * generated from:
7 * NetBSD: miidevs,v 1.97 2010/11/27 20:15:27 christos Exp 7 * NetBSD: miidevs,v 1.98 2010/12/11 18:09:13 matt Exp
8 */ 8 */
9 9
10/*- 10/*-
11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
12 * All rights reserved. 12 * All rights reserved.
13 * 13 *
14 * This code is derived from software contributed to The NetBSD Foundation 14 * This code is derived from software contributed to The NetBSD Foundation
15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
16 * NASA Ames Research Center. 16 * NASA Ames Research Center.
17 * 17 *
18 * Redistribution and use in source and binary forms, with or without 18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions 19 * modification, are permitted provided that the following conditions
20 * are met: 20 * are met:
@@ -122,26 +122,28 @@ @@ -122,26 +122,28 @@
122#define MII_STR_AGERE_ET1011 "Agere ET1011 10/100/1000baseT PHY" 122#define MII_STR_AGERE_ET1011 "Agere ET1011 10/100/1000baseT PHY"
123 123
124/* Atheros PHYs */ 124/* Atheros PHYs */
125#define MII_MODEL_ATHEROS_F1 0x0001 125#define MII_MODEL_ATHEROS_F1 0x0001
126#define MII_STR_ATHEROS_F1 "F1 10/100/1000 PHY" 126#define MII_STR_ATHEROS_F1 "F1 10/100/1000 PHY"
127#define MII_MODEL_ATHEROS_F2 0x0002 127#define MII_MODEL_ATHEROS_F2 0x0002
128#define MII_STR_ATHEROS_F2 "F2 10/100 PHY" 128#define MII_STR_ATHEROS_F2 "F2 10/100 PHY"
129 129
130/* Attansic PHYs */ 130/* Attansic PHYs */
131#define MII_MODEL_ATTANSIC_L1 0x0001 131#define MII_MODEL_ATTANSIC_L1 0x0001
132#define MII_STR_ATTANSIC_L1 "L1 10/100/1000 PHY" 132#define MII_STR_ATTANSIC_L1 "L1 10/100/1000 PHY"
133#define MII_MODEL_ATTANSIC_L2 0x0002 133#define MII_MODEL_ATTANSIC_L2 0x0002
134#define MII_STR_ATTANSIC_L2 "L2 10/100 PHY" 134#define MII_STR_ATTANSIC_L2 "L2 10/100 PHY"
 135#define MII_MODEL_ATTANSIC_AR8021 0x0004
 136#define MII_STR_ATTANSIC_AR8021 "Atheros AR8021 10/100/1000 PHY"
135 137
136/* Altima Communications PHYs */ 138/* Altima Communications PHYs */
137/* Don't know the model for ACXXX */ 139/* Don't know the model for ACXXX */
138#define MII_MODEL_ALTIMA_ACXXX 0x0001 140#define MII_MODEL_ALTIMA_ACXXX 0x0001
139#define MII_STR_ALTIMA_ACXXX "ACXXX 10/100 media interface" 141#define MII_STR_ALTIMA_ACXXX "ACXXX 10/100 media interface"
140#define MII_MODEL_ALTIMA_AC101 0x0021 142#define MII_MODEL_ALTIMA_AC101 0x0021
141#define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface" 143#define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface"
142#define MII_MODEL_ALTIMA_AC101L 0x0012 144#define MII_MODEL_ALTIMA_AC101L 0x0012
143#define MII_STR_ALTIMA_AC101L "AC101L 10/100 media interface" 145#define MII_STR_ALTIMA_AC101L "AC101L 10/100 media interface"
144/* AMD Am79C87[45] have ALTIMA OUI */ 146/* AMD Am79C87[45] have ALTIMA OUI */
145#define MII_MODEL_ALTIMA_Am79C875 0x0014 147#define MII_MODEL_ALTIMA_Am79C875 0x0014
146#define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface" 148#define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface"
147#define MII_MODEL_ALTIMA_Am79C874 0x0021 149#define MII_MODEL_ALTIMA_Am79C874 0x0021
@@ -319,26 +321,28 @@ @@ -319,26 +321,28 @@
319/* Marvell Semiconductor PHYs */ 321/* Marvell Semiconductor PHYs */
320#define MII_MODEL_xxMARVELL_E1011 0x0002 322#define MII_MODEL_xxMARVELL_E1011 0x0002
321#define MII_STR_xxMARVELL_E1011 "Marvell 88E1011 Gigabit PHY" 323#define MII_STR_xxMARVELL_E1011 "Marvell 88E1011 Gigabit PHY"
322#define MII_MODEL_xxMARVELL_E1000_3 0x0003 324#define MII_MODEL_xxMARVELL_E1000_3 0x0003
323#define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" 325#define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
324#define MII_MODEL_xxMARVELL_E1000_5 0x0005 326#define MII_MODEL_xxMARVELL_E1000_5 0x0005
325#define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" 327#define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
326#define MII_MODEL_xxMARVELL_E6060 0x0008 328#define MII_MODEL_xxMARVELL_E6060 0x0008
327#define MII_STR_xxMARVELL_E6060 "Marvell 88E6060 10/100 5-port PHY switch" 329#define MII_STR_xxMARVELL_E6060 "Marvell 88E6060 10/100 5-port PHY switch"
328#define MII_MODEL_xxMARVELL_E1149 0x000b 330#define MII_MODEL_xxMARVELL_E1149 0x000b
329#define MII_STR_xxMARVELL_E1149 "Marvell 88E1149 Gigabit PHY" 331#define MII_STR_xxMARVELL_E1149 "Marvell 88E1149 Gigabit PHY"
330#define MII_MODEL_xxMARVELL_E1111 0x000c 332#define MII_MODEL_xxMARVELL_E1111 0x000c
331#define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY" 333#define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
 334#define MII_MODEL_xxMARVELL_E1145 0x000d
 335#define MII_STR_xxMARVELL_E1145 "Marvell 88E1145 Quad Gigabit PHY"
332#define MII_MODEL_xxMARVELL_E1116 0x0021 336#define MII_MODEL_xxMARVELL_E1116 0x0021
333#define MII_STR_xxMARVELL_E1116 "Marvell 88E1116 Gigabit PHY" 337#define MII_STR_xxMARVELL_E1116 "Marvell 88E1116 Gigabit PHY"
334#define MII_MODEL_xxMARVELL_E1116R 0x0024 338#define MII_MODEL_xxMARVELL_E1116R 0x0024
335#define MII_STR_xxMARVELL_E1116R "Marvell 88E1116R Gigabit PHY" 339#define MII_STR_xxMARVELL_E1116R "Marvell 88E1116R Gigabit PHY"
336 340
337/* Myson Technology PHYs */ 341/* Myson Technology PHYs */
338#define MII_MODEL_xxMYSON_MTD972 0x0000 342#define MII_MODEL_xxMYSON_MTD972 0x0000
339#define MII_STR_xxMYSON_MTD972 "MTD972 10/100 media interface" 343#define MII_STR_xxMYSON_MTD972 "MTD972 10/100 media interface"
340#define MII_MODEL_MYSON_MTD803 0x0000 344#define MII_MODEL_MYSON_MTD803 0x0000
341#define MII_STR_MYSON_MTD803 "MTD803 3-in-1 media interface" 345#define MII_STR_MYSON_MTD803 "MTD803 3-in-1 media interface"
342 346
343/* National Semiconductor PHYs */ 347/* National Semiconductor PHYs */
344#define MII_MODEL_xxNATSEMI_DP83840 0x0000 348#define MII_MODEL_xxNATSEMI_DP83840 0x0000
cvs diff -r1.88 -r1.89 src/sys/dev/mii/miidevs_data.h (expand / switch to unified diff)

--- src/sys/dev/mii/miidevs_data.h 2010/11/27 20:15:43 1.88
+++ src/sys/dev/mii/miidevs_data.h 2010/12/11 18:09:33 1.89
@@ -1,20 +1,20 @@ @@ -1,20 +1,20 @@
1/* $NetBSD: miidevs_data.h,v 1.88 2010/11/27 20:15:43 christos Exp $ */ 1/* $NetBSD: miidevs_data.h,v 1.89 2010/12/11 18:09:33 matt Exp $ */
2 2
3/* 3/*
4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
5 * 5 *
6 * generated from: 6 * generated from:
7 * NetBSD: miidevs,v 1.97 2010/11/27 20:15:27 christos Exp 7 * NetBSD: miidevs,v 1.98 2010/12/11 18:09:13 matt Exp
8 */ 8 */
9 9
10/*- 10/*-
11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
12 * All rights reserved. 12 * All rights reserved.
13 * 13 *
14 * This code is derived from software contributed to The NetBSD Foundation 14 * This code is derived from software contributed to The NetBSD Foundation
15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
16 * NASA Ames Research Center. 16 * NASA Ames Research Center.
17 * 17 *
18 * Redistribution and use in source and binary forms, with or without 18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions 19 * modification, are permitted provided that the following conditions
20 * are met: 20 * are met:
@@ -32,26 +32,27 @@ @@ -32,26 +32,27 @@
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE. 37 * POSSIBILITY OF SUCH DAMAGE.
38 */ 38 */
39struct mii_knowndev mii_knowndevs[] = { 39struct mii_knowndev mii_knowndevs[] = {
40 { MII_OUI_AGERE, MII_MODEL_AGERE_ET1011, MII_STR_AGERE_ET1011 }, 40 { MII_OUI_AGERE, MII_MODEL_AGERE_ET1011, MII_STR_AGERE_ET1011 },
41 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, MII_STR_ATHEROS_F1 }, 41 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, MII_STR_ATHEROS_F1 },
42 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F2, MII_STR_ATHEROS_F2 }, 42 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F2, MII_STR_ATHEROS_F2 },
43 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, MII_STR_ATTANSIC_L1 }, 43 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, MII_STR_ATTANSIC_L1 },
44 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2, MII_STR_ATTANSIC_L2 }, 44 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2, MII_STR_ATTANSIC_L2 },
 45 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8021, MII_STR_ATTANSIC_AR8021 },
45 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_ACXXX, MII_STR_ALTIMA_ACXXX }, 46 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_ACXXX, MII_STR_ALTIMA_ACXXX },
46 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101, MII_STR_ALTIMA_AC101 }, 47 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101, MII_STR_ALTIMA_AC101 },
47 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101L, MII_STR_ALTIMA_AC101L }, 48 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101L, MII_STR_ALTIMA_AC101L },
48 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C875, MII_STR_ALTIMA_Am79C875 }, 49 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C875, MII_STR_ALTIMA_Am79C875 },
49 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C874, MII_STR_ALTIMA_Am79C874 }, 50 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C874, MII_STR_ALTIMA_Am79C874 },
50 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79C972_10T, MII_STR_yyAMD_79C972_10T }, 51 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79C972_10T, MII_STR_yyAMD_79C972_10T },
51 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c973phy, MII_STR_yyAMD_79c973phy }, 52 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c973phy, MII_STR_yyAMD_79c973phy },
52 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901, MII_STR_yyAMD_79c901 }, 53 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901, MII_STR_yyAMD_79c901 },
53 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901home, MII_STR_yyAMD_79c901home }, 54 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901home, MII_STR_yyAMD_79c901home },
54 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905B, MII_STR_xxBROADCOM_3C905B }, 55 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905B, MII_STR_xxBROADCOM_3C905B },
55 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905C, MII_STR_xxBROADCOM_3C905C }, 56 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905C, MII_STR_xxBROADCOM_3C905C },
56 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5201, MII_STR_xxBROADCOM_BCM5201 }, 57 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5201, MII_STR_xxBROADCOM_BCM5201 },
57 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5214, MII_STR_xxBROADCOM_BCM5214 }, 58 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5214, MII_STR_xxBROADCOM_BCM5214 },
@@ -117,26 +118,27 @@ struct mii_knowndev mii_knowndevs[] = { @@ -117,26 +118,27 @@ struct mii_knowndev mii_knowndevs[] = {
117 { MII_OUI_xxLEVEL1, MII_MODEL_xxLEVEL1_LXT970, MII_STR_xxLEVEL1_LXT970 }, 118 { MII_OUI_xxLEVEL1, MII_MODEL_xxLEVEL1_LXT970, MII_STR_xxLEVEL1_LXT970 },
118 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT971, MII_STR_LEVEL1_LXT971 }, 119 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT971, MII_STR_LEVEL1_LXT971 },
119 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT973, MII_STR_LEVEL1_LXT973 }, 120 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT973, MII_STR_LEVEL1_LXT973 },
120 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT974, MII_STR_LEVEL1_LXT974 }, 121 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT974, MII_STR_LEVEL1_LXT974 },
121 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT975, MII_STR_LEVEL1_LXT975 }, 122 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT975, MII_STR_LEVEL1_LXT975 },
122 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000_OLD, MII_STR_LEVEL1_LXT1000_OLD }, 123 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000_OLD, MII_STR_LEVEL1_LXT1000_OLD },
123 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000, MII_STR_LEVEL1_LXT1000 }, 124 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000, MII_STR_LEVEL1_LXT1000 },
124 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1011, MII_STR_xxMARVELL_E1011 }, 125 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1011, MII_STR_xxMARVELL_E1011 },
125 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_3, MII_STR_xxMARVELL_E1000_3 }, 126 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_3, MII_STR_xxMARVELL_E1000_3 },
126 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_5, MII_STR_xxMARVELL_E1000_5 }, 127 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_5, MII_STR_xxMARVELL_E1000_5 },
127 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E6060, MII_STR_xxMARVELL_E6060 }, 128 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E6060, MII_STR_xxMARVELL_E6060 },
128 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1149, MII_STR_xxMARVELL_E1149 }, 129 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1149, MII_STR_xxMARVELL_E1149 },
129 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1111, MII_STR_xxMARVELL_E1111 }, 130 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1111, MII_STR_xxMARVELL_E1111 },
 131 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1145, MII_STR_xxMARVELL_E1145 },
130 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116, MII_STR_xxMARVELL_E1116 }, 132 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116, MII_STR_xxMARVELL_E1116 },
131 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116R, MII_STR_xxMARVELL_E1116R }, 133 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116R, MII_STR_xxMARVELL_E1116R },
132 { MII_OUI_xxMYSON, MII_MODEL_xxMYSON_MTD972, MII_STR_xxMYSON_MTD972 }, 134 { MII_OUI_xxMYSON, MII_MODEL_xxMYSON_MTD972, MII_STR_xxMYSON_MTD972 },
133 { MII_OUI_MYSON, MII_MODEL_MYSON_MTD803, MII_STR_MYSON_MTD803 }, 135 { MII_OUI_MYSON, MII_MODEL_MYSON_MTD803, MII_STR_MYSON_MTD803 },
134 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83840, MII_STR_xxNATSEMI_DP83840 }, 136 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83840, MII_STR_xxNATSEMI_DP83840 },
135 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83843, MII_STR_xxNATSEMI_DP83843 }, 137 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83843, MII_STR_xxNATSEMI_DP83843 },
136 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83815, MII_STR_xxNATSEMI_DP83815 }, 138 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83815, MII_STR_xxNATSEMI_DP83815 },
137 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83847, MII_STR_xxNATSEMI_DP83847 }, 139 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83847, MII_STR_xxNATSEMI_DP83847 },
138 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83891, MII_STR_xxNATSEMI_DP83891 }, 140 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83891, MII_STR_xxNATSEMI_DP83891 },
139 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83861, MII_STR_xxNATSEMI_DP83861 }, 141 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83861, MII_STR_xxNATSEMI_DP83861 },
140 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83865, MII_STR_xxNATSEMI_DP83865 }, 142 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83865, MII_STR_xxNATSEMI_DP83865 },
141 { MII_OUI_xxPMCSIERRA, MII_MODEL_xxPMCSIERRA_PM8351, MII_STR_xxPMCSIERRA_PM8351 }, 143 { MII_OUI_xxPMCSIERRA, MII_MODEL_xxPMCSIERRA_PM8351, MII_STR_xxPMCSIERRA_PM8351 },
142 { MII_OUI_xxPMCSIERRA2, MII_MODEL_xxPMCSIERRA2_PM8352, MII_STR_xxPMCSIERRA2_PM8352 }, 144 { MII_OUI_xxPMCSIERRA2, MII_MODEL_xxPMCSIERRA2_PM8352, MII_STR_xxPMCSIERRA2_PM8352 },